JPS6257275B2 - - Google Patents

Info

Publication number
JPS6257275B2
JPS6257275B2 JP56135987A JP13598781A JPS6257275B2 JP S6257275 B2 JPS6257275 B2 JP S6257275B2 JP 56135987 A JP56135987 A JP 56135987A JP 13598781 A JP13598781 A JP 13598781A JP S6257275 B2 JPS6257275 B2 JP S6257275B2
Authority
JP
Japan
Prior art keywords
micropin
sheet
pin
blank
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56135987A
Other languages
Japanese (ja)
Other versions
JPS5837979A (en
Inventor
Junpei Suzuki
Fumikazu Oohira
Junji Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56135987A priority Critical patent/JPS5837979A/en
Publication of JPS5837979A publication Critical patent/JPS5837979A/en
Publication of JPS6257275B2 publication Critical patent/JPS6257275B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/80Constructional details
    • H10N60/81Containers; Mountings

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Containers, Films, And Cooling For Superconductive Devices (AREA)

Description

【発明の詳細な説明】 本発明は、超伝導素子実装用マイクロコネクタ
として用いる形状寸法が微小なマイクロピンの加
工法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for processing micro pins with minute dimensions used as micro connectors for mounting superconducting elements.

従来比較的、寸法形状の大きいコネクタの製作
には、ピン間隔が大きく、該各ピン径も太いの
で、切削・転造・プレス打ち抜き等の加工法が適
用されている。
Conventionally, to manufacture connectors with relatively large dimensions and shapes, processing methods such as cutting, rolling, press punching, etc. have been applied because the pin spacing is large and the diameter of each pin is large.

これらの加工法では、本発明の超伝導素子実装
用マイクロコネクタとして用いる微小な寸法形状
のマイクロピンの形成は不可能であり、また実例
もない。
With these processing methods, it is impossible to form micro pins with minute dimensions and shapes used as the micro connector for mounting superconducting elements of the present invention, and there are no examples.

本発明は、マイクロピンのピン座を多角形にし
たことを特徴とし、その目的は、マイクロピンの
ブランクを切削や放電加工を行なうことによりマ
イクロピンの成形を可能にした加工法を提供する
ことにある。
The present invention is characterized in that the pin seat of the micro pin is polygonal, and its purpose is to provide a processing method that makes it possible to form the micro pin by cutting or electrical discharge machining the blank of the micro pin. It is in.

第1図は、本発明の加工法により成形されたピ
ン座が多角形のマイクロピンの一実施例の斜視図
を示すものである。1はピン座が多角形のマイク
ロピン、2はSiフツトないし配線モジユール、2
aは配線パターン、3は該マイクロピン1とSiフ
ツトないし配線モジユール2とを接続するはんだ
バンプである。マイクロピン1の材質は、導電性
のよい素材、たとえば本実施例では白金を用い
た。各部の寸法は、ピン径1aは100μm以下、
マイクロピンの高さ1a′は150〜200μm、ピン座
の辺1bは150〜200μm程度、該ピン座の高さ
1b′は50μm程度と非常に小さい。さらにマイク
ロピン1の配置は、マイクロピン相互の間隔は大
きいところでも1000μmであり、千鳥状に並設し
てあり、一列のマイクロピンの数は60本で二列計
120本で一組を構成する。
FIG. 1 shows a perspective view of an embodiment of a micropin having a polygonal pin seat formed by the processing method of the present invention. 1 is a micro pin with a polygonal pin seat, 2 is a Si foot or wiring module, 2
Reference numeral a represents a wiring pattern, and reference numeral 3 represents a solder bump that connects the micro pin 1 to the Si foot or wiring module 2. The micro pin 1 is made of a material with good conductivity, such as platinum in this embodiment. The dimensions of each part are: pin diameter 1a is 100 μm or less;
The height 1a' of the micro pin is 150 to 200 μm, the side 1b of the pin seat is approximately 150 to 200 μm, and the height of the pin seat is approximately 150 to 200 μm.
1b' is very small, about 50 μm. Furthermore, the micro pins 1 are arranged in such a way that the distance between the micro pins is 1000 μm at most, and they are arranged in a staggered manner, with a total of 60 micro pins in one row and two rows.
One set consists of 120 pieces.

第2図は、本発明の加工法により前記マイクロ
ピン120本を一括で形成した一実施例のブランク
平面図の一部である。1″は白金シート(2点鎖
線で図示)、1′は断面が四辺形のマイクロピンの
ブランク、4は補強板である。5は溝幅であつ
て、該溝の深さは、白金シートの厚さ以上であ
る。
FIG. 2 is a part of a blank plan view of an embodiment in which 120 micropins are formed at once by the processing method of the present invention. 1'' is a platinum sheet (indicated by a two-dot chain line), 1' is a micropin blank with a quadrilateral cross section, and 4 is a reinforcing plate. 5 is a groove width, and the depth of the groove is The thickness is greater than or equal to .

本発明による加工法の一実施例を以下に詳述す
る。
An embodiment of the processing method according to the present invention will be described in detail below.

(1) 補強板4に、マイクロピンの全長に相当する
厚さの白金シート1″を貼り付ける。
(1) Attach a platinum sheet 1″ with a thickness equivalent to the total length of the micro pin to the reinforcing plate 4.

(2) 該白金シート1″の露出面にはんだ(第1図
の3に相当)を蒸着してから、フライス加工な
いし放電加工により溝幅5の溝を穿溝し複数個
のマイクロピンのブランク1′を形成する。
(2) After depositing solder (corresponding to 3 in Figure 1) on the exposed surface of the platinum sheet 1'', a groove with a groove width of 5 is bored by milling or electric discharge machining to form a blank for multiple micro pins. 1' is formed.

(3) あらかじめ、配線パターン2aを描いてある
Siフツトないし配線モジユール2と該マイクロ
ピンのブランク1′の形成された前記白金シー
トのはんだ蒸着面とを対向して位置決めした
後、はんだ付けにより加圧溶着し、しかる後該
補強板4だけを除去する。
(3) Wiring pattern 2a is drawn in advance.
After positioning the silicon foot or wiring module 2 and the solder-deposited surface of the platinum sheet on which the micropin blank 1' is formed to face each other, pressure welding is performed by soldering, and then only the reinforcing plate 4 is bonded. Remove.

(4) 前記、断面が多角形のマイクロピンのブラン
ク1′を植立形成したSiフツトないし配線モジ
ユール2を、第3図に示すピン径1aに相当す
る孔を120ケ所ピツチ精度よく穿孔したシート
状の放電加工電極6を用いて該放電加工電極6
とマイクロピンのブランク1′間に電圧を印加
しつつ該放電加工電極6を下降させて該マイク
ロピンのブランク1′を放電加工することによ
り第1図に示したマイクロピンが形成できる。
もちろん、ピン径1aに相当する内径のパイプ
状電極により単ピンずつ加工する方法でも良
い。
(4) A sheet in which 120 holes corresponding to the pin diameter 1a shown in Fig. 3 are punched with high precision in the Si foot or wiring module 2 on which the micropin blank 1' having a polygonal cross section is planted. The electric discharge machining electrode 6 is
The micropin shown in FIG. 1 can be formed by lowering the electrical discharge machining electrode 6 and electrical discharge machining the micropin blank 1' while applying a voltage between the micropin blank 1' and the micropin blank 1'.
Of course, a method of processing single pins one by one using a pipe-shaped electrode with an inner diameter corresponding to the pin diameter 1a may also be used.

以上説明したように、マイクロピン座の形状が
多角形であることによりマイクロピンのブランク
をフライス加工できるうえに、シリコンフツトな
いし配線モジユールにボンデイングした後、ピン
径加工を行なつているので、マイクロピンのブラ
ンクのピツチ等配置精度をそれ程要しない加工法
上の利点が顕著である。
As explained above, since the shape of the micro pin seat is polygonal, it is possible to mill the micro pin blank, and the pin diameter is processed after bonding to the silicon foot or wiring module. The advantage of this method is that it does not require much precision in the placement of pin blanks, such as the pitch of the pin blanks.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明によるピン座が多角形のマイ
クロピン斜視図、第2図は本発明によるマイクロ
ピンのブランク平面図の一部、第3図は放電加工
の状況を示す斜視図である。 1……マイクロピン、1a……ピン径、1a′…
…ピンの高さ、1b……ピン座の辺、1b′……ピン
座の高さ、1′……マイクロピンのブランク、
1″……白金シート、2……Siフツトないし配線
モジユール、2a……配線パターン、3……はん
だバンプ、4……補強板、5……溝幅、6……放
電加工電極。
FIG. 1 is a perspective view of a micropin with a polygonal pin seat according to the present invention, FIG. 2 is a partial blank plan view of the micropin according to the present invention, and FIG. 3 is a perspective view showing the state of electrical discharge machining. . 1...Micro pin, 1a...Pin diameter, 1a'...
...Pin height, 1b...Pin seat side, 1b'...Pin seat height, 1'...Micro pin blank,
1''...Platinum sheet, 2...Si foot or wiring module, 2a...Wiring pattern, 3...Solder bump, 4...Reinforcement plate, 5...Groove width, 6...Electro discharge machining electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 基板上にあらかじめ定めた形状のマイクロピ
ンを形成するマイクロピンの加工法において、補
強板にマイクロピンの全長に相当する厚さのマイ
クロピン素材からなるシートを貼り付ける第1の
工程と、該シートの露出面にはんだを蒸着した後
フライス加工ないし放電加工により該シート面に
所定の溝幅の溝を形成し、断面が多角形の複数個
のマイクロピンのブランクを形成する第2の工程
と、あらかじめ配線パターンを描いてあるSiフツ
トないし配線モジユールと、前記マイクロピンの
ブランクの形成されたシートのはんだ蒸着面とを
対向して位置決めした後加圧溶着し、しかる後前
記補強板を除去する第3の工程と、前記断面が多
角形のマイクロピンのブランクを植立形成したSi
フツトないし配線モジユールを、マイクロピン径
に相当する開孔を穿孔したシート状電極を用いて
放電加工することにより所定の形状のマイクロピ
ンを形成する第4の工程とからなることを特徴と
する超伝導素子実装用マイクロピンの加工法。
1 In a micropin processing method that forms micropins of a predetermined shape on a substrate, the first step is to attach a sheet made of micropin material with a thickness equivalent to the total length of the micropin to a reinforcing plate, and a second step of depositing solder on the exposed surface of the sheet and then forming grooves with a predetermined groove width on the sheet surface by milling or electrical discharge machining to form blanks for a plurality of micropins having polygonal cross sections; After positioning the Si foot or wiring module on which the wiring pattern has been drawn in advance and the solder-deposited surface of the sheet on which the micropin blank is formed so as to face each other, pressure welding is performed, and then the reinforcing plate is removed. The third step is the Si in which the micropin blank with a polygonal cross section is planted.
a fourth step of forming micro pins of a predetermined shape by subjecting the foot or wiring module to electrical discharge machining using a sheet-like electrode with openings corresponding to the diameter of the micro pins. Processing method for micro pins for mounting conductive elements.
JP56135987A 1981-08-29 1981-08-29 Processing method of super conductive element mounting micro-pin Granted JPS5837979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56135987A JPS5837979A (en) 1981-08-29 1981-08-29 Processing method of super conductive element mounting micro-pin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56135987A JPS5837979A (en) 1981-08-29 1981-08-29 Processing method of super conductive element mounting micro-pin

Publications (2)

Publication Number Publication Date
JPS5837979A JPS5837979A (en) 1983-03-05
JPS6257275B2 true JPS6257275B2 (en) 1987-11-30

Family

ID=15164540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56135987A Granted JPS5837979A (en) 1981-08-29 1981-08-29 Processing method of super conductive element mounting micro-pin

Country Status (1)

Country Link
JP (1) JPS5837979A (en)

Also Published As

Publication number Publication date
JPS5837979A (en) 1983-03-05

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