JPS6256882A - Burst level correcting circuit - Google Patents

Abstract

PURPOSE:To make an output amplitude constant by providing storage areas corresponding to pulses of order constituting a burst signal and specifying corresponding storage area every time an input pulse of order arrives at an address specifying circuit. CONSTITUTION:This circuit is constituted only as shown in a figure where an address specifying circuit 3 and storage areas 41 as many as pulses in the burst are provided, and consequently the circuit operates as if cyclic low-pass filters as many as the pulses in the burst signal were provided. Then, variation in the amplitude of a pulse train proportional to the crest value of a detection pulse train to an adder 2, i.e. high-frequency transmission pulse train is filtered according to low-pass filtering characteristics and appears at the output of the 2nd multiplier in the order of the pulses in the burst signal. Namely, the circuit performs automatic gain control in which negative feedback is provided so that the amplitude of the high-frequency transmission pulses is constant. Consequently, a complex function circuit need not be used to correct a sag phenomenon accurately, and there is no problem due to variation in temperature or source voltage in this case.

Description

[Detailed Description of the Invention] (Industrial Application Field) In a time series of pulses, a portion that includes an extremely large number of pulses exceeding the average number of repetitions is called a burst. The present invention relates to a correction circuit for making constant the output amplitude of an amplifier, particularly a high-frequency pulse amplifier used in a Takan system transponder that transmits direction and distance information to an aircraft.

(Prior Art) In a pulse amplifier, particularly a transponder for a Takan system, the transponder output is amplitude-modulated by a Takan antenna and azimuth information is added.

Therefore, the envelope line formed by the pulse train of the transponder output needs to have a flat level from the viewpoint of azimuth accuracy. However, in general, pulse amplifiers, especially pulse amplifiers using semiconductors, have a duty ratio such as burst pulses.
When amplifying a pulse train with a large value, the gain of the amplifier decreases due to a transient temperature rise at the junction, etc., and a sag phenomenon occurs in the output waveform. When a sag phenomenon occurs, the output amplification of the burst pulse decreases over time as shown in FIG. 6(a), causing the envelope line of the pulse train to be distorted.

In order to correct this distortion, conventionally, a function generation circuit has been used to generate a waveform suitable for correction, thereby performing compensation. A high frequency signal (continuous wave), an example of which is shown in FIG. 5, is input from terminal B, modulated by modulator 302, and then amplified by amplifier 301. The trigger pulse 307 is waveform-shaped by a pulse waveform shaping circuit 305 and then outputted to the modulator 302 as a modulation signal by the variable gain amplifier 304. A burst gate 308 having a width is input to a function generating circuit 306 using a resistor and a capacitor. In this case, the sag phenomenon is compensated by the capacitor charging waveform whose voltage increases over time. That is, the correction waveform increases the gain of the variable gain amplifier 304 over time,
The sag phenomenon caused by the amplifier 301 is corrected by increasing the modulation voltage.

(Problem to be Solved by the Invention) However, the final output corrected as described above is as shown in FIG. 6 (11), and the corrected waveform is not complete in the envelope of the burst portion, and There are the following problems with the technology using a function generating circuit like this. That is, (1) A complicated circuit is required to accurately approximate the sag phenomenon.

(2) This becomes even more difficult when the number of stages of amplifying elements is large in order to obtain a large output.

(3) Although the waveform of the sag phenomenon is also affected by the environmental temperature, it is difficult to make the correction waveform follow this change.

(4) Vulnerable to power supply voltage and other disturbances.

(5) Adjustment takes time.

In view of the above-mentioned problems of the technology using the conventional function generation circuit, an object of the present invention is to control the amplitude of a plurality of pulses constituting a burst with one control signal. By using digital technology, a single circuit can automatically control the focused pulses by focusing on individual pulses within the burst repetition period, treating them as a pulse train that appears at a burst repetition period, and keeping the amplitude of the pulse constant over successive repetition periods. An object of the present invention is to provide a burst level correction circuit that performs configuration.

(Means for Solving the Problems) The present invention has the following configuration to achieve the above object. That is, the burst correction circuit of the present invention includes a memory circuit having a plurality of memory areas to which addresses are given;
In response to a pulse train in which a pulse group consisting of a plurality of pulses appearing at predetermined intervals on the time axis repeatedly appears at a constant period, the memory is predetermined corresponding to the appearance order of each pulse within the pulse group. an addressing circuit that sequentially specifies circuit addresses for reading and writing; a D/A converter that reads data in a storage area at the specified address and converts it into an analog signal;
a first multiplier that multiplies the output of the D/A converter by α (×1) and outputs the multiplier; a high-frequency transmission pulse train modulated by the pulse train and transmitted using the output signal of the multiplier as one input signal; an adder whose other input signal is an amplitude detection pulse proportional to the peak output of each pulse; converts the output of the adder into a digital signal, and converts the digital signal into the signal currently specified by the addressing circuit; an A/D converter that outputs the signal to be stored in a storage area at an address; a second multiplier that multiplies the output signal of the D/A converter by (1-α) and outputs the multiplier; Find the difference between the output amplitude and a predetermined reference level, amplify it as appropriate, and
The present invention is characterized by comprising: a subtraction circuit that outputs a feedback polarity in which the value of the difference becomes smaller to a circuit that controls the peak output level of the high-frequency transmission pulse of the currently arriving order.

(Function) Hereinafter, the function of the burst level correction circuit of the present invention will be explained based on the drawings. The first is a block diagram showing the configuration of the present invention. FIG. 2 is a diagram showing a pulse trigger train having a burst and a burst gate. It is assumed that the burst is repeated at a period T. Assuming that a burst is composed of five pulses, order numbers are assigned from the left to the first pulse, second pulse, . . . , fifth pulse.

Now, if such a pulse trigger is applied to the addressing circuit 3 in FIG. 1, when the first pulse is input, the memory circuit 4
is instructed to read the data stored in the storage area 41 and add it to the D/A converter 5, and then to store the data from the A/D converter 2. When the second pulse comes in, the memory area 42 is instructed to read and write to the memory area 45 when five pulses come in in the same way.

Returning to the beginning of the explanation, when the first pulse is input, the signal read out from the storage area 41 is converted into an analog signal by the D/A converter, and then divided into two directions, one being sent to the first multiplier 6. The signal is multiplied by α (<1) and added to one input terminal of the adder 1. The other input terminal of the adder 1 receives a pulse signal train (referred to as a detection pulse train) that is obtained by partially detecting and amplitude-detecting a high-frequency transmission pulse that has undergone pulse modulation at the same timing as the trigger pulse applied to the addressing circuit 3. )
is entered. Therefore, the detection pulse train and the trigger pulse train coincide in time.

Therefore, when the first pulse is input, first the memory area 4
The data stored in the first multiplier 6 is read out, converted into an analog signal by the D/A converter 5, and the signal is sent to the first multiplier 6.
The signal multiplied by α and the first pulse of the detected pulse train are added by the adder 1, converted to a digital signal by the A/D converter 2, and then stored in the storage area 41 and used for the burst of the next cycle. This state is maintained until the first pulse is input. Next time the second pulse is input, memory area 4
The same operation as described above is performed for the second pulse of the detection pulse train, and the same operation is performed up to the fifth pulse.When a burst of the 0th order period arrives, the same operation as in the above burst is performed. If we look at the above-described operation of the circuit of the present invention with respect to a pulse train in which only the first pulse is taken out, for example, we get the equivalent circuit shown in FIG. This is delayed opening is T
It can be seen that the integrator has a delay circuit 9 of 1 and is a recursive low-pass filter. That is, it is a circuit in which the output follows the amplitude change of a pulse train input having a period T with a time constant that is much longer than the period T.

By providing an addressing circuit and a number of storage areas corresponding to the number of pulses in a burst, the circuit of the present invention can operate the cyclic low-pass filter shown in FIG. 3 within a burst using only the configuration shown in FIG. It performs the same action as if the number of pulses were provided as many as .

Thus, at the output of the second multiplier, changes in the amplitude of the pulse train proportional to the peak value of the detected pulse train, that is, the high-frequency transmission pulse train, are filtered by the low-pass characteristic to the adder 2 according to the order of the pulses within the burst. appear as a result. Then, this output is compared with a common reference voltage for all pulses of the order, and the difference voltage is amplified appropriately, and the peak value of the high frequency transmission pulse modulated by the pulse of the order that has just arrived is calculated. It is applied to the control circuit with a polarity that converges to a constant value. That is, an automatic gain control operation with negative feedback is performed so that the amplitude of the high-frequency transmission pulse is constant, and since the reference voltage is common to each order of pulses, the amplitude of the high-frequency transmission pulse is Although the peak value control is performed separately for each order of pulses, the peak values of the high frequency transmission pulses of all orders become the same.

Since the burst level correction circuit of the present invention operates as described above, there is no need for a complicated function circuit to accurately correct the sag phenomenon, and there is no problem at all even if the number of stages of amplification elements is increased. Even if there are fluctuations in ambient temperature or power supply voltage, automatic gain control is performed to completely compensate for the effects of these changes. No pressure is generated. The only adjustment required is the setting of the reference voltage and the setting of the coefficient α of the multiplier, and since both are independent inputs, they can be easily performed.

FIG. 4 shows a high-frequency transmission burst pulse amplitude-travel circuit using the burst level correction circuit 10 of the present invention.

The difference from the circuit configuration in FIG. 5 is that the gain control of the variable gain amplifier 11 is performed by the output signal of the burst level correction circuit 10. The input signal to the burst level correction circuit 10 is a signal obtained by extracting a part of the high frequency transmission pulse outputted from the amplifier 301 by the detector 13 and peak hold detection proportional to the peak value of the high frequency transmission pulse by the peak hold circuit. is added.

With the above configuration, the gain of the variable gain amplifier 11 is controlled for each order of pulses within a burst, and the gain of the variable gain amplifier 11 is controlled for each order of pulses within a burst.
At the output of 1, the peak values of each pulse become equal.

(Effects of the Invention) As explained above, the burst 12/bell correction circuit of the present invention is provided with a storage area corresponding to each order of pulses constituting the burst, and has the same timing as the burst. 1- By causing the addressing circuit to designate the storage area of the corresponding address each time an input pulse of each order arrives using the rigger pulse, a separate cyclic low-pass filter is provided for the pulse of each order. Therefore, when the circuit of the present invention is used as a feedback circuit of a system having a variable gain circuit to keep the amplitude of high-frequency transmission pulse constant, An automatic gain control function operates to keep the amplitude constant independently for each order of the constituent pulses, and as a result, the peak values of the high-frequency transmission pulses making up the burst are aligned. As described above, since the burst level correction circuit of the present invention enables amplitude-triggering by automatic gain control for each pulse, it is possible to obtain a curve that matches the sag curve as much as possible to correct the sag. Complex function circuits are no longer required, and automatic gain control is performed to compensate for the effects of fluctuations in ambient temperature and power supply voltage, making it easier to use than conventional fixed frequency circuits. There are no problems caused by fluctuations in temperature or power supply voltage. Furthermore, even if the number of amplifier stages increases, it does not adversely affect the automatic gain control operation. Adjustment can be made easily by simply setting the reference voltage and the coefficient of the multiplier, and since both are mutually independent elements.

The burst level correction circuit of the present invention has the following advantages.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a diagram showing a burst pulse trigger train and burst gate, FIG. 3 is a diagram showing an equivalent circuit of the configuration of FIG. 1, and FIG. 4 is a diagram showing the present invention. 5th diagram showing an amplitude-chemotaxis automatic gain control circuit using the circuit
The figure shows a conventional amplitude-taxis circuit using a function generation circuit. Figure 6 shows a burst pulse train. Figure (a) shows a sag phenomenon occurring, and figure (b) shows a function generation circuit. FIG. 3 is a diagram showing a waveform after being corrected by a circuit. 1... Adder, 2... A/D converter, 3... Address designation circuit, 4...
Memory circuit, 41- to 45... memory area, 5...
...D/A converter, 6...First multiplier, 7...Second multiplier, 8...Subtractor, 9... ... Delay circuit 210 ... Burst level correction circuit of the present invention, 1], ... Variable gain amplifier, 12 ... Peak hold circuit, 13 ...・Detector, 301...Amplifier, 302...Modulator, 304...
...Variable gain amplifier, 305...Pulse waveform shaping circuit, 306...Function generation circuit, 307
...Trigger pulse, 308...Purst gate. Agent: Yoshi Yahata, Patent Attorney, Hiroki Haku Moekaiho! Jt-A Fig. 1 Burst-shaped trif-R, +cis and burst case 3
θ2 month - 3 number weighs 2 main 2 [=1) saliva? l 〒Ihe thio leakage Ah-res〔1〇=-7-times occurrence rate, S Figure no\゛-stno\°les sequence Figure C

Claims (1)

[Claims] A memory circuit having a plurality of memory areas to which addresses are given; an addressing circuit that sequentially specifies predetermined addresses of the memory circuit for reading and writing in accordance with the order of appearance of each pulse; reads data in the memory area of the specified address and converts it into an analog signal; a D/A converter that multiplies the output of the D/A converter by α (<1) and outputs the multiplier; the output signal of the multiplier is used as one input signal; an adder whose other input signal is an amplitude detection pulse proportional to the peak output of each pulse of a high-frequency transmission pulse train to be modulated and transmitted; converting the output of the adder into a digital signal; converting the output of the adder into a digital signal; an A/D converter that sends the signal to be stored in the storage area of the address currently specified by the address designation circuit; a second signal that multiplies the output signal of the D/A converter by (1-α) and outputs the signal; a multiplier; calculates the difference between the output amplitude of the multiplier and a predetermined reference level, amplifies it as appropriate, and sends it to a circuit that controls the peak output level of the high-frequency transmission pulse of the currently arriving order. A burst level correction circuit comprising: a subtraction circuit that outputs an output with a feedback polarity in which the value of the difference becomes smaller;