JPS625558B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a horizontal line generator for a test pattern generator that displays a plurality of horizontal bright lines on a display surface of a raster scan display.

Raster scan display devices include television receivers,
It is used in various video equipment such as video monitors. When calibrating these raster scan display devices,
It is convenient to display a test pattern with vertical lines, horizontal lines, or both vertical and horizontal lines on the display surface of the display device. In actual calibration, a standard scale is attached to the display surface and this standard scale is compared with the displayed test pattern to measure linearity, pincushion distortion, convergence, etc.

By the way, different display systems have different number of scanning lines, horizontal active time, and other methods, so
Separate test pattern generators are required for different display systems. That is, if the test pattern generator of one system is used with a raster scan display of another system, the test pattern will not be displayed because the synchronization is different. For systems with different numbers of scan lines per field, the test pattern signal must be changed to display a predetermined number of horizontal lines. Therefore, different display systems require test pattern display devices that are compatible with those systems.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a horizontal line generator for a test pattern generator that can display a predetermined number of horizontal lines on a raster scan display, regardless of the number of scan lines in one frame.

Another object of the present invention is to provide a horizontal line generator for a test pattern generator that generates a test pattern consisting of a desired number of equally spaced horizontal lines.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows an example of a display on a display surface 10 of a raster scan display device. As shown in FIG. 1, the raster scanning display device receives a video signal from the test pattern generator according to the present invention and displays a predetermined number N (an integer) of horizontal bright lines 12. The total number of scanning lines L _T in one field is such that the number of dark lines (not shown) between adjacent horizontal bright lines 12 is M (an integer), and the scanning line at the top of the display surface 10 is the bright line 12. The number of dark lines at the bottom of the display screen is R
(integer), and the number of scanning lines during the vertical erase period is B
(integer), L _T =N+(N-1)M+R+B. According to the present invention, M is automatically adjusted so that R becomes smaller than (N-1) according to a change in the number of scanning lines in one frame, so almost the same test can be performed regardless of the number of scanning lines. - Patterns can be displayed. That is, if R is greater than or equal to (N-1), M increases until R becomes less than (N-1). If the vertical erasing period begins before N horizontal bright lines are displayed, M is set to zero, and after M is set to zero, M is adjusted according to the procedure described below. Therefore, a predetermined number (N) of horizontal bright lines are displayed regardless of the number of scanning lines in one frame. In addition, if B can be changed,
B such that R becomes zero for any number of scanning lines.
Note that it is possible to adjust

FIG. 2 is a block diagram of a test pattern generator having a horizontal line generator according to the present invention.
In FIG. 2, a horizontal synchronizing signal generator 14 generates a horizontal synchronizing signal Hs, whose frequency is controlled by a controller 16.
controlled by. The vertical synchronization and vertical erase signal generator 18 has a plurality of counters (counting means), and outputs a vertical synchronization signal Vs and a vertical erase signal Vb according to the horizontal synchronization signal. Note that the number of scanning lines is controlled by the controller 20. The horizontal line signal generator 22 receives the horizontal synchronization signal and the vertical erase signal, and
Outputs horizontal line signal HL. The output amplifier 24 is
The horizontal and vertical synchronizing signals and the horizontal line signal are mixed and a video signal is output to the terminal 26. The brightness of a horizontal line displayed on a raster scan display is controlled according to the amplitude of the horizontal line signal.

The horizontal line signal generator 22 will be described in detail with reference to FIG. Horizontal synchronization signal Hs is applied to clock terminal CLK of counter 30 via terminal 28. Comparator 32 is the content of counter 30 (C1)
and the contents (C2) of the memory circuit 34, and if the contents of the counter 30 and the memory circuit 34 are equal, a signal is output to the clear terminal CL of the counter 30.
The memory circuit 34 is a type of counter, and receives the clock signal and clear signal from the control logic circuit 36.
Received at clock terminal CLK and clear terminal CL, respectively. The comparator 38 compares the contents of the counter 30 with zero, and the comparator 38 compares the contents of the counter 30 with zero.
If 0 is cleared, one horizontal line output signal is generated in one horizontal active period. Note that the first counting means is composed of a counter 30, a memory circuit 34, and comparators 32 and 38. The horizontal line output signal from the comparator 38 is applied to the output terminal 40 and the clock terminal CLK of the second counting means 42.
Counting means 42 receives a clear signal from control logic circuit 36 at terminal CL. When the second counting means 42 counts a predetermined number N of horizontal line output signals, it outputs a signal to the function circuit 44 which designates the next state, while the function circuit 44 receives the vertical erase signal Vb from the terminal 46. First and second flip-flops (FF1 and FF2) 48, 50 receive set and reset signals, respectively, from control logic circuit 36 and apply a Q output signal to circuit 36. The horizontal synchronization signal applied to the input terminal 28 is applied to the clock terminal CLK of the third counting means 52 and to the state register 54. The third counting means 52 receives an enable signal EN from the control logic circuit 36 and outputs a signal to the control logic circuit 36 every time it counts a predetermined number (N-1) of horizontal synchronization signals. State register 54 receives a signal (3 bits) indicating the next state from function circuit 44 and applies the state signal (3 bits) to control logic circuit 36 and function circuit 44. The control logic circuit 36, the function circuit 44, the flip-flops (FF1, FF2) 48, 50, and the state register 54 constitute control means, and the circuits 36, 44 are a combination of logic gates.

4A and 4B are flowcharts for explaining the operation of the circuit of FIG. 3, and "T" and "F" in the figures indicate "true" and "false", respectively. In step 56, when the contents of the state register 54 are "000", the counter 30 counts the horizontal synchronization signal and the operation of the third counting means 52 is inhibited. At step 58, comparator 32 compares the contents of counter 30 (C1) with the contents of storage circuit 34 (C2);
If C1=C2, comparator 32 clears counter 30 in step 60. In step 62, the comparator 38 determines whether the content (C1) of the counter 30 is zero. If C1 = 0, the comparator 38 generates an output signal (horizontal line (bright line) output signal) in step 64. do. The second counting means 42 is a comparator 38
The second output signal is counted in step 66.
It is determined whether the content (C3) of the counting means 42 is equal to N. Function circuit 44 determines in steps 68 and 70 whether a vertical erase signal is being generated. The above steps are carried out by the third counting means 4.
This is repeated until the content of 2 equals N or a vertical erase signal is generated.

If C3 (the contents of the counting means 42)=N before the vertical erase signal is generated, the contents of the state register 54 change to "001" according to the output of the function circuit 44, and the process moves to step 72. In step 72, the third counting means 52 is enabled by the control logic circuit 36 to which the state signal "001" is applied and counts the horizontal synchronization signals. Also counter 3
0, clears or resets the counting means 42 and flip-flop 50. If the third counting means 52 outputs a signal, that is, if the content (C4) of the third counting means 52 is equal to (N-1) or exceeds (N-1) in step 74, the control logic circuit 36 In step 76, the flip-flop (FF1) 48 is set to "1". This is R(first
(see figure) is too large. At step 78, function circuit 44 determines whether a vertical erase signal has been generated. Steps 72-78 above
is repeated until a vertical erase signal is generated.

In step 70 or 78, the function circuit 44
When it is detected that the vertical erase period has entered, the contents of the state register 54 are changed to "011" by the function circuit 44 (ie, the process moves to step 80). In step 80, control logic circuit 36
resets the second flip-flop (FF2) 50, clears the counter 30 and the second counting means 42 to zero, and when the third counting means 52 does not receive the enable signal, the third counting means 52 cleared. A state in which the contents of the state register 54 are "011" means that M (see FIG. 1) is not very large. When the function circuit 44 detects in step 82 that the vertical erase period has ended, the contents of the state register 54 change to "100" and the process proceeds to step 84.

If the content of the state register 54 is "000" and the vertical erase period starts, if the content (C3) of the second counting means 42 is not equal to N, the state register 54 is cleared through steps 66 and 68.
The content of is “010” according to the operation of the function circuit 44.
Then, the process moves to step 86. At step 86,
The second flip-flop (FF2) 50 is turned to a "1" by control logic 36, indicating that M is very large. Further, in step 86, counter 30, second and third counting means 42, 52, respectively, are cleared by control logic circuit 36. When the function circuit 44 detects the end of the vertical erase period at step 88, the function circuit 44 advances the contents of the state register 54 to "100" (ie, proceeds to step 84).

The procedure for generating a horizontal line output signal when the content of the state register 54 is "100" (steps 84, 90 to 102 in FIG. 4B) is the same as the process for the case of "000" described with respect to FIG. 4A ( Step 5
6 to 70). Steps 98 and 10
2, when the function circuit 44 detects that the content of the second counting means 42 is equal to N (i.e. C3=N) before the start of the vertical erase period, the state register 5 is
The content of 4 changes to "101" (step 104).
At step 104, control logic circuit 36 controls second flip-flop (FF2) 50, counter 30,
Each of the second sensing means 42 is cleared and the third sensing means 52 is enabled. The third counting means 52 is
Count R in units of 1/(N-1). In step 106, the control logic circuit 36 determines whether the content (C4) of the third counting means 52 is equal to or greater than (N-1) (that is, whether the third counting means 52 is outputting a signal). to judge. Furthermore,
Control logic circuit 36 determines in step 108 whether the content of first flip-flop (FF1) 48 is "1". If the content (C4) of the third counting means 52 is equal to or greater than (N-1) and FF1 is "1", the control logic circuit 36
At step 110, a clock pulse is applied to the clock terminal of the memory circuit 34 every (N-1) scan lines. When the function circuit 44 detects in step 112 that the vertical erase period has entered, the contents of the state register 54 change to "111" in step 114.

In step 114, control logic circuit 36
Before the cycle completes, the flip-flops (FF1) 48, (FF2) 50, and the first counter 3
0, the second and third counting means 42, 52 are reset to zero. Note that when the vertical erase period ends in step 116, the contents of the state register 54 return to "000".

When the content of the state register 54 is "100" and the vertical erase period has started, the second counting means 42
If the contents of (C3) are not equal to N, the contents of state register 54 becomes "110" (step 118) via steps 98 and 100, and control logic circuit 36 causes flip-flop (FF1) 48,
Counter 30, second and third counting means 42, 52
Reset to zero. In step 120,
When control logic circuit 36 detects that flip-flop (FF2) 50 is already set, storage circuit 34 is cleared in step 122. Further, when the vertical erase period ends in step 124, the contents of state register 54 return to the state of step 56, ie, "000".

After that, the above operation is repeated until a predetermined number (N)
horizontal lines are displayed on a raster scan display at equal intervals.

As is clear from the above description, the horizontal line generator of the present invention can generate a test pattern signal consisting of a desired number of equally spaced horizontal lines, regardless of the number of scanning lines in one field.

Although the preferred embodiments of the present invention have been described above, it will be easy for those skilled in the art to make modifications to the present invention without departing from the gist of the present invention. For example, control logic circuit 36, function circuit 44, state register 54, flip-flops 48, 5
The control means consisting of 0 may be replaced by a so-called microprocessor. Furthermore, the number of scanning lines (B) during the vertical erase period is determined by the vertical synchronization and vertical erase signal generator 1.
8, and in this case, it is possible to set R to zero. The present invention can be applied to both progressive scanning and interlaced scanning. Furthermore, the width of the horizontal bright line can be controlled by adjusting the clear period of counter 30. Furthermore, it is also possible to reverse the polarity of the output of the horizontal line generator of the invention,
The first counting means can also be a programmable counter.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a display of a raster scan display device, FIG. 2 is a block diagram of a test pattern generator having a horizontal line generator of the present invention, and FIG. 3 is a block diagram of a preferred embodiment of the present invention. 4A and 4B are flowcharts for explaining the operation of the embodiment of FIG. 3. 30, 32, 34, 38...first counting means, 42
...Second counting means, 52...Third counting means, 36, 4
4, 48, 50, 54...control means.

Claims (1)

[Claims] 1. In a test pattern generation device for displaying a plurality of horizontal lines on a display surface of a raster scanning display device, a first counting means for counting horizontal synchronization signals and generating a horizontal line output signal every time a first predetermined number is reached;
a second counting means for counting the horizontal line output signal from the first counting means and outputting a signal when a second predetermined number is reached; and after the second counting means outputs the signal;
a third counting means for counting the horizontal synchronizing signal until a vertical erasing signal is generated; and a third counting means for counting the horizontal synchronizing signal until a vertical erasing signal is generated; control means for decreasing the first predetermined number by one predetermined number and increasing the first predetermined number of the first counting means if the content of the third counting means is larger than the third predetermined number at the time when the vertical erase signal is generated; A horizontal line generator for a test pattern generator, characterized in that the second predetermined number of horizontal lines is displayed on the raster scanning display device regardless of the number of scanning lines in one field.