JPS6255156B2 - - Google Patents

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Publication number
JPS6255156B2
JPS6255156B2 JP52155115A JP15511577A JPS6255156B2 JP S6255156 B2 JPS6255156 B2 JP S6255156B2 JP 52155115 A JP52155115 A JP 52155115A JP 15511577 A JP15511577 A JP 15511577A JP S6255156 B2 JPS6255156 B2 JP S6255156B2
Authority
JP
Japan
Prior art keywords
signal
output
analog
character
deformation rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52155115A
Other languages
Japanese (ja)
Other versions
JPS5487122A (en
Inventor
Kenji Kono
Masao Akyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15511577A priority Critical patent/JPS5487122A/en
Publication of JPS5487122A publication Critical patent/JPS5487122A/en
Publication of JPS6255156B2 publication Critical patent/JPS6255156B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は変形文字信号発生回路に係り、とくに
デイスプレイ装置や記録装置などのCRT(陰極
線管)に変形文字を出力する場合に適用して好適
な変形文字信号発生回路に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modified character signal generation circuit, and particularly to a modified character signal generation circuit suitable for outputting modified characters to a CRT (cathode ray tube) such as a display device or a recording device. Related.

近時、写真植字の高速化、自動化等を目指し
て、CRTを使用した電算写植が実施されてい
る。この電算写植において変形文字を作るには、
CRTビームの偏向位置を文字中心が基点になる
仮想座標系における正体文字各輝点の座標x,y
から、たとえば一次変換した座標X,Yへ変更す
るようにしている。このときのCRTビームの偏
向を制御する信号を発生する回路は変形文字信号
発生回路と呼ばれることがある。
Recently, computer typesetting using CRTs has been implemented with the aim of speeding up and automating phototypesetting. To create modified characters in this computer typesetting,
The deflection position of the CRT beam is determined by the coordinates x, y of each bright spot of the true character in the virtual coordinate system whose base point is the center of the character.
For example, the coordinates are changed to linearly transformed coordinates X and Y. The circuit that generates the signal that controls the deflection of the CRT beam at this time is sometimes called a modified character signal generation circuit.

ところで、従来の変形文字信号発生回路では前
記正体文字各輝点の座標x,yに対して、次式で
表わされる如き演算又は変換を行なつて新座標
X,YにCRTビームを偏向させていた。
By the way, in the conventional deformed character signal generation circuit, the CRT beam is deflected to the new coordinates X, Y by performing calculations or conversions as shown in the following equation for the coordinates x, y of each bright spot of the original character. Ta.

X=1/2{k1(x+y)+k2(x−y)} Y=1/2{k1(x+y)−k2(x−y} すなわち、従来の変形文字信号発生回路を用
い、かつ係数k1,k2が1となるよう指令する場合
は、変形のない正体文字をCRTに出力できるよ
う理論的にはなつている。
X=1/2{k 1 (x+y)+k 2 (x-y)} Y=1/2{k 1 (x+y)-k 2 (x-y} In other words, using the conventional modified character signal generation circuit, In addition, if the coefficients k 1 and k 2 are instructed to be 1, it is theoretically possible to output the original character without any deformation to the CRT.

しかしながら、このような演算はアナログ的に
行なわれることが多く、そのため精度が悪く前記
係数k1,k2が1となるよう指令しても従来回路で
は正体文字から少し変形した文字が出力される欠
点があつた。
However, such calculations are often performed in an analog manner, and as a result, the accuracy is poor, and even if the coefficients k 1 and k 2 are instructed to be 1, conventional circuits output characters that are slightly deformed from the original characters. There were flaws.

また、前記演算を全てデジタル的に行なうこと
もでき、この場合は精度の問題は回避されるが、
回路構成が複雑になると共に高価になる欠点があ
つた。
It is also possible to perform all of the above calculations digitally, in which case the accuracy problem is avoided, but
The disadvantage was that the circuit configuration was complicated and expensive.

かくして本発明は前記欠点の除去を目的として
おり、X=Ax+BPy,Y=AQx+By(A,B,
P,Qは変形率)なる変換式に基づく演算がなさ
れるデジタル・アナログ演算回路の組合せで構成
した変形文字信号発生回路によりこの目的を達成
するもので、以下その実施例を図面に従つて詳細
に説明する。
Thus, the present invention is aimed at eliminating the above-mentioned drawbacks, and is based on the following: X=Ax+BPy, Y=AQx+By(A, B,
This purpose is achieved by a deformed character signal generation circuit composed of a combination of digital and analog arithmetic circuits that performs calculations based on a conversion formula (P, Q are deformation rates), and an embodiment thereof will be described in detail below according to the drawings. Explain.

第1図は本発明が適用される写植における表示
部のブロツク図である。図中、MEMOはパター
ンメモリ;CNLは制御装置;DEF1は主偏向回
路;DEF2は副偏向回路;LGTは輝度制御回
路;ADはアナログ加算回路;CRTは陰極線管で
ある。
FIG. 1 is a block diagram of a display section in phototypesetting to which the present invention is applied. In the figure, MEMO is a pattern memory; CNL is a control device; DEF1 is a main deflection circuit; DEF2 is a sub-deflection circuit; LGT is a brightness control circuit; AD is an analog addition circuit; CRT is a cathode ray tube.

この表示部においては、図示の如く、まず制御
装置CNLに偏向制御信号(主偏向制御信号、変
形制御信号)とパターンメモリMEMOからの文
字パターンが入力される。制御装置CNLは主偏
向回路DEF1を制御して、CRTに表示すべき文
字の位置指定を該主偏向回路DEF1に行なわ
せ、副偏向回路DEF2を制御して文字パターン
の各ドツトの文字中心からの変位に応じた位置指
定を該副偏向回路DEF2に行なわせ、輝度制御
回路LGTを制御して輝度の調節を該輝度制御回
路LGTに行なわせている。前記主偏向回路DEF
1と副偏向回路DEF2との出力はアナログ加算
回路ADにより合成されてCRTの偏向コイルに送
出される。この結果CRT上には指定された位置
に文字が表示される。
In this display section, as shown in the figure, first, a deflection control signal (main deflection control signal, deformation control signal) and a character pattern from the pattern memory MEMO are input to the control device CNL. The control device CNL controls the main deflection circuit DEF1 to specify the position of the character to be displayed on the CRT, and controls the sub-deflection circuit DEF2 to specify the position of the character to be displayed on the CRT. The sub-deflection circuit DEF2 specifies the position according to the displacement, and controls the brightness control circuit LGT to adjust the brightness. Main deflection circuit DEF
1 and the outputs of the sub-deflection circuit DEF2 are combined by an analog adder circuit AD and sent to the deflection coil of the CRT. As a result, characters are displayed at the specified position on the CRT.

本発明は以上の構成である場合は副偏向回路
DEF2として用いられ、詳しくは第2図におい
て説明する。
When the present invention has the above configuration, the sub-deflection circuit
It is used as DEF2 and will be explained in detail in FIG.

第2図は前記副偏向回路DEF2として用いら
れ、本発明に係る変形文字信号発生回路のブロツ
ク図であり、白矢印はたとえば2進コードで構成
されたデジタル信号を示し、黒矢印はアナログ信
号を示している。図中、11,21はデジタル入
力信号をアナログ信号に変換するデジタル・アナ
ログ変換回路(以下DAと呼ぶ);12,13,
22,23は前段のアナログ出力とデジタル信号
とを入力し、それぞれのアナログ量とデジタル値
との積に等しいアナログ量の出力信号を発生する
乗算型デジタル・アナログ変換回路(以下乗算型
DAと呼ぶ);14,24は前段の2つの乗算型
DAのアナログ出力を加算したアナログ量の出力
信号を発生する加算回路である。
FIG. 2 is a block diagram of a modified character signal generation circuit according to the present invention, which is used as the sub-deflection circuit DEF2, where white arrows indicate digital signals composed of, for example, binary codes, and black arrows indicate analog signals. It shows. In the figure, 11, 21 are digital-to-analog conversion circuits (hereinafter referred to as DA) that convert digital input signals to analog signals; 12, 13,
22 and 23 are multiplying type digital-to-analog conversion circuits (hereinafter referred to as multiplication type) that input the analog output and digital signal of the previous stage and generate an output signal of an analog quantity equal to the product of each analog quantity and digital value.
(referred to as DA); 14 and 24 are the two multiplication types in the previous stage
This is an addition circuit that generates an analog output signal by adding the analog outputs of the DA.

動作について説明すると、まず、デジタル値の
前記変形率A,Bを含む指令信号Sx,Syがそれ
ぞれDA11,21に入力されてアナログ量の信
号になる。
To explain the operation, first, command signals Sx and Sy containing the deformation rates A and B in digital values are input to the DAs 11 and 21, respectively, and become signals in analog quantities.

変換されたこれらアナログ量の信号は乗算型
DA12,22にそれぞれ入力される。一方、該
乗算型DA12,22には文字中心からの各輝点
の座標x,yがそれぞれデジタル的信号△x,△
yで入力されていて、従つて、これらの乗算型
DA12,22からは積A・x,B・yにそれぞ
れ等しいアナログ量の出力信号が発せられる。次
にこれら積A・x,B・yに等しいアナログ量の
出力信号は、それぞれ次段の乗算型DA13,2
3に入力される。このとき該乗算型DA13,2
3は変形率Q,Pを含む指令信号By,Bxも同時
にそれぞれ入力している。この結果、これら乗算
型DA13,23からは夫々積Q・(A・x),
P・(B・y)に等しいアナログ量の出力信号が
得られる。
The converted signals of these analog quantities are multiplicative
The signals are input to DA12 and DA22, respectively. On the other hand, the coordinates x and y of each bright spot from the center of the character are stored in the multiplication type DAs 12 and 22 as digital signals △x and △, respectively.
y, and therefore these multiplication types
The DAs 12 and 22 output analog output signals equal to the products A.x and B.y, respectively. Next, output signals of analog quantities equal to these products A x and B
3 is input. At this time, the multiplication type DA13,2
3, command signals By and Bx including deformation rates Q and P are also input at the same time, respectively. As a result, the products Q・(A・x),
An analog quantity output signal equal to P.(B.y) is obtained.

さて、このようにして乗算型DA12,13,
22,23から出力されたそれぞれAx,BQx,
By,BPyの積に等しいアナログ量の信号は、加
算回路14で和Ax+BPyに、加算回路24で和
AQx+Byに等しいアナログ量すなわち、文字中
心からの正体文字各輝点の座標x,yに対して一
次変換した座標X,YにCRTビームを偏向させ
るための変形文字信号△Xa,△Yaになるように
加算されて出力される。
Now, in this way, multiplication type DA12, 13,
Ax, BQx, output from 22 and 23, respectively
The analog quantity signal equal to the product of By and BPy is added to the sum Ax+BPy by the adder circuit 14 and summed by the adder circuit 24.
Analog quantities equal to AQx + By, that is, transformed character signals △Xa, △Ya for deflecting the CRT beam to coordinates is added to and output.

以上の説明のようにこの変形文字信号発生回路
は文字中心からの正体文字各輝点の座標x,yに
対して一次変換した座標X,YにCRTビームを
偏向させる信号、すなわち変形文字信号△Xa,
△Yaを発生している。また、この一次変換は以
下の式で表わすことができる。
As explained above, this deformed character signal generation circuit generates a signal that deflects the CRT beam to coordinates Xa,
△Ya is occurring. Moreover, this linear transformation can be expressed by the following equation.

X=Ax+BPy Y=AQx+By そこで、変形率P,Qを共に0としA,Bを共
に1とするときには、変形のない正体文字が得ら
れる。そして、このときは、各基軸方向成分、た
とえば水平方向成分の座標値Xを得るために、単
に垂直方向成分yを消去している。従つて、従
来、垂直成分yを互いに極性の反対なものどうし
を加算し、相殺するのに比較し、極めて簡単かつ
精度よく垂直成分yの消去が行なわれ、同様に他
の方向成分についても同じであり、正確な正体文
字を得ることができる。
X=Ax+BPy Y=AQx+By Therefore, when the deformation rates P and Q are both 0 and A and B are both 1, a normal character without deformation is obtained. At this time, the vertical component y is simply deleted in order to obtain the coordinate value X of each base axis component, for example, the horizontal component. Therefore, compared to the conventional method of adding vertical components y with opposite polarities and canceling them out, the vertical component y can be eliminated very easily and accurately, and the same can be done for other directional components as well. , it is possible to obtain the correct true character.

次に第3図、第4図において、第2図に用いら
れた乗算型DAの具体的構成の一例を説明する。
Next, referring to FIGS. 3 and 4, an example of a specific configuration of the multiplication type DA used in FIG. 2 will be explained.

第3図において、R,2R,4R,8R……2
n-1Rはそれぞれ重味も付した抵抗;S1,S2,S3
S4……Soはスイツチ;T1,T2,T3,T4……To
はデジタル入力信号B1,B2,B3,B4……Boの入
力端子;Tはアナログ入力信号VRが入力される
基準電圧入力端子;OAは演算増幅器;RFは抵
抗;T0は出力e0を送出する出力端子である。
In Figure 3, R, 2R, 4R, 8R...2
n-1R is a weighted resistance; S 1 , S 2 , S 3 ,
S 4 ...S o is a switch; T 1 , T 2 , T 3 , T 4 ... T o
is the input terminal of the digital input signals B 1 , B 2 , B 3 , B 4 ...B o ; T is the reference voltage input terminal into which the analog input signal V R is input; OA is the operational amplifier; R F is the resistor; T 0 is the output terminal that sends out the output e 0 .

この乗算型D/Aでは抵抗R,2R,4R……
はそれぞれ重味を持つているので、流れる電流も
それぞれ重味を持つのである。そして出力e0は次
式となる。
In this multiplication type D/A, resistors R, 2R, 4R...
Since each has its own weight, the flowing current also has its own weight. And the output e 0 is given by the following formula.

e0=VR・R/R{B1・2゜+B2・2-1+B3 ・2-2+B4・2-3+……Bo・2-o+1} 但し、B1,B2……をBiとするときBi=1また
は0となる。ところで、第3図々示の構成では、
入力されるデジタル値は正又は負のいずれかに限
定されてしまうので、本発明では必要に応じて正
負両値のデジタル入力可能な乗算型DA、たとえ
ば第4図々示の構成の乗算型DAを用いている。
e 0 = V R・R F /R {B 1・2゜+B 2・2 -1 +B 3・2 -2 +B 4・2 -3 +...B o・2 -o+1 } However, B 1 , B 2 . . . as B i, B i =1 or 0. By the way, in the configuration shown in Figure 3,
Since the input digital value is limited to either positive or negative, the present invention uses a multiplication type DA that can input both positive and negative values digitally, for example, a multiplication type DA having the configuration shown in FIG. 4. is used.

第4図において、30はアナログ入力信号
ANLとデジタル入力信号のDGTの絶対値分のデ
ジタル信号ABSとを入力する第3図々示のよう
な乗算型DA;31は前記デジタル入力信号DGT
より絶対値分のデジタル信号ABSと符号(正又
は負)ビツトの信号SNと零値の信号ZRとを得る
デコーダ回路;32は正転アンプ;33は反転ア
ンプ;SW1,SW2はスイツチである。
In Figure 4, 30 is an analog input signal
A multiplication type DA as shown in FIG. 3 which inputs ANL and a digital signal ABS corresponding to the absolute value of the digital input signal DGT; 31 is the digital input signal DGT.
A decoder circuit that obtains a digital signal ABS for the absolute value, a sign (positive or negative) bit signal SN, and a zero value signal ZR; 32 is a normal amplifier; 33 is an inverting amplifier; SW 1 and SW 2 are switches. be.

この乗算型DAでは、入力されるデジタル値
が、正値、零値、負値によつてスイツチSW1はプ
ラス側P、プラス側P、マイナス側Mに切換えら
れ、スイツチSW2は導通、開放、導通となる。従
つて、前記デジタル値DGTが正値ならば、正転
アンプ32の出力、すなわち極性が反転されない
出力が得られ、負値ならば反転アンプ33の出
力、すなわち極性が反転された出力が得られ、更
に零値ならば出力OUTは零となるようになつい
る。
In this multiplication type DA, switch SW 1 is switched to the plus side P, plus side P, or minus side M depending on whether the input digital value is a positive value, zero value, or negative value, and switch SW 2 is switched on or off. , becomes conductive. Therefore, if the digital value DGT has a positive value, the output of the non-rotating amplifier 32, that is, the output whose polarity is not inverted, is obtained, and if it has a negative value, the output of the inverting amplifier 33, that is, the output whose polarity is inverted, is obtained. , furthermore, if the value is zero, the output OUT will become zero.

尚、前記デコーダ回路31は制御装置CNLの
内部に設けることもできる。
Incidentally, the decoder circuit 31 can also be provided inside the control device CNL.

第5図は本発明により得られた印字例であり、
文字の大部分の輝点が基点0を中心に右回りに回
転している右斜体変形文字a,dと逆に左回りに
回転している左斜体変形文字b,cとを示してい
る。また、これらの変形文字は元の正体文字を点
線で示す正方形領域に有していて、変形されたと
きに該正方形領域に含まれる平行四辺形領域に表
示されるようになつている。
FIG. 5 is an example of printing obtained by the present invention,
The right italic modified characters a and d, in which most of the bright spots of the characters rotate clockwise around the base point 0, and the left italic modified characters b and c, in which the bright spots of most of the characters rotate counterclockwise, are shown. Further, these modified characters have the original original characters in a square area indicated by a dotted line, and when transformed, they are displayed in a parallelogram area included in the square area.

このような変形文字は前記変形率が以下のよう
に指令することにより得られる。
Such deformed characters can be obtained by instructing the deformation rate as follows.

aの場合 A=1−P,B=1,P>0,Q=0 bの場合 A=1+P,B=1,P<0,Q=0 cの場合 A=1,B=1−Q,P=0,Q>0 dの場合 A=1,B=1+Q,P=0,Q<0 以上の説明でわかるように本発明によれば、
種々の斜体変形文字を簡単な回路構成で得られる
他、正体文字も演算の一部がアナログ的に行なわ
れるにも拘わらず、正確な字形で得ることができ
る。
In the case of a, A=1-P, B=1, P>0, Q=0 In the case of b, A=1+P, B=1, P<0, Q=0 In the case of c, A=1, B=1-Q , P=0, Q>0 In the case of d A=1, B=1+Q, P=0, Q<0 As can be seen from the above description, according to the present invention,
In addition to being able to obtain various italicized characters with a simple circuit configuration, the original characters can also be obtained in accurate shapes even though some of the calculations are performed in an analog manner.

尚、本発明は第3図又は第4図々示に乗算型
DAを用いるのに限定されず、また写植以外の
CRTを用いた装置にも適用することができる。
更に、長体や平体等の単に縦横方向にのみ変形し
た文字も得ることができるのは明白である。
In addition, the present invention is a multiplication type shown in FIG. 3 or 4.
Not limited to using DA, and other than phototypesetting
It can also be applied to devices using CRT.
Furthermore, it is obvious that characters deformed only in the vertical and horizontal directions, such as long and flat characters, can also be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明が適用できる写植装置の表示部
のブロツク図、第2図は本発明に係る変形文字信
号発生回路のブロツク図、第3図、第4図は乗算
型DAの構成例を示す図、第5図は本発明による
印字出力例を示す図である。 DEF1……主偏向回路、DEF2……副偏向回
路、AD……アナログ加算回路、CRT……陰極線
管、11,21……デジタル・アナログ変換回路
(DA)、12,13,22,23……乗算型デジ
タル・アナログ変換回路(乗算型DA)、14,2
4……加算回路、△X,△Y……文字に対応した
デジタル信号、Sx,Sy,Bx,By……デジタル値
の変形率が含まれる指令信号、△Xa,△Ya……
変形文字信号、OA……演算増幅器、SW1,SW2
……スイツチ、32……正転アンプ、33……反
転アンプ。
FIG. 1 is a block diagram of a display unit of a phototypesetting apparatus to which the present invention can be applied, FIG. 2 is a block diagram of a modified character signal generation circuit according to the present invention, and FIGS. 3 and 4 show an example of the configuration of a multiplication type DA. The figure shown in FIG. 5 is a diagram showing an example of print output according to the present invention. DEF 1 ...Main deflection circuit, DEF 2 ...Sub deflection circuit, AD...Analog addition circuit, CRT...Cathode ray tube, 11, 21...Digital-to-analog conversion circuit (DA), 12, 13, 22, 23 ... Multiplying digital-to-analog conversion circuit (multiplying DA), 14,2
4...Addition circuit, △X, △Y...Digital signals corresponding to characters, Sx, Sy, Bx, By...Command signals containing transformation rates of digital values, △Xa, △Ya...
Modified character signal, OA... operational amplifier, SW 1 , SW 2
...Switch, 32...Normal amplifier, 33...Inverting amplifier.

Claims (1)

【特許請求の範囲】 1 CRTに出力される各文字の中心が基点にな
る仮想の直交座標系を設け、正体文字各輝点の座
標x,yに対応した偏向信号(△X,△Y)と変
形率A,B,P,Q(A,B,P,Qは実数)と
を入力し、X=Ax+BPy,Y=AQx+Byなる座
標X,Yに前記各輝点を移動する如くして、X軸
又はY軸のいずれか一方の軸方向に平行に斜行し
た変形文字信号を出力する変形文字信号発生装置
であつて、 前記変形文字信号を発生する手段は、前記偏向
信号と変形率とを入力して乗算し、積Ax,Byに
比例した信号を出力する第1の乗算手段と; 第1の乗算手段の出力信号と変形率とを入力し
て乗算し、積AQx,BPyに比例した信号を出力す
る第2の乗算手段と; 第1及び第2の乗算手段の出力信号を入力し、
和Ax+BPy,AQx+Byに比例した前記変形文字
信号を出力する加算手段と;より構成され、 入力される前記偏向信号と変形率とをデジタル
値となし、前記第1の乗算手段として変形率のデ
ジタル値をアナログ量に変換し、該アナログ量と
偏向信号のデジタル値とを乗算したアナログ出力
を発生するデジタル・アナログ演算回路1対を用
い、 更に前記第2の乗算手段として該デジタル・ア
ナログ演算回路のそれぞれからの出力と別の変形
率のデジタル値とを乗算したアナログ乗算回路1
対と、 その出力を該変形率のデジタル値の付号ビツト
によつて正負反転する回路とを用いたことを特徴
とする変形文字信号発生装置。
[Claims] 1. A virtual orthogonal coordinate system is provided in which the center of each character output to the CRT is the base point, and deflection signals (△X, △Y) corresponding to the coordinates x, y of each bright spot of the real character are provided. and the deformation rates A, B, P, Q (A, B, P, Q are real numbers), and move each bright point to the coordinates X, Y where X=Ax+BPy, Y=AQx+By, A deformed character signal generating device that outputs a deformed character signal diagonally parallel to either the X-axis or the Y-axis, wherein the means for generating the deformed character signal combines the deflection signal and the deformation rate. a first multiplier that inputs and multiplies and outputs a signal proportional to the product Ax, By; inputs and multiplies the output signal of the first multiplier by the deformation rate, and outputs a signal proportional to the product AQx, BPy; a second multiplication means for outputting a signal; inputting the output signals of the first and second multiplication means;
an addition means for outputting the deformed character signal proportional to the sum Ax + BPy, AQx + By; the input deflection signal and the deformation rate are converted into digital values, and the first multiplication means outputs the digital value of the deformation rate; using a pair of digital/analog arithmetic circuits that converts into an analog quantity and generates an analog output obtained by multiplying the analog quantity by the digital value of the deflection signal; Analog multiplication circuit 1 that multiplies the output from each by a digital value of another deformation rate.
1. A deformed character signal generating device characterized by using a pair of deformed character signals, and a circuit for inverting the positive and negative of the output thereof according to the sign bit of the digital value of the deformation rate.
JP15511577A 1977-12-23 1977-12-23 Production system of modified character signal Granted JPS5487122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15511577A JPS5487122A (en) 1977-12-23 1977-12-23 Production system of modified character signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15511577A JPS5487122A (en) 1977-12-23 1977-12-23 Production system of modified character signal

Publications (2)

Publication Number Publication Date
JPS5487122A JPS5487122A (en) 1979-07-11
JPS6255156B2 true JPS6255156B2 (en) 1987-11-18

Family

ID=15598905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15511577A Granted JPS5487122A (en) 1977-12-23 1977-12-23 Production system of modified character signal

Country Status (1)

Country Link
JP (1) JPS5487122A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167081A (en) * 1981-04-08 1982-10-14 Nippon Electric Co Character pattern generator
JPS6173991A (en) * 1984-09-20 1986-04-16 株式会社 モリサワ Display method and apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5062329A (en) * 1973-10-01 1975-05-28
JPS5062330A (en) * 1973-10-01 1975-05-28

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5062329A (en) * 1973-10-01 1975-05-28
JPS5062330A (en) * 1973-10-01 1975-05-28

Also Published As

Publication number Publication date
JPS5487122A (en) 1979-07-11

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