JPS6253832U

JPS6253832U -

Info

Publication number: JPS6253832U
Application number: JP14473285U
Authority: JP
Priority date: 1985-09-20
Filing date: 1985-09-20
Publication date: 1987-04-03

Description

[Brief explanation of drawings]

第１図はこの考案に係る固体継電器の一例を示
す電気回路図、第２図Ａ〜Ｃは同固体継電器の要
部の信号波形図、第３図は同固体継電器の入力制
御方法の一例の説明図、第４図は同固体継電器の
スイツチング回路の変形例を示す電気回路図、第
５図は従来の固体継電器の構成図、第６図は従来
の固体継電器の入力制御方法の一例の説明図であ
る。１……入力信号回路、２……負荷回路、Ｉ_１，
Ｉ_２……入力端子、Ｅ……電源、ＲＬ……負荷、
Ｑ……半導体スイツチング素子、ＴＣ……トリガ
回路、ＳＣ……スイツチング回路、ＩＧ……積分
回路、ＤＶ……分圧回路。 Fig. 1 is an electric circuit diagram showing an example of the solid state relay according to this invention, Figs. 2 A to C are signal waveform diagrams of the main parts of the solid state relay, and Fig. 3 is an example of the input control method of the solid state relay. 4 is an electric circuit diagram showing a modification of the switching circuit of the solid state relay, FIG. 5 is a configuration diagram of a conventional solid state relay, and FIG. 6 is an explanation of an example of an input control method of a conventional solid state relay. It is a diagram. 1...Input signal circuit, 2...Load circuit, _I1 ,
_I2 ...Input terminal, E...Power supply, RL...Load,
Q...Semiconductor switching element, TC...Trigger circuit, SC...Switching circuit, IG...Integrator circuit, DV...Voltage dividing circuit.

Claims

[Claims for Utility Model Registration] (1) An input signal circuit having a pair of input terminals;
A load circuit having a semiconductor switching element connected in series to a power supply via a load, a trigger circuit located before the load side and triggering the semiconductor switching element in an activated state, and a trigger circuit located before the trigger circuit. a switching circuit that is electrically isolated from the input signal circuit and sets the trigger circuit inactive when an input signal is applied. (2) The switching circuit has a first transistor that turns on in response to the application of an input signal and a second transistor that sends a trigger signal to the trigger circuit in response to the first transistor. An integrator circuit that delays the trigger input is provided on the front stage side, and a voltage divider circuit that sets the operating point of the second transistor to a level higher than the operating point of the trigger circuit when no input signal is applied is connected to the second transistor _T2 . A solid state relay according to claim 1 of the utility model registration claim, which is provided on the base side.