JPS6253540A - Malfunction detecting circuit for frame buffer memory circuit - Google Patents
Malfunction detecting circuit for frame buffer memory circuitInfo
- Publication number
- JPS6253540A JPS6253540A JP60194503A JP19450385A JPS6253540A JP S6253540 A JPS6253540 A JP S6253540A JP 60194503 A JP60194503 A JP 60194503A JP 19450385 A JP19450385 A JP 19450385A JP S6253540 A JPS6253540 A JP S6253540A
- Authority
- JP
- Japan
- Prior art keywords
- buffer memory
- frame buffer
- frame
- malfunction
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
本発明は、フレームバッファメモリ回路（ＦＢＭ）に係
り特に、これが誤動作したことを検出する誤動作検出回
路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame buffer memory circuit (FBM), and particularly to a malfunction detection circuit for detecting malfunction of the frame buffer memory circuit (FBM).
従来、ＦＢＭが正常に動作しているかどうかの確認には
、人間による目視によっていたが、これには工数がかか
る、確認の確度がよくないなどの欠点がある。Conventionally, whether or not the FBM is operating normally has been confirmed by human visual inspection, but this has disadvantages such as requiring a lot of man-hours and the accuracy of confirmation is not good.
本発明目的は、ＦＢＭの誤動作を電気的に検出すること
によって、ＦＢＭの動作状態を正確かつ迅速に把握する
回路を提供するにある。An object of the present invention is to provide a circuit that can accurately and quickly grasp the operating state of an FBM by electrically detecting a malfunction of the FBM.
本発明は、このためＦＢＭが誤動作しはじめたときにフ
レームヘッダパターンが所定のタイムスロットに現れな
くなることを検出する様にした、以下図に従って、説明
を行う。For this reason, the present invention detects that the frame header pattern does not appear in a predetermined time slot when the FBM begins to malfunction.The present invention will be described below with reference to the figures.
ループ伝送路５に対して、フレームを送出し、又受信す
る高速信号処理部１は、フレームヘッダの所在を示すク
ロック（ＣＬＫＩ）とデータ（ＲＤａｔａｌ）をＦＢＭ
２に送出する。ＣＬＫｌとＲＤａｔａｌの位相関係を第
２図に示す。フレームバッファメモリ２ではＣＬＫ １
によってタイミングを計り、伝送路内のフレーム数が整
数倍になるようにして低速信号処理部３にデータＲＤａ
ｔａ３を送る。このときフレームバッファメモリ２が正
常に動作していれば、低速信号処理部３に与えられるデ
ータ（ＲＤａｔａ３）とフレームヘッダの所在を示すク
ロック（ＣＬＫ２）の位相関係は第３図のように一致す
る。The high-speed signal processing unit 1 that sends and receives frames to the loop transmission line 5 sends a clock (CLKI) indicating the location of the frame header and data (RData) to the FBM.
Send to 2. FIG. 2 shows the phase relationship between CLKl and RData. CLK 1 in frame buffer memory 2
The timing is measured by
Send ta3. At this time, if the frame buffer memory 2 is operating normally, the phase relationship between the data (RData3) given to the low-speed signal processing unit 3 and the clock (CLK2) indicating the location of the frame header will match as shown in FIG. .
しかし、もしフレームバッファメモリ２が誤動作したと
すればその直後のＲＤａｔａ２とＣＬＫ２の位相関係は
第４図のようになり、もはやＣＬＫ２によってフレーム
ヘッダが指示されな（なる。ここで、誤動作検出回路４
では、ＣＬＫ２で指示されるパターンとフレームヘッダ
パターンとの一致をとり、不一致であれば誤動作として
この不一致信号をラッチする。However, if the frame buffer memory 2 were to malfunction, the phase relationship between RData2 and CLK2 immediately after that would be as shown in FIG. 4, and the frame header would no longer be designated by CLK2.
Then, a match is made between the pattern indicated by CLK2 and the frame header pattern, and if they do not match, this mismatch signal is latched as a malfunction.
本実施例によれば、フレームバッフ１メモリ２の動作を
確実にチェックできる効果がある。According to this embodiment, there is an effect that the operation of the frame buffer 1 memory 2 can be checked reliably.
第５図は本発明の応用例を示すもので、第１図と異なる
のは、誤動作が検出されたときに、誤動作検出回路４か
らフレームバッファメモリ２をリセットする信号が出る
ことである。この実施例では、リセット信号によりフレ
ームバッファメモリ２の誤動作を自動的に回復させるこ
とができる。FIG. 5 shows an example of application of the present invention. The difference from FIG. 1 is that when a malfunction is detected, a signal for resetting the frame buffer memory 2 is issued from the malfunction detection circuit 4. In this embodiment, malfunctions in the frame buffer memory 2 can be automatically recovered by the reset signal.
以上の如く、本発明によれば、ＦＢＭの誤動作のチェッ
ク・リセットを正確かつ自動的に行えるという効果があ
る。As described above, according to the present invention, it is possible to accurately and automatically check and reset malfunctions of the FBM.
第１図は本発明の動作原理を説明する図、第２図〜第４
図はデータとクロックの位相関係を示す図、第５図は、
本発明の応用例を示す図である。
図において、１は高速信号処理部、２はＦＢＭ。
３は低速信号処理部、４は誤動作検出回路である。
＄１ｆｆｉ
’１４ｚｖ。
第３ 躬
審４侶Figure 1 is a diagram explaining the operating principle of the present invention, Figures 2 to 4
The figure shows the phase relationship between data and clock.
It is a figure showing an example of application of the present invention. In the figure, 1 is a high-speed signal processing unit, and 2 is an FBM. 3 is a low-speed signal processing section, and 4 is a malfunction detection circuit. $1ffi '14zv. No. 3: Four judges
Claims (1)
を整数倍にするフレームバッファメモリ回路において、
フレームヘッダパターンとの一致を検出することによっ
て、フレームバッファメモリ回路の動作を確認すること
を特徴とするフレームバッファメモリ回路の誤動作検出
回路。In a frame buffer memory circuit that multiplies the number of frames in a transmission path of a synchronous TDM loop network by an integer,
A malfunction detection circuit for a frame buffer memory circuit, characterized in that the operation of the frame buffer memory circuit is confirmed by detecting a match with a frame header pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60194503A JPS6253540A (en) | 1985-09-03 | 1985-09-03 | Malfunction detecting circuit for frame buffer memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60194503A JPS6253540A (en) | 1985-09-03 | 1985-09-03 | Malfunction detecting circuit for frame buffer memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6253540A true JPS6253540A (en) | 1987-03-09 |
Family
ID=16325596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60194503A Pending JPS6253540A (en) | 1985-09-03 | 1985-09-03 | Malfunction detecting circuit for frame buffer memory circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6253540A (en) |
-
1985
- 1985-09-03 JP JP60194503A patent/JPS6253540A/en active Pending
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