JPS6253536A - Noise preventing circuit - Google Patents

Noise preventing circuit

Info

Publication number
JPS6253536A
JPS6253536A JP19320485A JP19320485A JPS6253536A JP S6253536 A JPS6253536 A JP S6253536A JP 19320485 A JP19320485 A JP 19320485A JP 19320485 A JP19320485 A JP 19320485A JP S6253536 A JPS6253536 A JP S6253536A
Authority
JP
Japan
Prior art keywords
switch
transmission line
input
converter
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19320485A
Other languages
Japanese (ja)
Inventor
Terumitsu Yamashita
山下 輝光
Nobuaki Ouchi
大内 宣明
Yoshiji Nishizawa
西沢 美次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19320485A priority Critical patent/JPS6253536A/en
Publication of JPS6253536A publication Critical patent/JPS6253536A/en
Pending legal-status Critical Current

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To prevent a noise at the input point of time of a transmission line alarm signal by providing a delay circuit between a decoder of a reception section and a switch and inputting a voice output of a decoder to a D/A converter while being retarded for a prescribed time. CONSTITUTION:When a fault takes place in a transmission line, no transmission alarm signal ALARM is inputted to a switch 3, which is closed and a signal outputted from a decoder 1 is inputted to the D/A converter 2 via a delay circuit 4 and the switch 3 and converted into an analog signal. If a fault takes place on a transmission line, noise is inputted to a delay circuit via the decoder 1, the transmission line alarm signal ALARM is inputted to the switch 3, which is opened and the input to the D/A converter is '0'. Thus, the noise when the transmission line alarm signal is inputted is prevented.

Description

【発明の詳細な説明】 〔概 要〕 雑音防止回路であって、伝送アラーム信号発生の瞬間に
おける雑音を有効に防止しようとするものである。
[Detailed Description of the Invention] [Summary] This is a noise prevention circuit that attempts to effectively prevent noise at the moment when a transmission alarm signal is generated.

〔産業上の利用分野〕[Industrial application field]

本発明は、雑音防止回路に関する。 The present invention relates to a noise prevention circuit.

音声信号を符号化してデジタル信号に変換して送出する
送信部と、それを復号化してアナログ変換する受信部間
の伝送路に障害が発生した場合には受信部側に雑音が入
り込まないようにする必要がある。
If a failure occurs in the transmission path between the transmitter, which encodes the audio signal, converts it into a digital signal, and sends it out, and the receiver, which decodes it and converts it into analog, this system prevents noise from entering the receiver. There is a need to.

このために、受信側のD/A変換器の直前にスイッチを
設は障害発生時には伝送路アラーム信号によりD/A変
換器入力をしゃ断するようになっている。
For this reason, a switch is installed just before the D/A converter on the receiving side, so that when a failure occurs, the input to the D/A converter is cut off by a transmission line alarm signal.

〔従来の技術〕[Conventional technology]

従来の雑音防止回路は、第3図に示すように、復号器1
′とD/A変換器2′の間にスイッチ3′を接続した構
成を有し、伝送路アラーム信号ALARMがスイッチ3
′に入力されると、スイッチ3′を切り替えて復号器1
′を切り離し“0”をD/A変換器2′から出力するよ
うになっている。
The conventional noise prevention circuit has a decoder 1 as shown in FIG.
' and the D/A converter 2', a switch 3' is connected between the transmission line alarm signal ALARM and the D/A converter 2'.
′ is input to decoder 1 by switching switch 3′.
' is disconnected and "0" is output from the D/A converter 2'.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、従来技術では、伝送路アラームの発生瞬間にお
いて雑音を防止できないという問題点がある。
However, the conventional technology has a problem in that noise cannot be prevented at the moment when a transmission line alarm occurs.

即ち、第4図において、1=10において伝送障害が発
生しても(第4図(A))、直ちに伝送路アラーム信号
ALARMはスイッチ3′には入力せず、1=1.にお
いて入力する(第4図(B))。
That is, in FIG. 4, even if a transmission failure occurs when 1=10 (FIG. 4(A)), the transmission line alarm signal ALARM is not immediately input to the switch 3', and when 1=1. (Fig. 4(B)).

従って1=1.からt、までは、スイッチ3′は閉じた
ままであり復号器1′からD/A変換器2′へ雑音が入
力される。
Therefore 1=1. From to t, the switch 3' remains closed and noise is input from the decoder 1' to the D/A converter 2'.

従ってD/A変換器2′からは、斜線で示すように、雑
音が出力され(第4図(C)) 、伝送路アラーム信号
の発生する瞬間の雑音を防止できないという問題点があ
る。
Therefore, noise is output from the D/A converter 2' as shown by diagonal lines (FIG. 4(C)), and there is a problem that the noise cannot be prevented at the moment when the transmission line alarm signal is generated.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は、上記問題点を解決し、伝送路アラーム
信号が入力する瞬間における雑音を防止することにある
An object of the present invention is to solve the above-mentioned problems and to prevent noise at the moment when a transmission line alarm signal is input.

その手段として、本発明は第1図の如く受信部の復号器
1と上記スイッチ3間に遅延回路4を設は復号器1の音
声出力を一定時間遅らせてD/A変換器2に入力させる
ようにしである。
As a means for this purpose, the present invention provides a delay circuit 4 between the decoder 1 of the receiving section and the switch 3 as shown in FIG. That's how it is.

〔作 用〕[For production]

本発明によれば、復号器とスイッチ間に遅延回路を設け
たので、この遅延回路による遅延時間を、障害発生時か
ら伝送路アラーム信号入力時までの時間より長く設定す
れば、伝送路に発生した雑音はD/A変換器には入力さ
れないことになるので伝送路アラーム信号入力時点の雑
音を防止することができる。
According to the present invention, since a delay circuit is provided between the decoder and the switch, if the delay time by this delay circuit is set to be longer than the time from when a fault occurs to when a transmission line alarm signal is input, it is possible to Since this noise will not be input to the D/A converter, it is possible to prevent noise at the time when the transmission line alarm signal is input.

〔実施例〕〔Example〕

以下、本発明を、添付図面を参照して説明する。 The present invention will now be described with reference to the accompanying drawings.

第1図は本発明の原理図、第2図は第1図の動作説明図
である。
FIG. 1 is a principle diagram of the present invention, and FIG. 2 is an explanatory diagram of the operation of FIG. 1.

第1図の雑音防止回路は、復号器1、遅延回路4、スイ
ッチ3、D/A変換器2とから構成されている。
The noise prevention circuit shown in FIG. 1 is composed of a decoder 1, a delay circuit 4, a switch 3, and a D/A converter 2.

復号器1は、伝送路から到達した音声信号、例えばPC
M符号をデジタル音声信号に変換する装置である。
A decoder 1 receives an audio signal from a transmission path, such as a PC.
This is a device that converts M codes into digital audio signals.

遅延回路4は復号器1の出力を一定時間だけ遅らせる回
路である。
The delay circuit 4 is a circuit that delays the output of the decoder 1 by a certain period of time.

スイッチ3は、伝送路に障害が発生した場合に入力する
伝送路アラーム信号ALARMにより切り替えられてD
/A変換器2の入力を“0”にする。
Switch 3 is switched by the transmission line alarm signal ALARM which is input when a failure occurs in the transmission line.
/ Set the input of A converter 2 to "0".

D/A変換器2は、デジタル音声信号をアナログに変換
する装置である。
The D/A converter 2 is a device that converts a digital audio signal into an analog signal.

以下、上記構成を存する第1図の回路の動作を、第2図
に基いて、説明する。
Hereinafter, the operation of the circuit shown in FIG. 1 having the above configuration will be explained based on FIG. 2.

伝送路に障害が発生していない場合は、伝送路アラーム
信号ALARMはスイッチ3に入力されずスイッチ3は
閉じている。従って復号器1から出力された信号は遅延
回路4、スイッチ3を介してD/A変換器2に入力され
、アナログ変換される。
If no fault has occurred in the transmission line, the transmission line alarm signal ALARM is not input to the switch 3 and the switch 3 is closed. Therefore, the signal output from the decoder 1 is input to the D/A converter 2 via the delay circuit 4 and the switch 3, and is converted into an analog signal.

しかし、1=10において(第2図(A))伝送路に障
害が発生すると、図示する雑音が復号器lを経由して遅
延回路に入力される。
However, if a failure occurs in the transmission path when 1=10 (FIG. 2(A)), the noise shown in the figure is input to the delay circuit via the decoder l.

1=1.において、伝送路アラーム信号ALARMがス
イッチ3に入力される。
1=1. At this point, the transmission line alarm signal ALARM is input to the switch 3.

これにより、スイッチ3は開いてD/A変換器の入力は
0″になる。
This causes switch 3 to open and the input to the D/A converter to become 0''.

従って伝送路に障害が発生した1=18から、アラーム
信号ALARMがスイッチ3に入力される仁wj+ ま
での時間1.−10以上に、遅延回路4による遅延時間
T、を設定しておけば、スイッチ3が切られた後(t=
tl)に復号化された信号がスイッチ3に入力される(
第2図(B))。
Therefore, the time from 1=18 when a failure occurs in the transmission line to wj+ when the alarm signal ALARM is input to switch 3 is 1. If the delay time T by the delay circuit 4 is set to -10 or more, after the switch 3 is turned off (t=
The signal decoded at tl) is input to switch 3 (
Figure 2 (B)).

このためD/A変換器2には、1=1.以降は、信号は
入力されず“O”が出力される(第1図、第2図(D)
)。
Therefore, the D/A converter 2 has 1=1. After that, no signal is input and "O" is output (Figure 1, Figure 2 (D)
).

一方、1=12において伝送路の障害がなくなれば1=
1.においてアラーム信号ALARMは入力されなくな
り、スイッチ3は閉じる。
On the other hand, if there is no failure in the transmission path when 1=12, then 1=
1. At this point, the alarm signal ALARM is no longer input, and the switch 3 is closed.

〔発明の効果〕〔Effect of the invention〕

上記のとおり、本発明によれば、復号器とスイフチ間に
遅延回路を設けたので、この遅延回路による遅延時間を
、障害発生時から伝送路アラーム信号入力時までの時間
より長く設定すれば、伝送路に発生した雑音はD/A変
換器には入力されないことになるので伝送路アラーム信
号入力時点の雑音を防止することができる。
As described above, according to the present invention, since the delay circuit is provided between the decoder and the swift, if the delay time by this delay circuit is set to be longer than the time from the occurrence of a fault to the time when the transmission line alarm signal is input, Since the noise generated on the transmission path is not input to the D/A converter, it is possible to prevent noise at the time when the transmission path alarm signal is input.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理図、第2図は本発明の動作説明図
、第3図は従来技術の構成図、第4図は従来技術の動作
説明図である。 I・・・復号器、 2・・・D/A変換器、 3・・・スイッチ、 4・・・遅延回路。 本発明の原理図 第1図 本発明の動作説明図 第2図
FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of the operation of the present invention, FIG. 3 is a configuration diagram of the prior art, and FIG. 4 is an explanatory diagram of the operation of the prior art. I...Decoder, 2...D/A converter, 3...Switch, 4...Delay circuit. Figure 1: Principle diagram of the present invention Figure 2: Explanation diagram of the operation of the present invention

Claims (1)

【特許請求の範囲】 送信部と受信部を結ぶ伝送路に障害が発生した場合に受
信部に入力する雑音を防止する回路において、 上記受信部を構成する復号器とD/A変換器の間に、伝
送路アラーム信号により該D/A変換器への入力をしゃ
断するスイッチを設けると共に該スイッチの入力側に遅
延回路を設け、 該遅延回路の遅延時間を、上記伝送路に障害が発生して
から伝送路アラーム信号が上記スイッチに入力されるま
での時間以上に、設定したことを特徴とする雑音防止回
路。
[Scope of Claims] In a circuit for preventing noise input to the receiving section when a failure occurs in the transmission path connecting the transmitting section and the receiving section, between a decoder and a D/A converter constituting the receiving section. In addition, a switch is provided to cut off the input to the D/A converter in response to a transmission line alarm signal, and a delay circuit is provided on the input side of the switch, and the delay time of the delay circuit is set so that the delay time of the delay circuit is determined by the time when a failure occurs on the transmission line. The noise prevention circuit is configured to be set for a period longer than the time from when the transmission line alarm signal is input to the switch.
JP19320485A 1985-09-03 1985-09-03 Noise preventing circuit Pending JPS6253536A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19320485A JPS6253536A (en) 1985-09-03 1985-09-03 Noise preventing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19320485A JPS6253536A (en) 1985-09-03 1985-09-03 Noise preventing circuit

Publications (1)

Publication Number Publication Date
JPS6253536A true JPS6253536A (en) 1987-03-09

Family

ID=16304031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19320485A Pending JPS6253536A (en) 1985-09-03 1985-09-03 Noise preventing circuit

Country Status (1)

Country Link
JP (1) JPS6253536A (en)

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