JPS6253072A - Area gradation generating circuit - Google Patents

Abstract

PURPOSE:To obtain a dot pattern optimum for respective picture elements of a digital picture by providing two dot pattern memories of dot dispersal type and dot collective type, and a circuit to select and control either one of the said memories. CONSTITUTION:An A/D converter 2 converts a signal from a video signal generator 1 to a digital signal 14, and the digital signal is stored in a frame memory 3. A dot pattern selector-controller 7 stores a digital picture 15 data read by a memory read signal A 10 in its buffer memory, computes the difference, and compares the result with a threshold to determine the turning on/off of a dot pattern selection signal 21. The dot pattern memory A 41 shows the dot dispersal type, and one B 42 dot collective type. A multiplexer 8 transmits a dot pattern data 17 if the signal 21 is such one as included in the peripheral shape of the current picture element, but transmits one 18 if not included, to a latch/shifter 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an area gradation generation circuit for providing pseudo halftones to display (recording) devices such as liquid crystal displays, plasma displays, printers, etc. that are originally capable of only displaying binary values. It is.

2. Description of the Related Art In conventional area gradation generating circuits, a dot pattern corresponding to luminance or density as shown in FIG. 2 δ or b is often used to provide pseudo halftones in area. In FIG. 2, each number in the matrix indicates the arrangement order of the dots, and depending on the level of the input digital image signal, the on/off of the dots is determined according to the following rule.

When the level of the input digital image signal is 2 (in the example in Figure 2, 2 can take on 17 levels from 0 to 16), in the case of a brightness display device, the dots corresponding to numbers 2 or higher are In the case of a zero-density recording device, dots corresponding to numbers 2 or higher are turned off, and the rest are turned on.

Using this nXzt dot pattern, from O to n
In order to generate area gradation of n2+1 steps up to 2, conventionally, for example, as shown in FIG.
- After being converted into a digital image signal 12 using the A/D converter 2, the digital image signal 12 is read into the frame memory 3 by the write signal 8, and the digital image signal 12 is read out by the read signal 9. Read out the dot pattern memory 4 as an image signal 13t-address signal,
The contents 14 are latched in the latch/shifter 6, and after being subjected to parallel◆serial conversion using the shift pulse 10, they are sent to the display unit 6 as a dot pulse train 16, and the dots on the display unit 6 are controlled on/off.

Problems to be Solved by the Invention In area gradation generation using a dot pattern, υ gradation reproduction and apparent resolution characteristics are influenced by the method of constructing the dot pattern. Generally, it is known that the dot dispersed construction method has excellent resolution characteristics, and the dot concentrated construction method has excellent tone reproduction characteristics. In conventional circuits, either the above-mentioned resolution characteristics or gradation reproduction characteristics are often emphasized and utilized.
However, when emphasis is placed on resolution, false contours become noticeable in areas where gradations change smoothly, and when emphasis is placed on gradation reproduction, useful contour lines become blurred.

The present invention has been made in view of this point, and utilizes the gradation reproduction characteristics by the concentrated dot type in areas where the gradation changes smoothly, and utilizes the resolution characteristics by the dispersed dot type in the contour areas. The aim is to provide an area gradation circuit that is capable of

Means for Solving the Problems In order to solve the above problems, the present invention includes two dot pattern memories of a dot distributed type and a dot concentration type, and selects and controls which dot pattern memory should be used. A circuit is provided to obtain an optimal dot pattern for each pixel of a digital image.

Operation In the above-described configuration, the dot pattern selection control section of the present invention considers, for each pixel ZK, eight neighboring pixels surrounding pixel Z, 1==1 to 8, and calculates the following formula. Perform the calculation.

This indicates a second-order difference operation (Laplacian operation),
A large value is taken at the part where the gradation changes greatly, that is, at the contour part. Therefore, a certain threshold t is determined and Z')t
When , pixel 2 is included in the contour part using a dot-dispersed dot pattern, and conversely, when z'<t, pixel 2 is included in the part where the gradation changes are uniform or smooth. If we decide to use a concentrated dot pattern as a dot, the superior resolution characteristics of the dispersed dot pattern will work in the contour areas, and the gradation reproduction of the concentrated dot pattern will be better in areas where the gradation changes are uniform or smooth. By taking advantage of the superior characteristics, a high-quality pseudo-halftone image can be obtained.

Embodiment FIG. 1 is a block diagram showing an embodiment of the area gradation generation circuit of the present invention. In FIG. 1, 1 is a video signal generation section, and 2 is an A/D conversion section, which converts an analog video signal 13 into a digital image signal 14. This is a 3Fi7 frame memory, which takes in a digital image signal 14 in response to a memory write signal 9 and stores a digital image.

Reference numeral 7 denotes a dot pattern selection control section, which controls the digital image data 1 read out by the memory readout signal A10.
5 is stored in a buffer, the difference calculation according to equation (1) is performed, and the result is compared with a threshold value to determine whether the dot pattern selection signal 21 is on or off. 16 is the puffer output of the dot pattern selection section 7, and has the same meaning as the digital image data 16.

41 is a dot pattern memory A, and 42 is a dot pattern memory B, for example, dot pattern memory A41.
The dot pattern memory B42 may be of the dot distributed type as shown in FIG. 2a, and the dot pattern memory B42 may be of the dot concentrated type as shown in FIG. The digital image data 16 serves as an address for the dot pattern memory A41 and the dot pattern memory B42, and is read out from the dot pattern data 17°18 by the readout signal B11.
are output as respectively. 8 is a multiplexer which transmits dot pattern data 17 through a data line 19 when the dot pattern selection signal 21 determines that the current pixel is included in the contour, and transmits dot pattern data 18 when the current pixel is not included in the contour. It functions as a switch for sending data to the latch/shifter 6. The dot pattern data taken into the latch/shifter 5 is parallelized by the shift pulse 12.
Serial conversion is performed and output as serial data 1) pattern data 2o. e is a display section that displays serial dot pattern data 20K.

Correspondingly, the on/off of the display dot is controlled.

Effects of the Invention As described above, according to the present invention, it is possible to generate an optimal dot pattern depending on the situation in which pixels are placed in an image, and to achieve high-quality area gradation. It is extremely useful as a generation method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an area gradation generation circuit according to an embodiment of the present invention, FIGS. 2a and b are explanatory diagrams showing examples of dot patterns used in area gradation generation, and FIG. FIG. 2 is a block diagram of an area gradation generation circuit. 1...Video signal generation section, 2...A/D
Conversion section. 3...Frame memory, 41.42...
・Dot pattern memory, 6...Latch/shifter, 6...Display unit, 7...Dot pattern selection control unit, 8...Multiplexer, 9...
...Write signal line, 10.11...Read signal line, 12...Shift pulse, 13...
...Analog video signal line, 14...Digital image signal line, 15.16...Pixel data line,
17°18.19...Dot pattern signal line,
20... Serial dot pattern signal line, 2
1...Dot pattern selection signal line. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 2 (Den Dotto 1 (! (shi 2 Dotto certain medium size,

Claims (1)

[Claims] an analog video signal generation section, an A/D conversion section that converts the analog video signal into a digital image signal, a frame memory that stores a digital image, two dot pattern memories that provide an area gradation pattern, and the two dots. A dot pattern selection control unit and multiplexer for selecting a pattern memory, a latch/shifter for latching the dot pattern read from the dot pattern memory and converting it from parallel to serial, and displaying binary information of dots. Area gradation generation circuit equipped with a display section for