JPS6252973A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the facing area of a control gate and a floating gate and reduce the occupying area of a memory cell by a method wherein a groove is formed in a diffused layer of which the control gate is composed and the floating gate is is extended into the groove with an insulating film in between. CONSTITUTION:One active region is formed on a semiconductor substrate and a diffused layer, which is to be control gate 1, is formed in parallel to the active region. At the predetermined region in the diffused layer 1, a groove 12 is formed. Then, two transistors (memory transistor and selecting transistor) are formed in series by forming a word line 3 and a floating gate 2 on the active region. The control gate 1 is formed on the surface of the groove 12 too and the floating gate 2 is formed in the groove 12 too with a thin insulating film in between.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an electrically programmable/erasable nonvolatile semiconductor memory device (EEFROM).

[Prior Art] FIG. 4, FIG. 5, and FIG. 6 are diagrams showing the structure of a memory cell of a conventional nonvolatile semiconductor memory device of this type. The figure and FIG. 6 are diagrams schematically showing the cross-sectional structure thereof. This type of semiconductor memory device is, for example, 15SCCDIGEST OF
Ding ECHN ICAL PAPER 3, 1984, pages 268 to 26 are truly disclosed.

In FIG. 4, a memory cell of a semiconductor memory device includes a source 6 and a drain 7 of a memory transistor, each formed of an impurity diffusion layer, and a bit line 5 for reading information held by the memory transistor. Also,
Accumulating and discharging charges to the 70-terminal gate 2 and floating gate 2 for accumulating charges.
! includes a control gate 1 formed of an impurity diffusion layer for A word line 3 made of polysilicon for selecting this memory transistor is formed extending laterally in the drawing. Further, a source electrode 8 for applying a voltage to the source 6 of the memory transistor is provided and connected to the source 6 through a contact hole 81.

Further, a pit line electrode 9 for applying an electric current to the bit line 5 is provided, and is connected to the bit line 5 through a contact hole 91 . Furthermore, control gate 1
A control gate electrode 10 is provided to apply a voltage to the bit line and is connected to the bit line through a contact hole 101. The 70-ting gate 2 is formed in a concave shape and faces the drain 7 and control gate 1 of the memory transistor with an insulating film interposed therebetween. Here, at the intersection between the floating gate 2 and the drain 7 of the memory transistor, the floating gate 2 and the drain 7 face each other with a thin insulating film of about 100 A interposed therebetween.
A tunnel region 4 serving as a path for charges is formed.

In addition, floating gate 2 and control gate 1
A thin insulating film of about 100 A is formed between the capacitor and the capacitor.

In FIG. 5, control gate 1 - floating gate 2 and memory transistor drain 7 -
A thin insulating film is formed between the floating gates 2, and a thick insulating film is formed between the floating gates 2 and the semiconductor substrate 50. Therefore, there is a capacitance of 1 between floating gate 2 and control gate 1.
3 is formed, 70-ting gate 2-semiconductor substrate 5
01! A capacitor 14 is formed between the floating gate 2 and the drain of the memory transistor.

FIG. 6 is a diagram schematically showing a cross-sectional structure including the source, drain, and bit line of a memory cell. In FIG. 6, a word line 3 for selecting a memory transistor is provided on the semiconductor substrate region between the drain 7 of the memory transistor and the bit line 5. In FIG. Next, the operation will be explained.

First, the writing operation will be explained. At this time, the source electrode 8 is electrically placed in a 70-ting state, the control gate electrode 10 is placed at a ground potential, the word line electrode 11 is placed at a high voltage, and the pit line electrode 9 is placed at a high voltage. In this state, bit line 5 and word line 3
becomes a high voltage, so the potential of the drain 7 becomes a high voltage. This increases the potential difference between the control gate 1 and the drain 7, and a high electric field is also applied to the tunnel current region 4 due to capacitance division by the capacitance II (parasitic capacitance) circuit formed between the control gate 1 and the drain 7. be done. As a result, a tunnel current flows from the floating gate 2 toward the drain 7.

As a result, electrons are extracted from the floating gate 2, the threshold voltage of the memory transistor is shifted to a lower side, and the memory transistor becomes a depletion type transistor. Therefore, when the control gate 1 is set to the ground potential during a read operation, the memory transistor is turned on.

Next, the case of erasing operation will be explained. At this time, the source electrode 8 is set to a ground potential, the control gate electrode 10 is set to a high voltage, the word line electrode 11 is set to a high voltage, and the pit line electrode 9 is set to a ground potential.

In this state, the bit line 5 is at ground potential and the word line 3 is at a high voltage, so the drain 7 is at ground potential. As a result, drain 7 and control gate 1
During this period, the potential difference becomes large, and a high electric field is also applied to the tunnel region 4 due to capacitance division by the capacitive circuit between the drain 7 and the control gate 1, and a tunnel current flows from the drain 7 to the control gate 2. As a result,
Electrons are accumulated in the floating gate 2, and the threshold of the memory transistor is filled! The voltage shifts to the higher side, and the memory transistor becomes an enhancement type transistor. Therefore, when the control gate 1 is set to the ground potential during reading, the memory transistor is turned off. Information "1°" is generated by the on and off states of this memory transistor.

“0” is stored.

FIG. 7 is a diagram isometrically showing the configuration of a capacitor circuit consisting of parasitic capacitors formed in a memory transistor. Figure 7 (a > shows the potential at the time of writing, Figure 7 (b
) is a diagram showing the state at the time of erasing. The electric field applied to the insulating film of the tunnel region 4 will be described below with reference to FIGS. 7(a) and 7(b).

Now, the value of the capacitance 113 between the control gate 1 and the floating gate 12 is 01, the value of the capacitance 114 between the floating gate 2 and the semiconductor substrate 50 is 02, the value of the capacitance 15 between the floating gate 2 and the drain 7 is 03, The film thickness of the tunnel insulating film is TOXq, and the applied high voltage is VPP. At this time, the electric field E applied to the tunnel region 4 during writing
v is.

It is expressed as Further, the electric field εe applied to the tunnel region 1i114 during erasing is expressed as follows, as seen from FIG. 7(b). In either case, the larger the control gate-floating gate capacitance ff1c1 is, the larger the electric field applied to tunnel @ia4 becomes, so the tunnel current increases, and as a result, the threshold (! voltage (
(memory transistor) variation becomes large. The large amount of change in the threshold voltage has the advantage of increasing the successive margin and extending the data retention time.

[Problems to be Solved by the Invention] In a conventional semiconductor memory device of this type, in order to increase the successive margin, data retention time, etc., it is necessary to increase the capacitance between the control gate and the floating gate. It was necessary to increase the area. However, increasing the opposing area poses a problem that becomes a major bottleneck when achieving higher integration of semiconductor memory devices.

Therefore, an object of the present invention is to solve the above-mentioned problems and provide a semiconductor memory device equipped with a memory cell that occupies a small area without reducing the capacitance between the control gate and the floating gate. .

[Means for Solving the Problems] A semiconductor memory device according to the present invention has a groove formed in the diffusion layer region constituting the contact gates, a diffusion layer also formed on the surface of the groove, and! A floating gate is formed so as to extend through eight edge films.

[Since the active groove is provided and the floating gate is formed so as to extend into the groove, the opposing area of the control gate and the floating gate increases, and the control gate and floating gate can be connected without increasing the area occupied by the memory cell. It becomes possible to increase the capacitance between gates.

[Example of the invention in action] Hereinafter, the practical theory of this invention will be explained with reference to the drawings.

FIG. 1 is a plan view of a memory cell of a semiconductor memory device according to an embodiment of the present invention, and FIGS. 2 and 3 are diagrams schematically showing the cross-sectional structure of the memory cell shown in FIG. In FIG. 1, unlike the memory cell of the conventional semiconductor memory device shown in FIG. 4, a groove 12 is formed in the control gate 1, and the floating gate 2 extends into the groove 12. It is formed. This increases the opposing area between the floating gate and the control gate 1, increasing the volume 1 between them. Other structures are the same as before.

The configuration of the memory cell is as follows.

First, one active region is formed on a semiconductor substrate, and a diffusion layer that becomes the control gate 1 is formed in parallel to this active region. A groove 12 is provided in a predetermined region of this diffusion 111. Next, by providing a word line 3 and a floating gate 2 on this active region, two transistors (memory transistor, selection transistor) are formed in series.

FIG. 2 is a diagram schematically showing a cross-sectional structure including the control gate 1 and drain 7 of the semiconductor memory vt@ shown in FIG. As seen from FIG. 2, the control gate 1 is also formed on the surface of 'a12, which is a feature of the present invention, and the floating gate 2 is formed on a thin insulator II.
It is also formed within this groove 12 via a.

FIG. 3 is a diagram schematically showing a cross-sectional structure including the source, drain, and bit line of a memory cell of the semiconductor memory device shown in FIG. 1. As seen from FIG. 3, the cross-sectional structure in this direction is the same as the conventional one.

As can be seen from FIGS. 1 to 3, since the control gate 1 and the floating gate 2 face each other with an insulating film in between even within the spacer 12, the distance between the control gate 1 and the floating gate 82 is By utilizing this opposing area, it can be made larger than before.

Furthermore, even when the memory cells are highly integrated and the area occupied by the memory cells is reduced, the lateral area of the trench 12 is hardly affected, so that a sufficiently large capacitance between the control gate and the floating gate can be maintained. can be obtained. As a result, as seen from equations (1) and (2>), the amount of change in the threshold value of the memory transistor can be set sufficiently, and the read margin and data retention time can be increased.

Note that the potential of each electrode during writing and erasing operations may be the same as in the conventional example, but since the electric field applied to the tunnel region 4 is larger than that in the conventional example, the threshold li1
? ! If the amount of change in pressure is made comparable to the conventional one, it is possible to reduce the effect of the applied high voltage 'V'FP. This is advantageous when increasing the integration of semiconductor memory devices.

[Effects of the Invention] As described above, according to the present invention, a groove is provided in the diffusion layer constituting the control gate, and the floating gate I is formed even inside the hawk via the insulating film.・If the opposing area between the rolling gate and the floating gate can be increased, and the amount of change in the threshold voltage of the memory transistor is kept at the same level as before, the area occupied by the memory cell can be reduced. , and the value of the applied high voltage VFF can be reduced, making it possible to obtain a highly integrated semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor memory device which is an embodiment of the present invention. FIG. 2 is a diagram schematically showing a cross-sectional structure of a region including a control gate and a drain of the semiconductor memory device of FIG. 1. FIG. 3 is a diagram schematically showing a cross-sectional structure including active chain acids (source, drain, and bit line) of the semiconductor memory device of FIG. 1. FIG. 4 is a diagram showing a planar arrangement of a conventional semiconductor memory device. FIG. 5 is a diagram schematically showing a cross-sectional structure including a control gate and a floating gate of a conventional semiconductor memory device. Figure 6 shows the conventional semiconductor record II! If
FIG. 2 is a diagram schematically showing a cross-sectional structure including active ams (source, drain, and bit line) of FIG. FIG. 7 is a diagram isometrically showing a capacitive circuit consisting of parasitic capacitors formed in a memory transistor. In the figure, 1 is a control gate, 2 is a floating gate, and 12 is a groove. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Fig. 1 12: 5 Koi Fig. 4 Fig. 7 (a) 1 Komi no call (b) Urao call

Claims (1)

[Scope of Claim] A semiconductor memory device including at least one MOS type transistor formed in an active region of a semiconductor substrate, wherein the MOS type transistor is formed on the semiconductor substrate with an insulating film interposed therebetween, and the MOS type transistor is formed on the semiconductor substrate with an insulating film interposed therebetween. and a second gate formed of an impurity diffusion layer in a location different from the active region of the semiconductor substrate to control the accumulation of charge in the first gate, A groove is formed in the diffusion region to serve as a gate, and the first gate is formed to extend into the groove, thereby increasing the facing area of the first gate and the second gate. Semiconductor storage device.