JPS6248127A - Carrier phase control device - Google Patents

Abstract

PURPOSE:To prevent divergence of a discriminating feedback type phase lock loop by feeding back the output of a phase error detector when the reliability of an output of a discriminator is discriminated to be sufficient and an output of a phase error estimating device when the reliability is discriminated to be insufficient respectively to a delay line of the phase error estimate device. CONSTITUTION:A complex base band signal 101 passing through a discrimination feedback type phase locked loop 100 is fed to a discriminator 102, the discrimination result of which is fed to a phase error detector 103 and a reliability discriminator 104. The phase error detector 103 detects a phase error from the output of the phase locked loop 100 and the result of discrimination of the discriminator 102 and gives the error to a phase error estimation device 105. The reliability discrimination device 104 discriminates the reliability from the output of the phase locked loop 101 and the result of discrimination from the discriminator 102 and outputs logical 1 when the reliability is better than the predetermined threshold value and outputs logical 0 when worse. The phase error estimating device 105 has a function estimating the present phase error depending on the past reliable phase error information and discriminates whether or not the output of the phase error detector 103 is used for the estimation of the present phase error based on the output of the reliability discriminator 104.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a carrier wave recovery section of a data communication system, and is capable of suppressing divergence of a decision feedback type phase-locked loop, especially when the signal-to-noise power ratio is low. The present invention relates to a carrier phase control device.

[Prior art and its problems]

With advances in digital signal processing technology and integrated circuit technology, the use of error correction codes in the fields of satellite communications and data communications has recently been considered or implemented. Generally, a decision feedback type phase-locked loop is used in the carrier recovery section of communication systems using multilevel modulation, and even when error correction codes are used in such communication systems, CCITT (International Telegraph and Telephone Consultation) Committee), Question, 16/XV
As shown in II, as a decision result for phase-locked loop feedback, it is common to feed back a hard decision result that does not use code redundancy for each baud. The reason why the decoding result is not used is that the decoding delay impairs the responsiveness of the carrier recovery section.

As a result of research on codes with high code gain, even at low signal-to-noise power ratios when the phase-locked loop that feeds back the hard decision results diverges due to errors in hard decisions, it is possible to use only the capabilities of the modulation method and error correction code. If this is taken into consideration, a situation can now occur in which a low error rate can be achieved without hindering communication. Considering this situation, there is a need for a method to avoid divergence of the carrier wave regenerator when the signal-to-noise power ratio is low while using hard decision results so as not to impair the responsiveness of the carrier wave regenerator.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a carrier phase control device that can avoid divergence of a decision feedback phase-locked loop when the signal-to-noise power ratio is low.

[Structure of the invention]

The carrier wave phase control device of the present invention includes a phase-locked loop that receives a complex baseband signal as an input, a determiner that receives the output of this phase-locked loop as an input, and a a phase error detector and a reliability judger that calculate phase error and reliability, respectively, based on these inputs; and outputs of the phase error detector and reliability judger, respectively; a phase error estimator that estimates a phase error based on a finite number of past reliable phase error detector outputs as a second input;
The output of this phase error estimator is fed back to the phase locked loop, and when the reliability determiner determines that the reliability of the output of the determiner is sufficient, the phase error estimator returns the output of the phase error estimator to the phase error detector. The present invention is characterized by having a configuration in which the output of the phase error estimator is fed back to the delay line of the phase error estimator when the reliability of the output of the phase error estimator is determined to be insufficient.

[Summary and principle of the invention]

As discussed in the section on prior art and its problems, for example, in communication systems equipped with cooperative error correction codes, there is a need for a method to avoid the divergence of decision feedback phase-locked loops when the signal-to-noise power ratio is low. . The main cause of phase-locked loop divergence at low signal-to-noise power ratios is that there is a high possibility that the phase error extracted based on an incorrect decision has the opposite sign and large absolute value from the true phase error. It occurs due to a cause. Originally, the phase that changes like white noise is not something that a phase-locked loop can follow, but considering that the phase-locked loop tracks phase changes that have some correlation with the sample time interval, this occurs due to the process described above. A possible method for preventing divergence is to feed back an estimated value of the current phase error using past phase error information to a decision feedback phase-locked loop. That is, by using past phase error information, the influence of incorrect phase error information can be reduced.

Next, the phase error estimation method will be described. The optimal estimator in the sense of minimizing the mean square error of the estimated phase error is as follows.

Let the phase error observed value at time t-i be χ, -1. If the i-th component of the tap vector of the optimal estimator is Wi, then the observed phase error vector X at time t and the tap vector W of the optimal estimator are expressed as follows.

At this time, the estimated phase error value of 10α at time t, Yt+α, is expressed by the following equation.

Ytyaα=Xt”W=W”X.

However, XtT and W7 mean the transposed matrices of Xt and W, respectively.

If the reference for the phase error at time t+α is Z, then
The estimation error ε of the phase error at time t+α due to the observed phase error vector X at time t is given by the following equation.

εt=Zt

Snake (εL') −E ((2, −W”X,)(Z
, -X tTshell) )=8 (7t") -22(Zt
tilt”) +W”E (XtXt”) It1 Cross-correlation matrix P of phase error reference and phase error observed value
, the autocorrelation matrix R of the observed phase error values is defined as follows: R E (X, Xt') The root mean square of the estimation error of the phase error is expressed as follows.

E(εt”) =E(Zt')−2PTW+WTRW
Since the rate of change of the mean square of the estimation error with respect to the tap vector of the optimal estimator in the sense of minimizing the mean square of the phase error estimation error is zero, VE(εt'')=
Since 2P+2RW=0, the tap vector W of the optimal estimator
is given by the following equation.

W=R−'P (1) In practice, the above equation is rarely used as is due to the complexity of determining the correlation matrix and inverse matrix, and the maximum slope method that updates the tap vector is used as shown in the following equation. is used. In the maximum slope method, the tap vector is updated to reduce the square of the instantaneous estimation error based on the rate of change in the tap vector of the square of the instantaneous phase error estimation error.

The rate of change with respect to the tap vector of the square of the instantaneous estimation error is given by the following equation.

From the above formula, the tap vector should be updated as follows.

Wt. 1-W, -με% = Wt +2μεt X By using this method, the tap vector converges to the solution of equation (1) on a steady basis.

An optimal estimate of the phase error can be obtained by the method based on the above principle. However, even in the above estimation method, when the phase error information that is input to the estimator is significantly different from the true phase error, it is considered that the estimation method is considerably affected by the phase error information. Considering this point, the accuracy of the estimated value can be improved by determining the reliability of the phase error using a certain scale, and when the reliability does not meet a certain criterion, the phase error information is not used for phase error estimation. things are possible. This method can be performed using the following steps: The current phase error is estimated based on a finite number (N) of past phase error observed values without using the current phase error observed value χ, and is supplied to the phase-locked loop. If the reliability of the current phase error observed value detected by the phase error detector is sufficient, the phase error is estimated; if the reliability of the current phase error is determined to be insufficient, the current phase error is estimated. The value is retained for use in phase error estimation at the next time, and is used as the 0th component of the phase observed value vector one sample time later. Furthermore, when the reliability of the observed phase error value is insufficient, the tap vector is not updated using the maximum slope method.

〔Example〕

FIG. 1 shows a functional block diagram of a carrier phase control device according to the present invention. The complex baseband signal 101 that has passed through the decision feedback phase lobe loop 100 is sent to the decision device 1029.
Phase error phase error information 3. The signal is supplied to the reliability determiner 104. The determination result of the determiner 102 is transmitted to the phase error detector 103.
and is supplied to the reliability determiner 104.

The phase error detector 103 detects a phase error from the output of the phase locked loop 100 and the determination result of the determiner 102, and supplies this phase error to the phase error estimator 105. The reliability determiner 104 determines reliability based on the output of the phase-locked loop 100 and the determination result of the determiner 102, and outputs 1 when the reliability is better than a predetermined threshold, and outputs O when it is bad. The phase error estimator 105 has a function of estimating the current phase error based on past reliable phase error information, and uses the output of the phase error detector 103 based on the output of the reliability determiner 104 to estimate the current phase error. I am deciding whether or not to do so.

For example, the reliability is determined using the 15th phase phase lock loop 100.
The determination can be made based on the distance between the output coordinates and the signal point coordinates selected by the determiner 102. When this distance is small, reliability is high; when this distance is large, reliability is low.

FIG. 2 shows a detailed configuration of the phase error estimator 105.

201 is the output of the phase error detector 1.03, and 202 is the estimated phase error value. The first multiplexer (MU
X) 205 sets the phase error detector output 201 to 0 when the output 204 of the reliability judger 104 is 1, that is, when the reliability of the output of the judger 102 is sufficient.
In other words, when the reliability of the output of the determiner 102 is insufficient, the phase error estimated value 202 is selected. D,,D,
.

...+DN is the first. Second. . . . is the Nth sample time delay element and forms a delay line.

pt+ I) t-++ pt-2+ ...+ pt
-N is time t, (t-1), if the current time is t,
(t-2), ....

(t-N) corresponds to the phase error detector output or phase error estimate. 203 is a phase error estimation error, which is selected by the second multiplexer (MUX) 207 when the reliability determiner output 204 is 1, and becomes a signal 208. When the reliability determiner output 204 is 0, the multiplexer 207 outputs 0. That is, the signal 208 takes the value of the phase error estimation error itself when the reliability of the phase error estimation error is high, and takes the value of zero when the reliability is low. p
When t-+ + p t-2+...+ pt-*
Time (t-1), (t-2), ..., (t-
The phase error detector output or phase error estimate corresponding to N) is multiplied by the signal 208 and then the integrator I++
12+...

It is integrated by I. Integrator 11+IL...r Il
+ output is pt-++ p t-2+...+pt-
Time of H (t-1).

(t-2), . . . , (t-N) are multiplied by the phase error groove detector output or phase error estimated value, and then added by an adder 206 to obtain a phase error estimated value 202.

The phase error estimate 202 is fed back to the decision feedback phase locked loop 100. This phase error estimated value 202 is
As described above, when the reliability of the output of the determiner 102 is insufficient, the multiplexer 205 selects the sample time delay elements DI, D2 . ...+DN is fed back to the delay line.

〔Effect of the invention〕

According to the present invention, it is possible to avoid divergence of the decision feedback type phase-locked loop when the signal-to-noise power ratio is low without sacrificing the responsiveness of the carrier wave regenerator.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram of a carrier phase control device according to the present invention, and FIG. 2 is a diagram showing an example of the phase error estimator in FIG. 1. 100... Phase-locked loop 101... Complex baseband signal 102 after passing through the phase-locked loop... Determiner 103... Phase error detector 104 ... Reliability judger 105 ... Phase error estimator 201 ... Output 202 of phase error detector 103
. . . Phase error estimation value 203 . . . Phase error estimation error 204 . . . Output 205 of reliability judger 104.
...First multiplexer 206...Adder 207...Second multiplexer 208...
...Phase error estimation error or spill, D, ..., D
++......Sample time delay element 1) t+ pL-l+ p t-2+...9 animals-9
...Time t. (t-1), (t-2), ・ ・ , (t-N)
Phase error detector output or phase error estimate corresponding to

Claims (1)

[Claims] (1) A phase-locked loop that receives a complex baseband signal as an input, a determiner that receives the output of this phase-locked loop as an input, and the output of this determiner and the output of the phase-locked loop as first and second inputs. A phase error detector and a reliability judger each calculate the phase error and reliability based on these inputs, and the outputs of the phase error detector and reliability judger are used as first and second inputs, respectively. a phase error estimator that estimates a phase error based on a finite number of reliable phase error detector outputs, the output of the phase error estimator is fed back to a phase-locked loop, and the phase error estimator includes: When the reliability determiner determines that the reliability of the output of the determiner is sufficient, the output of the phase error detector is determined, and when the reliability is determined to be insufficient, the output of the phase error estimator is determined as the phase error. A carrier phase control device configured to feed back to the delay line of the estimator.