JPS6244896A - Sample value holding circuit - Google Patents

Abstract

PURPOSE:To prevent an output value from varying by inputting an analog signal every scanning period, extracting and holding a specific sample value and then sending the extracted value to the succeeding stage. CONSTITUTION:When a video signal corresponding to a certain scanning period is inputted, a peak value of the video signal is charged to a capacitor Ca by a diode D and the capacitor Ca. A transfer switch ST is closed only for a short period at the timing extremely near the succeeding horizontally synchronizing signal and the peak value of the video signal is applied and held to/in a capacitor Cb through a buffer 30 and outputted through a buffer 40. A reset switch SR is closed only a short period immediately after the reopening of the switch ST after short closing to reset the peak value to be the charging voltage of the capacitor Ca to zero. Thereafter, similar operation is repeated.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

In order to process an analog signal repeatedly obtained in a certain scanning period, this invention provides a sample value that outputs a specific level value of the signal extracted and held during a certain period, that is, a sample value during the next period. The present invention relates to a hold circuit and a sample value hold circuit suitable for rationally determining a "threshold value" for binarization of a video signal of an object obtained by an imaging device, in which the analog signal is a video signal of a subject obtained by an imaging device.

[Prior art and its problems] Image information processing technology is used to automate visual inspection of objects. In other words, features related to position, dimensions, shape, etc. are extracted from the video signal of the subject obtained by an imaging device such as a television camera, and pass/fail is determined based on the deviation from a preset standard value. be. In this case, a certain "threshold value" is used before feature extraction.
Binarization processing of the video signal is performed based on. Reasonably determining this ``threshold'' is the key to faithfully reproducing the image of the subject and, in turn, conducting the inspection correctly. Conventional methods for determining the "threshold value" include the following. I will briefly describe the progress of the improvement so that you can better understand the meaning of the method. First, there was a fixed two-point method. This involves placing a matte black background board near the subject, capturing an image of it, using the video signal level as a reference level, and then adjusting and fixing the ``threshold''. A drawback of this method is that the processed image may not be faithful to the raw image depending on the imaging conditions. In other words, if the subject is text written on a colored mount, the video signal level will fluctuate due to uneven illumination on the subject or changes in the color of the mount, so if you binarize based on a fixed "threshold" This will cause inconvenience. Furthermore, even if uniform illumination of the subject is achieved, the video signal level may change around the screen due to unevenness in image density (shedding) caused by uneven sensitivity in the photoelectric conversion element or insufficient light at the periphery of the lens. Therefore, if a fixed "threshold" is used for binarization, the binarized image will be distorted with respect to the raw image. The following methods can be used to improve the above. That is,
For each scanning cycle, a "threshold value" is set for binarization based on a specific level value in the video signal of the previous scanning cycle.
It is designed to determine. As this specific level value, ■ a peak value, ■ a value lower by a certain value than the peak value level, ■ a value that divides the black level value of the black matte background board and the peak value by a certain ratio, or a black level value and There are weighted average values with peak values. As mentioned above, the black level value and the peak value of the black matte background board are divided by a certain ratio, or the weighted average value of the black level value and the peak value is used as a specific level value and the "threshold" for binarization is used. The determining method will be explained with reference to FIGS. 6 and 7. Fig. 6 is a block circuit diagram of a conventional example in which a peak value hold circuit as a sample value hold circuit is applied to a binarization device, and Fig. 7 shows a video signal as an input and a It is a time chart which shows each waveform with a value signal. In FIG. 6, 15 is a photoelectric conversion element included in an imaging device (not shown), 16 is an amplifier, 17, 19 and 27
．． 29 is a peak value and black level/sample value switch, respectively; 18A, 18B, and 28A, 28B are a peak value hold circuit and a black level/sample value hold circuit, respectively; 20.21 is a difference device; and 22 is an adjustment voltage divider. , 23 is a comparator, and 24 is a binarized signal. This operation will be explained. In FIG. 6, photoelectric conversion element 1
The video signal from 5 is amplified through an amplifier 16 to obtain a video signal 50 as shown in FIG. 7(a). Switch 17.
19 is operated alternately to hold the peak value within one horizontal scanning period, for example, 38 in FIG. When sampling the previous scanning period, the peak value held in the other peak value hold circuit 18B is output from the switch 19.Similarly, for the black level, the circuit section S selects the peak value from the previous scanning period. The black level value held during the period is output from the switch 29. A difference voltage 46 between this black level value and the peak value from the switch 19 is created in the difference machine 21, and this is applied to the adjustment voltage divider. 22, the voltage is divided into two parts (for example, divided into 1/2) and applied as an adjusted partial pressure 47 to the differentiator 20. In this differentiator 20, the adjusted partial pressure 47 and the peak value 46 previously output from the switch 19 are combined. The comparator 23 then compares the video signal 50 with the r threshold determined as described above in the comparator 23. Depending on the magnitude, the binary signal 60 shown in FIG. 5 fb) is output. In this way, a more appropriate "threshold value" can be determined depending on whether the peak value level in the previous scanning cycle is higher or lower. Above, we have described in some detail the mechanism for determining the "threshold" of the binarization device and the roles of the peak value hold circuit and the black level/sample value hold circuit therein. This is to help you better understand the background and purpose of value hold circuits. Next, a conventional example of a peak value bold circuit, which is an example of a Zamburui direct hold circuit, will be explained in detail with reference to FIG. A non-inverting input terminal of a buffer 31 is connected to one switching contact 17a of the switch 17 via a diode. Further, the connection line between the input terminal and the cathode of the diode D1 is connected to ground through the capacitor C1, the switch SRI, and the resistor R1, respectively. The output terminal of the buffer 31 is connected to one switching contact 19a of the switch 19. The above constitutes the beer value bold circuit belonging to the first system. The peak value bold circuit of the second system also has a completely similar configuration. The operation of the above circuit is as follows. As shown by the solid line in FIG. 5, when the terminal 17c of the switch 17 and the contact 17a are connected, and the terminal 19c of the switch 19 and the contact 19b are connected, the video signal as a voltage input is connected to the diode. The capacitor CI is charged through D1, and the maximum value of the input voltage is always kept charged. Buffer 31
is a circuit with an amplification factor of 1 in which the input resistance is extremely large and the output resistance is extremely small, so the output voltage value is directly equal to the input voltage value. The switch SRI has a reset function. That is, as shown by the broken line in FIG. 5, the terminal 17c of the switch 17 and the contact 17b are switched and connected, the terminal 19c of the switch 19 and the contact 19a are switched and connected, and the charged voltage is output. However, immediately before each switch 17, 19 is switched to the solid line position again, the switch SRI is closed for a short time to reset the voltage to zero and prepare fjA for inputting the video signal for the next scan. It is. In the above example, the aspect of the sample value during the scanning period is the peak value, but in other cases, for example, the signal level at a certain time during the scanning period, the difference between the maximum value and the minimum value, or the maximum value. The average value of the value and the minimum value, or the average value □ of the signal level in the scanning period, etc. can be taken as appropriate depending on the purpose. Of course, in these cases, the diodes DI, D2 and capacitor CI C2 of the conventional example
Instead, a corresponding extraction and holding circuit will be applied. Now, in this conventional circuit, there are two paths through which the video signal passes for each scanning period, so the output values may vary slightly due to the delicate characteristics of the circuits belonging to those paths. ■ Therefore, when the "threshold value" is determined using this output, the "threshold value" varies somewhat for each scanning period, causing distortion in the binarized signal. [Objective of the Invention] The object of the present invention is to solve the problems more than those of the conventional ones, and to solve the problem when a certain value of a signal sampled in each scanning period is output during the next period. Another object of the present invention is to provide a sample value hold circuit that does not vary at least slightly depending on the circuit characteristics, and is relatively simple and has good cost performance. has the following configuration: a sample value extraction and holding circuit that extracts and holds a specific sample value of an analog signal for each scanning period; a transfer device that controls the timing of the transfer operation; , and a sample value transfer/holding circuit that holds the specific sample value transferred via the transfer device are connected in series.The sample value extraction/holding circuit also includes a circuit for resetting the held sample value; A reset operation 1 switch is provided to control the timing of the reset operation.When an analog signal is input to the sample value extraction and holding circuit, this circuit extracts a specific sample value during the scanning period and holds it at the same time. The transmitter performs a short transfer operation in the temporal vicinity of the next horizontal synchronization signal, and the signal held in the sample value extraction and hold circuit is transferred to the sample value transfer and hold circuit and held as is. Then, after the transfer operation of the retractor, the reset switch is operated and the held sample value is reset to zero.Then, the video signal of the next scanning cycle is input, The same process is repeated thereafter.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to FIGS. 1 and 2. This example relates to a peak value hold circuit, which is one of the sample value hold circuits. FIG. 1 shows the circuit, and FIG. 2 shows a signal waveform diagram and a time chart of operating signals. The configuration of the circuit is as follows. 15 is a photoelectric conversion element (not shown) of an imaging device; 16 is an amplifier that amplifies the video signal from the photoelectric conversion element 15; this amplified video signal is used as a peak value hold circuit as a sample value hold circuit according to the present invention; It is input to the circuit 10. D is a diode, C
a and Cb are each a capacitor, one side is connected to the internal baseline of the peak value bold circuit from the input terminal to the output terminal, and the other side is grounded. Ca and diode D extract and hold the peak value of the video signal, and cb holds the peak value. SR and ST are a reset switch and a transfer switch, respectively, which are always open and whose closing timing is controlled by a control device (not shown). 30 and 40 are operational amplifiers called buffers, in which a voltage signal input to a non-inverting input terminal is output as is from an output terminal. In addition, this input resistance is very high and almost no current is taken out from the photoelectric conversion element 15, and at the same time, negative feedback is applied to the maximum, so this output resistance is very small, even if current is taken out on the output side. , the output voltage does not fluctuate. That is, even when extracting an output current, the value of the input voltage can be accurately output. And diode D, banfa 3
0. A transfer switch ST and a buffer 40 are connected in series from an input terminal to an output terminal. The circuit from the diode D to the buffer 30 constitutes a peak value extraction/holding circuit 10A, and the portion from the transfer switch ST to the buffer 40 constitutes a peak value transfer/holding circuit 10B. Next, the operation of this circuit will be explained. When a video signal corresponding to a certain scanning period is input in the form of a voltage signal,
Since the reset switch SR&t is always open, the capacitor Ca is always charged with the maximum value, that is, the peak value, of the video signal by the diode D and the capacitor Ca. Then, the transfer switch ST is controlled to close for a short time at a timing very close to the next horizontal synchronization signal. Then, the peak value of the video signal is applied to the capacitor cb via the buffer 30 and held there, and is output via the buffer 40. The reset switch SR is
Immediately after the transfer switch ST opens for a short time and then opens again, it closes for a short time to reset the peak value of the charging voltage of the capacitor Ca to zero. The same process is repeated thereafter. In this way, the peak value of the video signal in each scanning period is outputted with a delay of one scanning period. Figure 2 (a) to tel is a chronological diagram of what has been explained above, where (a) shows a video signal as an analog signal, and in this figure, 'rp is the scanning period, P1 to tel. P
4 is a peak value during each scanning period, which is the voltage value charged in the capacitor Ca. The figure (b) shows temporal changes in peak values, each of which maintains a constant value after the time corresponding to the peak value. The same figure (C1 is the transferred capacitor c
b shows the voltage value, and the peak value one scanning cycle ago is shown in the same figure (
Transfer is performed by closing the transfer switch ST based on the operation signal of d). The timing of this transfer signal must be selected close to the scanning synchronization signal, as shown by the broken line. In addition, in the same figure (el is an operation signal for resetting the voltage value of the capacitor Ca to zero, and it must be done immediately after the transfer switch completes its operation. As a result, at the timing shown by the broken line in the figure) The peak value of the peak (mountain) is reset to zero. The above is a case where the sample value is a peak value. Examples of other aspects of sample values are described below. Another embodiment shown in FIG. 3 is a case where the video signal value at a certain specific point in time during the scanning period is used as the sample value. The specific time value bold circuit 11 includes a specific time black value extraction/holding circuit 118 and a specific time black value transfer/holding circuit J.
It is connected in series with IB. The latter is the same as the first embodiment. The difference from the first embodiment lies in the sample value extraction means. That is, the switch SS is always open, and is closed only for a short time when a sample value is to be extracted, and is operated by a pulse signal from a control section or an extraction command signal generation section (not shown). Therefore, at a specific time, the switch SS is closed for a short time, and the voltage at that time is extracted as the charging voltage of the capacitor Ca. The other operations are the same as those described above, so the explanation will be omitted. Next, in yet another embodiment shown in FIG. 4, the average value of the video signal during a certain scanning period is extracted as a sample value,
This is to be used as a comparison standard during the next scanning period. The average value hold circuit 12 is constructed by connecting an average value extracting/holding circuit 128 and an average value transfer/holding circuit 12B in series in the same manner as described above. The latter is the same as the first embodiment. The average value as a sample value is resistance Rm, capacitor Cm,
This is obtained by a well-known integrating circuit consisting of a 5° buffer. That is, if the input voltage as a video signal is νi, and the voltage charged to the capacitor Ca via the integrating circuit is Vo, then dividing this Vo by the scanning period Tp in a subsequent stage (not shown) yields the average value regarding the scanning period. is obtained. The transfer by the switch ST and the zero reset by the switch SR are the same as in the first embodiment, so their explanation will be omitted.

【Effect of the invention】

Due to the above configuration and operation, the present invention has the following superior effects compared to the conventional example. (1) A circuit that performs a series of operations such as inputting an analog signal every scanning period, extracting and holding a specific sample value, and sending it to the next stage, that is, a sample value hold circuit, is a single system. Therefore, fluctuations in the output value due to differences in the characteristics of the two circuits cannot occur. (2) Since the circuit is a single system, compared to the conventional two-system system, there is no need for a switch before and after the sample value hold circuit, and at the same time, the circuit configuration and number of parts used are reduced. , which has a significant effect of improving reliability and reducing cost at the same time. (3) In particular, in the case of the embodiment, since buffers are provided at the output stage of each of the sample value extraction and holding circuit and the sample value transfer and holding circuit, the input resistance is very high, so almost no current is drawn from the analog signal source. Don't take it out. Furthermore, since the negative feedback is maximized, the output resistance of the buffer is extremely low, so even if current is extracted, the output voltage will not fluctuate. That is, even if the output current is taken out, the input voltage value can be accurately detected, which is convenient for measurement.

[Brief explanation of drawings]

FIG. 1 is an embodiment according to the present invention, FIG. 2 is a signal waveform diagram and time chart in the embodiment, FIG. 3 is another embodiment according to the present invention, and FIG. 4 is still another embodiment according to the present invention. Fig. 5 is a circuit diagram of a conventional example, Fig. 6 is a block circuit diagram of an application of the conventional example to a video signal binarization device, and Fig. 7 is a circuit diagram of a video signal in an application example of the above conventional example. It is a waveform diagram with a binarized signal. Symbol explanation: D = diode, Ca, Cb, Cm: :I capacitor, Rm: resistor, SR: reset switch, ST: transfer switch, SS: switch, 10: peak value hold circuit, 10A: peak value extraction and hold circuit, 10B : Peak value transfer/hold circuit, 11: Specific time value hold circuit, 11A: Specific time black value extraction/hold circuit, 11B: Specific time black value transfer/hold circuit, 12: Average value hold circuit, 12A: Average value extraction/hold circuit, 12B: Average value transfer holding circuit, 30.40, 50: Bath sofa. Fang 1 diagram

Claims (1)

[Claims] 1) In a device that inputs an analog signal obtained by scanning at a certain period and for each scanning period, and outputs each specific sample value extracted from each analog signal, (a ) A sample value extraction and holding circuit that includes a circuit that extracts a specific sample value from each analog signal and temporarily holds the sample value, and a reset switch that is controlled to operate when the sample value should be reset. (b) a transfer switch connected in series with the sample value extraction and holding circuit and controlled to operate at the time when the sample value should be transferred; a sample value transfer/holding circuit consisting of a circuit that holds the sample value and outputs it to the next stage, the transfer switch operates close to the timing of the horizontal synchronization signal, and the reset switch operates at least at the timing of the horizontal synchronization signal. A sample value hold circuit characterized in that it operates after the operation of a transfer switch is completed.