JPS6243221A - Data compressing and coding device - Google Patents

Abstract

PURPOSE:To save the register length and at the same time to reduce the coding delay by providing a carry alarm signal generating circuit and a section reducing circuit, by reducing the width of the relevant section to limit the transmission of the carry to the fixed length or less when a carry alarm signal is generated. CONSTITUTION:The information digits xi supplied through an input terminal 101 are supplied successively to a probability parameter generator 102. the generator 102 delivers the probability parameters ci(xi) and q(xi) to lines 104 and 103 respectively in response to the value of xi. The adders and multipliers update the values of F1, F2 and A, and store them in registers 108, 106 and 105 respectively. The digits higher than the lower M digits are delivered successively through an output terminal 109 out of the value of the F1. While the lower M digits of the F1 are also supplied to an alarm circuit 110. Then, a carry alarm signal is sent to a section reducing circuit 111 in case the transmission of the carry longer then the M digits is about to start. Receiving the carry alarm signal, the circuit 111 reduces the A to prevent the input of '1' to a line 107.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is a data compression/encoding method that removes redundancy included in digital data when transmitting or storing it, thereby saving transmission time or storage capacity. It is related to the device.

(Prior Art) As a method of compressing redundant data and a method of restoring the original redundant data from the compressed data, a method using a one-piece code is commonly known and used. For details on the arithmetic code data compression encoding device (device that compresses data; hereinafter also simply referred to as the encoding device) and data compression/decoding device (device that restores data; hereinafter also simply referred to as the decoding device), For example, International Business Machines Corporation (International Business M.
achines Corporation) to 197
IBM Journal of Research Anod Development (IBM Journal)
of Research and Develop
ent) Volume 20, No. 3, pages 198-203 and 19
Volume 28, No. 2 of the same magazine, published in 1984, 135-149
Page and Stanford University in the United States.
Richard Clark Pass':2 (Richard C1) issued in 1976 at
ark Pa5co) Ph.D. thesis ``Source Coding Algorithms 7 Aufast Data Compression''
for fast data compression
It is detailed in the nth month.

Of these methods, the method for compressing data will be briefly described. Information digit string X1. X2. ....

XN is a code digit string w19w2 . . . , VJl, for example, as follows, and the redundancy of the information digit string is removed.

First, let F be the value at the smaller end (ie, 0) of a predetermined interval on a number line (from 0 to 1), and T be the width of that interval (ie, 1). Next, the following steps Al) to A5) are executed. In the following, it is assumed that X←y indicates that the value of y is substituted for X. It is also assumed that all operations are performed in the b-adic system.

Al) The value of i is set to 1.

A2) Enter the i-th information digit Xi A3)
Probability of appearance q, (X,) of the i-th information digit xi
and find the cumulative appearance probability.

A4) FmF+c, (x,)T Tmq, (x,)・T and truncate T to a predetermined significant figure.

A5) If i<N, increase the value of i by 1 and move on to A2).

If i=N, end.

Finally, from among the real numbers in the interval determined by the final values of F and T, choose a real number with the smallest number of digits when the real number is expressed numerically, and use the expression digits 00w1 of the selected real number.
w2...W, is a code digit string w, w,...

Defined as W. Note that the following notation will be used below for convenience of explanation.

T=A-b-' A:= O, t1t2...jJ(A)F=(F1+
F2)・b-1 Fl: fl, f, 2°”'1j (Fl) F2:0.F2
, 1f2. °”f2j(F2) where 1(A), l(F
g, l(F'2) represent the representation digit numbers of A, Fl, and F2, respectively. Further, in the initial state (that is, when the encoding device is initialized with F as 0 and T as 1), it is assumed that t1=0. Then, the above-mentioned step A4) is expressed as follows.

A4.1) If F2 + ci(x,)・A > 1, execute FleFl + 1 A4.2) F2mfrac(F2+ci(xi)・A)
shall be. Here, frac(x) is a function that gives a value below the decimal point of X.

A4.3) Amqi(xi)A shall be.

4.4) If t1=0 Flmb-F1+f, 1 F2sfrac(b-F2) eb-A Ihz + 1 A4.5) If t1=0, move to A4.4).

Otherwise, move on.

A4.6) A's decimal fish box has +1 or less tK+1. tK+
2. ...is discontinued.

It is shown in the above-mentioned literature that if the above procedures Al) to A5) are followed, the length L of the code word is generally smaller than the length N of the information digit string, and data can be compressed.

On the other hand, to briefly describe how to restore data:
The code digit string ww is, for example, the following 1, 2. ”
'WL' is converted into the original information digit string X.

X2. ..., XN is restored.

First, W is 0. VFl, w2. ... Substitute wL, S
Assign 1 to . Next, the following steps B1) to B5) are executed. In the following, it is assumed that X←y indicates that the value of y is substituted for X. It is also assumed that all operations are performed in the b-adic system.

Bl) Let the value of i be 1. B2) Let Xl be the largest digit among y that satisfies c, (y)≦W/S.

B3) Output x as a restored information digit.

B4) WeW-c4(xH)S Smq, (x,)・S and truncate S to a predetermined significant figure.

B5) If i<N, increase the value of i by 1 and proceed to B2).

If i=N, end.

Note that the following notation will be used below for convenience of explanation.

5=B-b-δ B=0.51S2...5l(B) W=(W1+W2)・b-δ W1=w, 1w, 2°""1j(Wl) W2 = 0-
W2.1"2,2°"W27 (W2) where 1 (B),
1 (Wl) and 1 (W2) represent the representation digit numbers of B, Wl, and W2, respectively. Further, in the initial state (that is, when the decoding device is initialized with W set to 0.W1W2 . . . town and S set to 1), it is set to 5140. Then, the above-mentioned procedure B2) is expressed as follows.

B2) The maximum digit among y that satisfies c, (y)≦(W1+W2)/B is set to 4.

Further, step B4) is expressed as follows.

B4.1) If W2-c, (x,)-B<O, then W1 elongation W
1-1 Execute W2m(1,0+W2) --cl(x,)・B. Otherwise perform W2mW2-c:(xρ,B.

B4.2) Bmq, (Tao)・B shall be.

B4.3) If 51=0 W14p-b-W1+w2,1 W2mfrac(b-W2) B Cage b-B δ−δ+1 shall be.

B4.4) If 51=0, move to B4.3).

Otherwise, move on.

B4.5) B's decimal fish box +1 or lower "K+1."K
+2. ”, will be discontinued.

If the above steps Bl) to B5) are followed, the code digit string W1
゜w2. ..., the original information digit string X1 from WL
．． X2. ..., the above-mentioned document shows that XN can be restored without error.

Further, the above-mentioned document shows that the above-mentioned steps Al) to A5) and Bl) to B5) have properties that are convenient for deviceization as described below, for example. First of all,
The advantage is that it allows for flexible design depending on the purpose of use. That is, in the above procedure, the length N of the information digit string was set to a predetermined constant value, but by just slightly changing the above procedure (to the extent that it does not affect the configuration of the device), the length L of the code digit string can be changed. Can be set to a constant value. The second point is that if the length N of the information digit string is made sufficiently large, compression efficiency will improve;
is the point where the theoretical limit is almost reached. Finally, the third point is that the code digits can be sequentially output in the above steps Al) to A5). That is, according to the above literature, once a carry occurs in the calculation F1eF1+1,
Since the carry will not propagate again to higher-order digits than the range in which the carry propagated, for example, if b=2 and F1=1
0101111, the carry cannot be propagated to the upper 3 bits 101 of Fl (because the operation F14-F1+
1 is executed and the carry propagates, it is the fourth
This is because the carry is up to the bit, and after that, the carry does not occur to a higher level than the range in which the carry once propagated.)
. By using this property, code digits can be sequentially output before the encoding of all information dips 1 is completed. For example, b=2 and F1=1010111
When it is 1, the upper three bits 101 of Fl do not change in subsequent calculations, so they can be output as sign digits.

Now, a data compression encoding device and a data compression decoding device for compressing data and restoring data as described above are disclosed in, for example, US Patent No. 4,122,44 of International Business Machines Corporation of the United States.
This can be realized by a circuit including arithmetic operation circuits such as addition and multiplication as described in No. 0.

(Problem to be Solved by the Invention) However, in the conventional system, code digits can be output sequentially only in the above procedure AI).
Even if +1 was executed and the carry propagated, it was limited to cases where the range of propagation was small. For example, b=2 and F1
When =10101101, the carry propagates only from the lower digit to the second digit, so the upper 6 digits can be output sequentially as the sign digit, but F1=
When F14=F1+1 is executed in the case of 01111111, the carry propagates to the most significant digit, so it is impossible to output the code digits sequentially.

Therefore, the capacity (number of digits) of the register for storing the expression digits of Fl needs to be sufficiently large in consideration of the case where the code digits cannot be sequentially output. Furthermore, if code digits cannot be output sequentially, the delay time during encoding (referred to as encoding delay) will also increase.

However, depending on the application, it is required to reduce the encoding delay. For example, computer terminals require encoding and decoding devices with high compression efficiency in order to increase line usage efficiency, but on the other hand, in order to communicate with computers, encoding devices and decoding devices with small encoding delays are required. equipment is required.

Conventional data compression encoding devices and data compression decoding devices not only require large-capacity registers, but also have the disadvantage that they cannot realize the above-mentioned applications.

An object of the present invention is to eliminate the above-mentioned drawbacks of conventional data compression encoding devices and data compression decoding devices, and to provide a data compression encoding device incorporating a new carry control method.

(Means for Solving the Problems) The present invention sequentially changes predetermined intervals on a number line using a predetermined method according to information digits that are input in sequence, and finally In a data compression encoding device that outputs a numerical representation of a real number included in the interval obtained as a code digit string for an input information digit string, the contents of a register storing the value at one end of the interval are monitored. An alarm circuit generates a carry alarm signal according to a predetermined rule, and if a carry alarm signal is generated, the propagation of the carry is kept below a certain length by shortening the width of the section. By including a section shortening circuit for limiting the length of the register that holds the value at one end of the section, the length of the register that holds the value at one end of the section can be reduced to a certain length or less, and at the same time, the encoding delay can be reduced.

(Effect) From the above literature, in the above procedure A4.1), F1e=F
If the carry propagation length when performing 1+1 is at most X digits (X is not a constant value), the digits of Fl higher than the X digits can be output as sign digits. Therefore, if the carry propagation length becomes smaller.

The present invention limits the carry propagation length to X digits or less as follows.

The carry propagation length exceeds X digits when all the lower X digits of Fl become b-1 in the above procedure A4.1) when F2 + C1(xi)・A >
1 and the operation F1mF1 + 1 is executed. Therefore, in order to make the carry propagation length less than or equal to )F2+c, (x
i), make the value of A smaller than 1, and perform the operation F1
6=Prevent execution of F1+1. Specifically, the following procedure is added between conventional procedures A4) and A5).

A, b) If all the lower X digits of Fl are b-1, then move to A, otherwise.

A1) sections, namely Fl, F2. Shorten A using a predetermined rule.

A, C) If t1=0 Fl-b-F1+f2,1 F2sfrac(b-F2) mb-A zmt+1 A, 2) If t1=0, move to A, C).

If t1kiO, move on to the next step.

A, E) Move to A, B).

A) Move on to the next step.

In particular, as the predetermined rule of step A9),
If we decide to divide the value of A by b, after executing step A, no), the value of A will return to the value before executing step A6) t14o
Therefore, the above procedures A0) to A, 2) are replaced with the following procedures A and G).

A,)) F'1mb-F1+f2゜F2mfra
c(b-F2) tut + 1 This operation is equivalent to shifting the contents of the register in which the representation digits of Fl, F2 are stored by one digit toward higher positions.

FIG. 1 is a basic configuration diagram of the present invention. In the figure, the information digit x1 input from the input terminal 101 is sequentially input to the probability parameter generator 5102, and the probability parameter generator 102 generates the probability parameter ci(X,
) and qi(x,) respectively on the lines 104. line 10
Output to 3. The adder and multiplier are set to F according to the procedure described above.
Update the values of l, F2°A and store them in register 10 respectively.
Stored at 8,106°105. Note that, to line 107, 1 is output when F2 +c, (x,)·A≧1, and 0 is output otherwise. The digits higher than the lower M digits of the value of Fl are sequentially outputted from the output terminal 109. On the other hand, the lower M digits of F1 are also supplied to the alarm circuit 110, and when propagation of a carry longer than M digits is about to occur, that is, when all the M digits become b-1, a carry alarm signal is sent to the section shortening circuit 110.
Send to 1. When the section shortening circuit receives a carry alarm signal, it decrements A to prevent a 1 from being input to line 107.

On the other hand, in order to restore the original information digit string from the coded digit string output by the encoding device of the present invention, the following procedure is performed. The encoding device shortens the interval when all of the lower M digits of Fl become b-1. Therefore, the decoding device also has a register Fl as a copy or part of a copy of the coding device.

Adding F2 corresponds to a rule in which the decoding device reproduces the operation of the encoding device, and when the lower M digits of the register F1 are all b-1, the encoding device shortens the section. Then, the contents of registers W and S of the decoding device are corrected. Specifically, conventional procedures B, 3) and B, 4
), add the following steps.

B, a) Execute FsF + c (X,). That is, if F2+ct(xH)B≧1, set F14-Fl + 1 and execute F2Jrac(F2+c, (x,)-B).

If the lower M digits of Fl are all b-1, then move to B, g).

B, C) The encoding device converts the value of F using the same rule as the rule for shortening the interval.

Furthermore, the values of W and S are converted in accordance with the rule. In other words, if the encoding device shortens the interval as FmF+gt F4-T-hi (hi<1), then it becomes W 佽W-gi SmS-戊.

B, 2) If 50=0, Flmb-F'l+f, 1. Wlmb-W1+w21,
F2mfrac (b-F2), W2mfrac (b-W
2) B, where t<-t+1, BmbrB δ-δ+1, e) If 51=0, move to B, 2).

If s0ki0, move on to the next step.

B, move to) 30 mouths).

B, g) Move on to the next step.

In particular, if the encoding device has decided to divide the width of the interval by b as a rule for shortening the interval, the value of B after executing step B, 2) will be the value before executing step B, c), and S, Since the paralysis is 0, the above steps B, C) to B, E) are replaced with the following steps B and H).

B, Ch) Flmb-F1+f2, 1F2mfra
c(b-F2) Wleb-Wl + w, 1 W2#frac(b-W2) zmI+1 δ-δ+1 This operation saves the contents of the registers containing the representation digits of Fl, F2 and Wl, W2 to the higher This is equivalent to shifting one digit in the opposite direction.

FIG. 2 is a basic configuration diagram of a decoding device incorporating section correction. In the figure, F register 2o7°F2 register 208. The IF information circuit 209 is the same as that included in the corresponding encoding device. Input terminal 201
The code digit 舊 input from Wl.

Register 202 in which the representation digits of W2 are stored
are input in order, and the x1 generator 203 has a probability parameter 4
By varying the output supplied to C, (
Find the maximum digit Xl among y that satisfies y)≦(W1+W2)/B, and use it as the final output. Note that when the output of the x1 generator 3 is y, the comparison result between c4(y) and (W1+W2)/B is supplied to the line 211. When the output of the Xi generator 203 is determined,
The adder and multiplier update the values of W and H according to the above-described procedure and store them in registers 202 and 206, respectively. Also F Lujistar 207. The contents of F2 register 208 are changed according to the encoding procedure described above. The output of the X4 generator 203 is also supplied to the output terminal 5, and when the value of X is determined, it is output from the output terminal 5 in order. On the other hand, the contents of the F register are also supplied to the alarm circuit 209, and when shortening of the section is detected, a detection signal is sent to the section correction circuit 210.

When the section correction circuit 210 receives the alarm signal, it registers the registers 202, 206, 207, and 208 according to predetermined rules.
Correct the contents of. That is, steps B and C) are executed.

(Embodiment) As an embodiment, a data compression encoding device configured according to the present invention is shown in FIG. 3, and a corresponding data compression decoding device is shown in FIG. 4. 1 of Figure 3 and Figure 4, respectively.
Blocks or lines having the same functions as those in FIGS. 1 and 2 are designated by the same numbers. In this embodiment, b=2.

That is, it is assumed that calculations in the encoding device and the decoding device are performed in binary notation, and numerical values are displayed in binary notation.

The encoding device in FIG. 3 inputs the information bit x from the input terminal 101.
1, X, into a probability parameter generator S (which can be configured, for example, by a read-only memory or an adaptive predictor), and a probability parameter q(X,).

Obtain c(x,) and perform the arithmetic operations shown in the above procedure to obtain Fl, F2 . The value of A is updated. Bits higher than the lower M bits of Fl are sequentially outputted from the output terminal 109. On the other hand, the value of the lower M bits of F1 is also supplied to the alarm circuit 110. Since the alarm circuit 110 generates a carry alarm signal when all the lower M bits of Fl become 1 (=b-1), the alarm circuit 11
0 can be constructed by ANDing the M bits. When the section shortening circuit receives a carry alarm signal, it shortens the congestion of the section in synchronization with other circuits. In this example, the interval is shortened by dividing A by b (:2), so register 1 where the expression bits of Fl and F2 are stored.
By directly shifting the contents of 06.108 to the left (toward the higher bits), the interval can be shortened (i.e., step A9 described above).
~A, 2) is being executed.

In the decoding device shown in FIG. 4, the code bits W input from the input terminal 201 are sequentially input to the register 202, and Xi! The generator 203 first outputs 1. And cl(1) and (Wl+W2)/ which are supplied to line 211
Check the comparison results with B, and if c, (1)≦(W1+W
2) If /B, then X uni 1 otherwise, set di=0, and set xl as the final output. Once the output of the X5 generator is determined,
The adders and multipliers are connected to registers W and B according to the procedure described above.
, Fl, and F2 are updated. Further, the output of the generator is also supplied to the output terminal 205, and when the output is determined, it is sequentially outputted from the output terminal 205. on the other hand,
The value of Fl is also supplied to the alarm circuit 209. Similar to the alarm circuit of the encoding device, the alarm circuit 209 generates a carry alarm signal when all the lower M bits of Fl become 1. When the section correction circuit 210 receives the carry alarm signal, it corrects W, B, Fl, and F2 in synchronization with other circuits. In this embodiment, the encoding device shortens the interval by dividing the interval A by 2.
By directly shifting the contents of registers 202.207.208 in which the expression bits of W, Fl, and F2 are stored to the left (toward the higher bits), the interval is corrected, that is, the procedure described above B) ~ B, E) is running.

(Effects of the Invention) As described above, according to the present invention, unlike conventional data compression encoding/decoding devices, the data compression code has a small encoding delay and a small memory capacity for storing coded digits. The encoding/decoding device can be easily configured.

Moreover, since the data compression encoding/decoding apparatus shown in the embodiment can be configured with a simple circuit, it can also be used in high-speed data transmission systems.

It is clear that these can have a great effect in improving efficiency and performance in the future development of high-speed digital communication networks and the widespread use of large-capacity ratio devices.

[Brief explanation of drawings]

Fig. 1 is a basic configuration diagram of the present invention, Fig. 2 is a diagram showing the basics of a decoding device used with the present invention, Fig. 3 is a diagram showing an embodiment of the present invention, and Fig. 4 is a diagram showing the decoding device. It is a figure showing an example of composition. 102, 204... Stochastic parameter generator, 106,
108.105.202.206.207.208...
・Register, 110, 209...Alarm circuit, 111・
...section shortening circuit, 203...xi generator 21
0...Section correction circuit. Agent jr burying L 1 勺 原 1]'+'ff -)
Figure 1 1ot Input terminal, to. Out-h terminal Fig. 2 212 Equal to line 7 in Fig. 1 Fig. 3 IQ+ Input terminal 108M bit register + 09 Output terminal Fig. 4 Timing Iris

Claims (1)

[Claims] Using a predetermined method according to the information digits that are input in sequence, predetermined intervals on the number line are sequentially changed, and the numerical representation of the real numbers included in the finally obtained interval is obtained. In a data compression encoding device that outputs a code digit string for an input information digit string, the contents of a register storing the value at one end of the interval are monitored and a carry alarm signal is generated according to a predetermined rule. and an interval shortening circuit that limits carry propagation to a certain length or less by shortening the width of the interval when a carry alarm signal is generated. Compression encoding device.