JPS6242355B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory device having features in an arrangement of memory cells and a decoder circuit, particularly an N-type memory device.
The present invention relates to a memory device composed of MOS transistors (MOST).

[Background of the invention]

Regarding semiconductor memory using conventional N-type MOST, Digest of 1977, International Solid State Conference, pp. 12-13
Page (Digest of 1977 IEEE International Solid−
State Circuit Conference, pages 12-13), it is divided into two memory arrays,
A data line decoder is arranged between each memory array, and a word line decoder is arranged in each memory array orthogonally to the data line decoder. Further, first and second internal address signals are supplied from a common address buffer to these data line and word line decoders in a time-series manner, and the data line decoder receives the first and second internal address signals from a common address buffer. It is connected to the address buffer mentioned above by a cut MOST that turns off and on at the time of input.

A first external address signal is supplied to the address buffer, and a corresponding first internal address signal causes the word line decoder to operate. this,
The cut MOST is off, and this first
The internal address signal is not supplied to the data line decoder. Next, when a second external address signal is supplied to the address buffer,
The second internal address signal is output from the address buffer, but at this time, the cut MOST is on, so the second internal address signal is
It is supplied to both the data line and word line decoders.
Therefore, the data line and word line decoders are
However, in order to store the information of the first address signal by the word line decoder, a cutting MOST is provided at the word line decoder output section, and the word line is When the decoder operates, this cut MOST is turned off. In this way, the word line decoder outputs information on the first address signal, and the data line decoder outputs information on the second address signal.

However, in a memory device with such a configuration, the second
The internal address signal causes both the data line and word line decoders to operate, which increases the load capacity of the address buffer, which is undesirable from the viewpoint of speeding up. Furthermore, as described in JP-A-51-74535, when the word line is formed of polysilicon and a memory cell in which the word line is miniaturized is used, the resistance of the word line is high. . Therefore, in order to reduce the propagation time of signals on word lines, it is desirable to have a relatively large number of memory arrays. In such a memory device consisting of a large number of memory arrays, the word line decoders are distributed at many locations, so if the conventional technology were to be used as is, it would be necessary to output address buffers to all the word line decoders. New supply wiring is required to supply the signal. This reduces the degree of integration. Further, Japanese Utility Model Application Publication No. 51-163830 discloses a technique in which a memory array is divided into two and input/output lines are arranged between the memory arrays. However, since multiple sets of input/output lines are not provided, control is difficult, and wiring is required above the decoder, making circuit layout difficult.

[Purpose of the invention]

The present invention was made to solve the problems of the conventional art, and an object of the present invention is to provide a memory device that can operate at high speed. A further object of the present invention is to provide a memory device that is highly integrated and capable of high-speed output.

[Summary of the invention]

For this purpose, in the memory device according to the present invention, the data line decoder and the word line decoder are connected to the address buffer via the common address signal line, and the word line decoder is connected to the common address signal line. , are connected via switch means. When the address buffer outputs a first address signal, the switch means is turned on and the first address is applied to both the word line decoder and the data line decoder. The data line decoder has means therein for inactivating the data line decoder when receiving this first address signal, and the action of this means causes the data line decoder to respond to this first address signal. Does not respond to signals. Thereafter, when the second address signal is output from the address buffer, the switch means is turned on, and the second address signal is not input to the word line decoder, and the data line decoder responds to address signals. In this way, the word line decoder and the data line decoder respond sequentially to the first and second address signals.

Furthermore, in the memory device according to the present invention, by dividing the memory array into a large number of parts, the parasitic capacitance and resistance value of word lines and data lines can be reduced, and the memory device can be driven at high speed. By arranging multiple sets of common data lines, the length of the control line from the data line decoder for connecting the common data line and the data line can be shortened, and the number of outputs can be increased at high speed with extremely low signal delay. It is possible to provide a memory device that can accommodate a large number of memory devices, and facilitates circuit arrangement and control.

〔Example〕

The present invention will be explained below with reference to Examples.

2A, 2B, 2C, 2D, 2, 2, 2,
2 is a memory array each containing a plurality of memory cells, and a word line (made of polysilicon) 4
Memory cells are provided at the intersections of A to 4H, 4 to 4, and data lines (made of aluminum) 6A, 6Q, 6, and 6. However, memory cells are not located at all of these intersections;
As described in No. 51-74535, a memory cell is provided at one of the two intersection points.
Word lines 4A to 4D, etc. are memory cell array 2A,
It is commonly provided in 2B etc. A preamplifier (not shown) is provided between a pair of adjacent data lines. Further, this pair of data lines are connected to common data lines 18, 18 or 19, 19. Half of the external address signal (first external address signal) is first input to the address buffer 10, and the corresponding half of the internal address signal (first internal address signal) is input to the latch circuit 12.
be taken in. The output of this latch circuit 12 is sent to all decoders, that is, word line decoders 16A, 16B, 1 through an internal address signal line 20.
6A, 16, data line decoders 14A to 14
D, is supplied.

Word line decoder 16A, 16B, 16, 1
6B is provided between a pair of memory cell arrays adjacent to each other in the direction in which the word lines extend, and data line decoders 14A, 14B, 14C, 14D
are provided between a pair of memory cell arrays adjacent in the direction in which the data lines extend.

The internal address signal line 20 includes a first signal line portion 20A provided in parallel to the word line 4A, etc.
It consists of second signal line portions 20B and 20C connected to the middle of this first signal line portion and provided in parallel to the data line 6A and the like.

The first signal line portion 20A is provided in the direction of the data line decoders 14A to 14D and is connected to each of the data line decoders 14A to 14D (this connection point is not shown).

The second signal line portions 20B, 20C are connected to the word line decoders 16A, 16B, 16, 16 via the switch MOSTQ _C (FIG. 2).

The second signal line portions 20B and 20C are connected to the first signal line portion at a distance from the connection point between the data line decoders 14B and 14D and the first signal line portion 20A, respectively, when viewed from the address buffer 12. has been done. In addition, the second signal line portion 20
B, 20C are viewed from the address buffer 12,
The data line decoders 14A and 14C are connected to the first signal line portion 20A in the vicinity thereof.

Therefore, the second signal line portion 20B is connected to the first signal line portion 20A and the data line decoders 14A, 14.
It is connected to the first signal line portion in the middle of the connection point with B.

Address latch circuit 14, word line decoder 1
FIG. 2 shows a detailed circuit diagram of a portion of the word line 4A of the data line decoder 14A and a portion of the data line decoder 14A related to the data lines 6A and 6B. The other data line decoders and word line decoders also have the same configuration as the data line decoders and word line decoders shown in FIG. FIG. 3 is a time chart of control signals of the circuit shown in FIG. A first external address signal A ₀ -A _o is input to address buffer 10 via line 8 . When a high-level clock signal _φ6 is input to the address buffer 10 at time _T1 , (n+1) pairs of signals _a0 , ₀ , _a1 , ₁ , . . .
...A first internal address signal consisting of a _o and _o is output. ₀ , ₁ , ...... _o is a ₀ , a ₁ , ...... a
_o , high and low levels are reversed. At that time, the precharge signal φ applied to the latch circuit 12
₅ has already changed from high level to low level. Since the signal _φ5 was at a high level until then, the node 25 in the partial latch circuit 12A _{became MOSTQ6.}
is precharged to a high potential (V volts). The signal a ₀ is applied to the gate of MOSTQ ₅ . When signal a ₀ is high level, MOSTQ ₅ is turned on. As a result, the potential at node 25 becomes low level, and MOSTQ ₃ is turned off. Since the high level signal a ₀ is also applied to the gate of MOSTQ ₄ , the high level internal address signal a ₀ ' is output on line 20 from the source of MOSTQ ₄ . If the signal a ₀ is at a low level, MOSTQ ₄ and Q ₅ are in an off state, and the potential at the node 25 remains at a high level. Therefore MOSTQ ₃ is in the on state.
As a result, internal address signal a ₀ ' becomes low level. In this way, the signal a ₀ ' takes a level corresponding to the high and low levels of the signal a ₀ . The other MOSTs ₃ , ₄ , ₅ , ₆ in the partial latch circuit 12A are _MOSTQ3 , _Q4 ,
The signal ₀ is converted into the corresponding signal ₀ ' using exactly the same principle as the operation of Q ₅ and Q ₆ . In the same way, the latch circuit 12 outputs the first internal address signals a ₁ ,
The first internal address signals a _{1 ′} , _{1 ′} , . . . a _o ′, _o ′ corresponding to ₁ , .
The reason for providing this latch circuit 12 will be described later. Until time _T1 , the signals _a0' - _o ' on line 20 are all at a low level. Internal address signal line 20 is made of aluminum. The operation of the word line decoder will be explained using the word line decoder 16A as an example.

Until time _T1 , the precharge signal _φ3 remains at high level, so the gate of MOSTQ _XA is
It is precharged to a high potential via MOSTQ _XB and Q _XC , and MOSTQ _XA is in the on state. MOSTQ _X0 with source and drain connected in common
~Q The low level signal on line 20 is applied to the gate of _Xo , and all of these MOSTs are in the off state. MOSTQ _XB is always on. Signal _φ7 applied to the drain of MOSTQ _XA
is at a low level, so the word line 4A is at a low level. When time T ₁ is reached, signal φ ₃ becomes low level and MOSTQ _XC is turned off. On the other hand, at this time, the latch circuit 12 outputs signals _a0 ' to _o '. Of these signals, half of the signals are at high level and the rest are at low level. Among these signals, a ₀ ′, a ₁ , ………a _o ′ are sent via MOSTQ _C
MOSTQ _X0 ~ Q Added to _Xo . When these signals are all low, MOSTQ _X0 -Q _Xo all remain off and the gate of MOSTQ _XA remains precharged to a high potential. At time _T2 , the signal _φ7 goes high, and the word line 4A
A high level signal is output to select the word line 4A. If at least one of the signals a ₀ ' to _{a o} ' is at a high level, at least one of MOSTQ _X0 to Q _Xo is turned on, and the gate of MOSTQ _XA is discharged to a low potential. Therefore, word line 4
A remains at a low level. Thus word line 4
A is selected or unselected by address signals a ₀ -a _o . When the word line 4A is selected, the storage signal of the memory cell MC is read onto the data line 6A. The dummy word line D _W is also selected in the same way,
The contents of the dummy cell DMC are output onto the data line 6B adjacent to the data line 6A. The signals on these data lines 6A and 6B are preamplified (not shown).
The differential width is amplified by On the other hand, at time T ₃ , signal φ ₁ goes low, MOSTQ _C is cut off, and word line decoder 16A is isolated from line 20. As a result, the first internal address signal taken in via MOSTQ _C is
MOSTQ _X0 ~Q Stored at the gate of _Xo . Word line decoder 16A decodes using this stored first internal address signal. Therefore, the potential of the word line 4A does not change thereafter.

The above operation period T ₁ of the word line decoder 16A
~ _T4 , data line decoder 14A is inactive. That is, since the signal _φ2 applied to the gate of MOSTQ _GA is at a low level, MOSTQ _GA
is off.

Therefore, MOSTQ _Y0 to Q _Yo , whose sources and drains are connected in common, are always off regardless of the levels of the signals _a0 ' to _ao ' applied to their gates. In this way, MOSTQ _GA cooperates with precharge MOSTQ _YD to control the data line decoder 14 to be inactive. During this period, the signal _φ4 is at a high level until time _T2 , and therefore,
Through MOSTQ _YC and Q _YA and Q _YB respectively,
The gates of MOSTQ _YE and Q _YF are precharged to a high potential. At this time, the signals φ ₈ and φ ₉ applied to the drains of MOSTQ _YE and Q _YF are at low level, and the data lines 6A, 6, 6B, and 6 are separated from the common data lines 18, 18, 19, and 19, respectively. ing. At time T ₂ when the word line decoder, for example 16A, completes its operation, the signal φ ₄ changes to low level and MOSTQ _YC and Q _YD are turned off.

After that, the signal _φ2 becomes high level at time _T5 .
MOSTQ _GA turns on, discharging node 26 to ground potential, and decoder 14A is ready for operation.

The signals φ ₅ and φ ₆ go to high level and low level, respectively, once after time T ₄ and then return to low level and high level, respectively, at time T ₆ .

Between times T ₄ and T ₆ a second external address signal is input to the address buffer 10 via line 8, and at time T ₆ a corresponding second internal address signal is output from this address buffer 10. Ru. Subsequently, address latch 12 outputs a second internal address signal on line 20. In decoder 14A, the signal a ₀ ' on line 20,
a ₁ ′, ......a _o ′ are MOSTQ _Y0 , Q _Y1 , ... respectively
...It is input to the gate of Q _Yo . When all these signals are low level, MOSTQ _YE ,
Q: _YF 's gate is at a high level.

Next, at time _T7 , the signal _φ8 becomes high level,
MOSTQ _YG , _YG turns on and data lines 6A, 6
B is connected to the common data lines 18, 18. At this time, the signal _φ9 is at a low level, so that
MOSTQ _YH , _YH is off and data line 6
A, 6 and common data lines 19, 19 remain separated. Conversely, when _φ8 is at a low level and _φ9 is at a high level, 6,6 is connected to 19,19. In this way, only one of the signals φ ₈ and φ ₉ is set to a high level depending on which of the memory cell arrays 2A and 2 is read out.

If at least one of these signals a ₀ ′, a ₁ ′, ......a _o ′ is at a high level,
The gates of MOSTQ _YE and Q _YF are discharged, and these
MOST is off and 6A, 6B, 6, 6
remains separated from the common data line and is in a non-selected state. In this way, the operation of the data line decoder 14A is completed at time _T7 .

Next, at time _T8 , the address buffer 10 and address latch 12 are reset, and at time _T9 , the word line and data line decoders are reset. As a result, the circuit returns to the initial state corresponding to time _T1 .

During this data line decoder operation, the signal φ
₂ becomes high level and MOSTQ _GA turns on, node 26 is discharged from high level to low level, and when the decoder is not selected, node 2
7 discharges from high level to low level. This potential change is caused between the gate and source of MOSTQ _Y0 ~ Q _Yo .
Capacitive coupling with the internal address signal line occurs through the overlap capacitance between the gate and drain and the stray capacitance between the internal address signal line pair nodes 26 and 27, causing undershoot in the low level internal address signal. Due to this undershoot, MOSTQ _C , which is in the off state, is turned on, and when Q _C is turned on, the high-level internal address signal taken into the word line decoder is discharged to a low level, and this potential change is caused by the capacitance. cause a bond,
MOSTQ _XA gate voltage drops and word line 4A
becomes floating. However, if the latch 12 is provided at the output portion of the address buffer 10, the undershoot can be prevented by the action of MOSTQ ₃ , ₃ , and the above problem will not occur. The latch circuit 2 is provided for this purpose.

〔Effect of the invention〕

In the above operation, the load capacitance of the address latch 12 is small, and therefore the address latch 12 can drive the signal line 20 at high speed. That is, during word line decoder operation, the sources and drains of MOSTQ _Y0 to Q _Yo of the data line decoder 14A are precharged to the same voltage, so
The gate capacitance of these MOSTs is substantially equal to zero, and since the common signal line 20 is made of aluminum, its capacitance can also be reduced. Therefore,
Address latch 12 during word line decoder operation
The influence of these capacitances on the load capacitance seen from the front can be reduced.

Furthermore, when the data line decoder 14A operates,
The word line decoder 16A is based on MOSTQ _C.
Since they are separated from the common signal line 20, the load capacitance seen from the address latch 12 is not affected by the gate capacitance of MOSTQ _X0 to Q _Xo of the word line decoder 16A.

As a result, when the word line is made of polysilicon, the data line is made of aluminum, and the common signal line is made of aluminum, the resistance per unit length of the word line is higher than that of the data line and the common signal line. Even if the number of cells is large, according to the present invention, it is possible to obtain a memory device that can perform a memory cell selection operation at high speed. Furthermore, according to the present invention,
Using a common signal line, it is possible to select memory cells in many memory cell arrays, resulting in a highly integrated memory device.

Further, according to the present invention, by arranging a plurality of sets of common data lines between memory arrays, it is possible to easily provide a high-speed memory device with little signal delay, capable of multiple outputs, and a high-speed circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a memory device according to the present invention when viewed from above, FIG. 2 is a detailed circuit diagram of the main parts of the memory device according to the present invention, and FIG. 3 is a circuit used in the circuit of FIG. 2. This is a time chart of the signal. 2A-2D, 2-2...Memory array, 4
A~4H, 4~4, D _W ...Word line, 6A
~6Q, 6~6...data line, 10...address buffer, 12...address latch circuit 1
2, 14A to 14D...data line decoder, 16
A, 16B, 16, 16... Word line decoder, 18, 18, 19, 19... Common data line.

Claims (1)

[Claims] 1. A memory array 4 consisting of a plurality of words, a plurality of data lines provided to intersect with these, and a plurality of memory cells provided at the intersections of these word lines and data lines. an address buffer for generating an internal address signal in response to an external address signal; a first external address signal for selecting the word line; and a first external address signal for selecting the word line; A common signal line for converting a second external address signal for selection into first and second internal address signals and sequentially sending out the converted first and second internal address signals; word line selection means connected to each of the signal line and the word line for selecting a corresponding word line in response to the first internal address signal; and connected to each of the signal line and the data line. and data line selection means for selecting a corresponding data line in response to the second internal address signal, wherein the memory section is divided into at least two parts in a word line direction and a data line direction. The word line selection means is provided between two of these four memory arrays, and the signal line is composed of the first memory array on the signal line. , while the second internal address signal is being transmitted, are coupled by switch means that are turned on and off, respectively, and the word line selected when the switch means is on continues to be selected even when the switch means is off. The data line selection means is provided perpendicularly to the word line selection means and corresponds to each memory array, and the data line selection means transmits the first internal address signal onto the signal line. While being
While no data line is selected and the second internal address signal is being sent on the signal line, the corresponding data line is selected in response to the second internal address. A memory device comprising: 2. The memory device according to claim 1, wherein the plurality of memory cells are each provided at one of two intersections formed by a pair of the data line and the word line. . 3. A patent claim characterized in that the word line selection means holds the first address signal inputted from the switch means and has means for decoding the held first address signal. The memory device according to item 1. 4 The word line selection means has a plurality of first field effect transistors whose sources and drains are commonly connected, and the switch means connects the gates of each of the first field effect transistors to the common a plurality of second field effect transistors for connection to the signal line of the plurality of first field effect transistors, and the first address signal inputted from the common signal line is connected to the gates of the plurality of first field effect transistors. 4. The memory device according to claim 3, wherein the memory device is a means for holding the memory. 5 The common signal line includes a plurality of first signal lines provided in parallel with the plurality of word lines and a plurality of second signal lines provided in parallel with the plurality of data lines.
The first signal line is connected to the data line selection means, the second signal line is connected to the first signal line, and the word line selection means is connected to the first signal line. 2. The memory device according to claim 1, wherein the memory device is connected to the second signal line via the switching means. 6 The second signal line is connected to the first signal line at a point farther from the connection point between the first signal line and the data line selection means when viewed from the address generation means. The memory device according to claim 5, characterized in that: 7. The second signal line is connected to the first signal line at a point farther from the connection point between the first signal line and the data line selection means when viewed from the address generation means. The memory device according to claim 5, characterized in that: 8 The second signal line connects to the first signal line at a point further away and closer to the connection point between the first signal line and the data line selection means, respectively, from the point of view of the address generation means. The word line selection means includes first and second word line selection means connected to the third and fourth signal lines, respectively. 6. A memory device according to claim 5, characterized in that the memory device comprises: 9 The plurality of word lines have a plurality of first and second data lines, and each of the plurality of data lines has a plurality of first and second data lines, each of which is provided to intersect with the first and second data lines. The first and second word line selection means are connected to the first and second word lines, respectively, and select at least one of the first and second word lines. The data line selection means is connected to the first and second data lines, respectively, and the first and second data lines for selecting the first and second data lines, respectively. 9. The memory device according to claim 8, further comprising data line selection. 10 The word line selection is provided between the plurality of memory cells so as to constitute first and second memory cell arrays separated in the data line direction,
The data line selection means includes first and second data line selection means for selecting data lines respectively connected to memory cells in the first and second memory cell arrays, and 6. The memory device according to claim 5, wherein the signal line is connected to the first and second data line decoding means and the first signal line. 11 The data line selection means includes a plurality of field effect transistors whose sources and drains are commonly connected and whose gates are connected to the common signal line, and which precharges the common sources and drains to a predetermined voltage. and switching means connected to the common source for discharging the common source after the first address signal is input to the common signal line. Claims 1 to 9
The memory device according to any of paragraphs. 12. The memory device according to claim 11, wherein the word line is made of polysilicon and the common signal line is made of aluminum. 13. The memory device of claim 11, wherein the word line is made of polysilicon and the data line is made of aluminum. 14 A plurality of word lines and a plurality of data line pairs which intersect with these lines and are provided in parallel to each other so that when one has information of a high potential, the other has information of a low potential. and a memory unit comprising a set of four memory arrays each consisting of a plurality of memory cells provided at one of two intersections formed by the pair of data lines and the word line; an address buffer for converting a first external address signal for selecting a line and a second external address signal for selecting the data line pair into first and second internal address signals;
a signal line for transmitting the converted first and second internal address signals; connected to each of the signal line and the word line;
word line selection means for selecting a corresponding word line in response to the first internal address signal; and word line selection means connected to each of the signal line and the data line pair and responsive to the second internal address signal. do,
A memory device having data line selection means for selecting a corresponding data line pair, wherein the memory section is configured as a set of four memory arrays divided into two in a word line direction and a data line direction, The data line selection means is provided between two opposing memory arrays divided into two in the data line direction, and the word line selection means is provided between two opposing memory arrays divided into two in the word line direction. provided between each data line selection means and the data line pair of the memory array on one side of each data line selection means, and provided in common to a plurality of said data line pairs; A first common data line pair arranged to be connectable to the data line pair, each data line selection means, and a data line pair provided between the data line pair of the memory array on the other side of each data line selection means. , and is provided in common to the plurality of data line pairs and is connectably arranged to the data line pair.
A common data line pair is provided, and the decode signal of the data line selection means allows
A memory device comprising means for commonly controlling connections between a data line pair and each of the common data line pairs.