JPS6240951B2 - - Google Patents
Info
- Publication number
- JPS6240951B2 JPS6240951B2 JP16709380A JP16709380A JPS6240951B2 JP S6240951 B2 JPS6240951 B2 JP S6240951B2 JP 16709380 A JP16709380 A JP 16709380A JP 16709380 A JP16709380 A JP 16709380A JP S6240951 B2 JPS6240951 B2 JP S6240951B2
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- resistor
- input terminal
- output
- inverting input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M7/2173—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a biphase or polyphase circuit arrangement
Description
【発明の詳細な説明】
この発明は、交流信号を直流信号に変換する全
波整流回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a full-wave rectifier circuit that converts an alternating current signal into a direct current signal.
従来の静止形継電器等において、整定と全波整
流を行なう場合は、第１図のように回路を構成す
るのが普通であつた。すなわち、まず、演算増幅
器と可変抵抗１２と抵抗１３とでなる反転増幅回
路で入力信号を所定の大きさ（整定用の可変抵抗
１２によつて調整できる）に変換し、演算増幅器
１４、抵抗１５，１６、ダイオード１７，１８よ
りなる半波整流回路１９で半波整流し、この半波
整流出力の方が抵抗２１を介して送られる交流信
号よりも２倍の大きさになるよう抵抗２０，２１
の値を定めて、交流信号と半波整流出力とを重ね
合わせることによつて全波整流出力を合成し、こ
れをさらに演算増幅器２２と抵抗２３よりなる反
転増幅回路で増幅するという回路構成をとる。と
ころが、第１図から分るように、従来のものは部
品点数が多く、回路構成も複雑であるという欠点
がある。 In conventional static relays and the like, when performing settling and full-wave rectification, it was common to configure a circuit as shown in FIG. That is, first, an inverting amplifier circuit consisting of an operational amplifier, a variable resistor 12, and a resistor 13 converts an input signal into a predetermined magnitude (which can be adjusted by the variable resistor 12 for setting), and then converts the input signal to a predetermined magnitude (adjustable by the variable resistor 12 for setting). , 16, a half-wave rectifier circuit 19 consisting of diodes 17, 18 performs half-wave rectification, and the resistor 20, 21
The circuit configuration is such that a full-wave rectified output is synthesized by determining the value of , superimposing the alternating current signal and the half-wave rectified output, and further amplifying this with an inverting amplifier circuit consisting of an operational amplifier 22 and a resistor 23. Take. However, as can be seen from FIG. 1, the conventional device has the drawbacks of a large number of parts and a complicated circuit configuration.
この発明は、上記に鑑み、部品点数が少なくて
しかも簡単な回路構成で整定と全波整流とを行な
える全波整流回路を提供することを目的とする。 In view of the above, an object of the present invention is to provide a full-wave rectifier circuit that can perform settling and full-wave rectification with a small number of parts and a simple circuit configuration.
以下、この発明の一実施例を図面にもとづいて
説明する。第２図は、この発明の一実施例の構成
を示す図面である。入力端子３１は可変抵抗３３
を介して抵抗３４の一端と第２の演算増幅器３７
の非反転入力端子に接続される。入力端子３２
は、第１の演算増幅器３６の非反転入力端子と出
力端子４２に接続さすれる。前記抵抗３４の他端
と抵抗３５の一端と第３のダイオード４０のアノ
ードは前記第１の演算増幅器３６の反転入力端子
と接続される。前記抵抗３５の他端と前記第２の
演算増幅器３７の反転入力端子と第１のダイオー
ド３８のカソードと第２のダイオード３９のカソ
ードは出力端子４１に接続される。前記第１の演
算増幅器３６の出力端子は前記第１のダイオード
３８のアノードと前記第３のダイオード４０のカ
ソードに接続される。前記第２の演算増幅器３７
の出力端子は前記第２のダイオード３９のアノー
ドに接続される。 Hereinafter, one embodiment of the present invention will be described based on the drawings. FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. Input terminal 31 is variable resistor 33
one end of the resistor 34 and the second operational amplifier 37 via
is connected to the non-inverting input terminal of Input terminal 32
is connected to the non-inverting input terminal and output terminal 42 of the first operational amplifier 36. The other end of the resistor 34, one end of the resistor 35, and the anode of the third diode 40 are connected to the inverting input terminal of the first operational amplifier 36. The other end of the resistor 35, the inverting input terminal of the second operational amplifier 37, the cathode of the first diode 38, and the cathode of the second diode 39 are connected to the output terminal 41. The output terminal of the first operational amplifier 36 is connected to the anode of the first diode 38 and the cathode of the third diode 40. the second operational amplifier 37
The output terminal of is connected to the anode of the second diode 39.
上記の構成で、入力端子３２に対して入力端３
１を“正”とする入力信号の場合、第１の演算増
幅器３６の出力は“負”に偏位し、第１の演算増
幅器３６の反転入力端子の仮想零点が保持される
ので、第３のダイオード４０は順方向にバイアス
される。また第１の演算増幅器３６の反転入力端
子の仮想零点が保持されるので、可変抵抗３３、
抵抗３４の接続点の電圧e′iは、入力電圧をｅi ＋
可変抵抗３３の抵抗値をR3、抵抗３４の抵抗値
をR4とすれば、
e′i＝ｅｉ ＋／Ｒ３＋Ｒ４×R4
となる。一方第２の演算増幅器３７の出力は
“正”に偏位するので、第２のダイオード３９が
順方向にバイアスされ、第２の演算増幅器３７の
出力は第２のダイオード３９を介して第２の演算
増幅器３７の反転入力端子へ帰還される。従つて
第２の演算増幅器３７の反転入力端子と非反転入
力端子の電位は等しくなる。第２の演算増幅器３
７の非反転入力端子は可変抵抗３３と抵抗３４の
接続点に接続され、第２の演算増幅器３７の反転
入力端子は出力端子４１と接続されているので、
出力電圧e0 +は
e0 +＝e′i＝ｅｉ ＋／Ｒ３＋Ｒ４×R4
となる。出力電圧e0 +が“正”であり第１の演算
増幅器３６の出力が“負”であるから第１のダイ
オード３８は逆方向にバイアスされてカツトオフ
となる。抵抗３４および抵抗３５を介して第１の
演算増幅器３６の仮想零点へ流れる電流i1、i2
は、抵抗３５の抵抗値をR5として、
i1＝ｅｉ ＋／Ｒ３＋Ｒ４
i2＝ｅ０ ＋／Ｒ５＝ｅｉ ＋・Ｒ４／（Ｒ３＋
Ｒ４）Ｒ５
となる。i1＋i2の電流は第３のダイオード４０を
介して第１の演算増幅器３６の出力端子へ流れ込
む。 In the above configuration, input terminal 3 is connected to input terminal 32.
In the case of an input signal in which 1 is "positive", the output of the first operational amplifier 36 is shifted to "negative", and the virtual zero point of the inverting input terminal of the first operational amplifier 36 is maintained, so that the third diode 40 is forward biased. Further, since the virtual zero point of the inverting input terminal of the first operational amplifier 36 is maintained, the variable resistor 33,
The voltage e′ i at the connection point of the resistor 34 is the input voltage e i +
If the resistance value of the variable resistor 33 is R 3 and the resistance value of the resistor 34 is R 4 , then e′ i =e i + /R 3 +R 4 ×R 4 . On the other hand, since the output of the second operational amplifier 37 is shifted to "positive", the second diode 39 is biased in the forward direction, and the output of the second operational amplifier 37 is transferred to the second diode 39 through the second diode 39. is fed back to the inverting input terminal of the operational amplifier 37. Therefore, the potentials of the inverting input terminal and the non-inverting input terminal of the second operational amplifier 37 become equal. Second operational amplifier 3
The non-inverting input terminal of the second operational amplifier 37 is connected to the connection point between the variable resistor 33 and the resistor 34, and the inverting input terminal of the second operational amplifier 37 is connected to the output terminal 41.
The output voltage e 0 + is e 0 + = e′ i = e i + /R 3 +R 4 ×R 4 . Since the output voltage e 0 + is "positive" and the output of the first operational amplifier 36 is "negative", the first diode 38 is reverse biased and cut off. Currents i 1 , i 2 flow to the virtual zero point of the first operational amplifier 36 via the resistor 34 and the resistor 35
Here, the resistance value of the resistor 35 is R5 , i 1 = e i + /R 3 +R 4 i 2 = e 0 + /R 5 = e i +・R 4 /(R 3 +
R4 ) R5 . A current of i 1 +i 2 flows through the third diode 40 to the output terminal of the first operational amplifier 36 .
入力端子３２に対して入力端子３１を“負”と
する入力信号の場合、第１の演算増幅器３６の出
力は“正”に偏位し、第１の演算増幅器３６の反
転入力端子の仮想零点が保持されるので、第３の
ダイオード４０は逆方向にバイアスされカツトオ
フとなり、第１のダイオード３８は順方向にバイ
アスされる。第１の演算増幅器３６の出力は第１
のダイオード３８および抵抗３５を介して第１の
演算増幅器３６の反転入力端子へ帰還される。第
１の演算増幅器３６の反転入力端子の仮想零点に
対して抵抗３４および抵抗３５を介して流入する
電流i1、i2は入力電圧をｅi −として、
i1＝ｅｉ −／Ｒ３＋Ｒ４、i2＝ｅ０／Ｒ５
となる。仮想零点へ流入する電流の和は零となる
から、出力電圧e0 -は
e0 -＝−ｅｉ −／Ｒ３＋Ｒ４×R5
となる。一方第２の演算増幅器３７の非反転入力
端子へは可変抵抗３３および抵抗３４で分圧され
た“負”の信号が入力され、反転入力端子へは
“正”の出力電圧e0が入力されるので、出力は
“負”に偏位し第２のダイオード３９は逆バイア
スされてカツトオフとなる。 In the case of an input signal that makes the input terminal 31 "negative" with respect to the input terminal 32, the output of the first operational amplifier 36 is deviated "positive", and the virtual zero point of the inverting input terminal of the first operational amplifier 36 is shifted to "positive". is held, so the third diode 40 is reverse biased and cut off, and the first diode 38 is forward biased. The output of the first operational amplifier 36 is the first
is fed back to the inverting input terminal of the first operational amplifier 36 via the diode 38 and the resistor 35. The currents i 1 and i 2 flowing into the virtual zero point of the inverting input terminal of the first operational amplifier 36 via the resistor 34 and the resistor 35 are expressed as i 1 =e i − /R 3 where the input voltage is e i − . +R 4 , i 2 =e 0 /R 5 . Since the sum of the currents flowing into the virtual zero point becomes zero, the output voltage e 0 - becomes e 0 - = -e i - /R 3 +R 4 ×R 5 . On the other hand, a "negative" signal divided by the variable resistor 33 and the resistor 34 is input to the non-inverting input terminal of the second operational amplifier 37, and a "positive" output voltage e 0 is input to the inverting input terminal. Therefore, the output is biased "negative" and the second diode 39 is reverse biased and cut off.
R4＝R5とすれば、絶対値の等しい入力信号に
対して、
e0 -＝−ｅｉ −／Ｒ３＋Ｒ４×R5
＝−−ｅｉ ＋／Ｒ３＋Ｒ４×R4＝ｅｉ ＋／Ｒ３＋
Ｒ４×R4＝e0 +
となり、入力信号の極性に関係なく出力には、入
力信号の絶対値を可変抵抗３３と抵抗３４で分圧
した値と等しい“正”の信号が得られる。また入
力信号の絶対値が変化しても出力が一定の値とな
るよう整定する場合は、入力信号の絶対値の比と
（R3＋R4）の比が等しくなるように可変抵抗３３
の抵抗値を変化すれば良い。 If R 4 = R 5 , then for input signals with equal absolute values, e 0 - =-e i - /R 3 +R 4 ×R 5 =--e i + /R 3 +R 4 ×R 4 = e i + /R 3 +
R 4 ×R 4 =e 0 + , and a “positive” signal equal to the value obtained by dividing the absolute value of the input signal by the variable resistor 33 and the resistor 34 is obtained at the output regardless of the polarity of the input signal. In addition, when setting the output to a constant value even if the absolute value of the input signal changes, use the variable resistor 33 so that the ratio of the absolute value of the input signal and the ratio of (R 3 + R 4 ) are equal.
All you have to do is change the resistance value.
なお、ダイオード８，９，１０の向きを反対に
することによつて“負”の出力を得ることもでき
るが、説明は省略する。 Note that a "negative" output can also be obtained by reversing the directions of the diodes 8, 9, and 10, but a description thereof will be omitted.
以上のようにこの発明によれば、反転増幅器の
仮想零点が常に保たれ、反転増幅器の入力抵抗と
整定抵抗の一部を共用できるような構成として、
整定抵抗で分圧された信号を、反転増幅器と比反
転増幅器に入力し、出力信号と入力信号が異極性
の場合は反転増幅器の出力を出し、出力信号と入
力信号が同極性の場合には非反転増幅器の出力を
出すようにしたので、部品点数も少なく簡単な構
成で整定と全波整流を行なうことができる。 As described above, according to the present invention, the virtual zero point of the inverting amplifier is always maintained, and a part of the input resistance and the setting resistance of the inverting amplifier can be shared.
The signal divided by the setting resistor is input to the inverting amplifier and the ratio inverting amplifier. If the output signal and the input signal have different polarities, the inverting amplifier outputs the output signal, and if the output signal and the input signal have the same polarity, the output signal is output from the inverting amplifier. Since the output is output from a non-inverting amplifier, the number of parts is small and it is possible to perform settling and full-wave rectification with a simple configuration.
第１図は従来例の回路図、第２図は本発明の一
実施例の回路図である。
１１，１４，２２，３６，３７……演算増幅
器、１９……半波整流回路、３１，３２……入力
端子、４１，４２……出力端子。
FIG. 1 is a circuit diagram of a conventional example, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 11, 14, 22, 36, 37... operational amplifier, 19... half-wave rectifier circuit, 31, 32... input terminal, 41, 42... output terminal.
Claims (1)
れた第１、第２の演算増幅器を有し、該第１の演
算増幅器の反転入力端子を可変抵抗と抵抗の直列
回路を介して該入力端子に接続するとともに該第
１の演算増幅器の出力端子を第１の一方向性素子
を介して該出力端子に接続し、且つ該第１の演算
増幅器の反転入力端子と該第１の演算増幅器の出
力端子との間に第２の一方向性素子を接続し、該
第１の演算増幅器の反転入力端子と該出力端子と
の間に抵抗を接続し、さらに、該第２の演算増幅
器の非反転入力端子を該可変抵抗と抵抗との接続
点に接続し、該第２の演算増幅器の出力端子を、
第３の一方向性素子を介して該出力端子に接続す
るとともに、該第２の演算増幅器の反転入力端子
に接続し、該第１、第２、第３の一方向性素子の
それぞれの方向を該入力端子から該出力端子への
方向に対して同一とした全波整流回路。 ２ 該第１、第２、第３の一方向性素子をダイオ
ードでそれぞれ構成した特許請求の範囲第１項記
載の全波整流回路。[Claims] 1. A first operational amplifier and a second operational amplifier are inserted in parallel between an input terminal and an output terminal, and the inverting input terminal of the first operational amplifier is connected to a variable resistor and a resistor. an inverting input terminal of the first operational amplifier; and an output terminal of the first operational amplifier, a resistor is connected between the inverting input terminal of the first operational amplifier and the output terminal, and further, The non-inverting input terminal of the second operational amplifier is connected to the connection point between the variable resistor and the resistor, and the output terminal of the second operational amplifier is connected to the connection point between the variable resistor and the resistor.
connected to the output terminal via a third unidirectional element, and connected to the inverting input terminal of the second operational amplifier, and connected to each direction of the first, second, and third unidirectional elements. A full-wave rectifier circuit in which is the same in the direction from the input terminal to the output terminal. 2. The full-wave rectifier circuit according to claim 1, wherein the first, second, and third unidirectional elements are each composed of a diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16709380A JPS5791673A (en) | 1980-11-27 | 1980-11-27 | Full wave rectifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16709380A JPS5791673A (en) | 1980-11-27 | 1980-11-27 | Full wave rectifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5791673A JPS5791673A (en) | 1982-06-07 |
| JPS6240951B2 true JPS6240951B2 (en) | 1987-08-31 |
Family
ID=15843284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16709380A Granted JPS5791673A (en) | 1980-11-27 | 1980-11-27 | Full wave rectifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5791673A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6338410A (en) * | 1986-07-31 | 1988-02-19 | コクヨ株式会社 | Chair |
| JPS6338412A (en) * | 1986-07-31 | 1988-02-19 | コクヨ株式会社 | Chair |
| JPH0414965B2 (en) * | 1986-07-31 | 1992-03-16 | Kokuyo Kk | |
| JPH0414966B2 (en) * | 1986-07-31 | 1992-03-16 | Kokuyo Kk |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2590197B2 (en) * | 1988-05-10 | 1997-03-12 | 株式会社東芝 | Half-wave rectifier circuit and peak hold circuit |
-
1980
- 1980-11-27 JP JP16709380A patent/JPS5791673A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6338410A (en) * | 1986-07-31 | 1988-02-19 | コクヨ株式会社 | Chair |
| JPS6338412A (en) * | 1986-07-31 | 1988-02-19 | コクヨ株式会社 | Chair |
| JPH0414965B2 (en) * | 1986-07-31 | 1992-03-16 | Kokuyo Kk | |
| JPH0414966B2 (en) * | 1986-07-31 | 1992-03-16 | Kokuyo Kk |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5791673A (en) | 1982-06-07 |
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