JPS6239952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention mainly relates to an operation test of a group of counters in a timepiece circuit system. The counters referred to here include second, minute, hour, day, day, and month counters for clocks, minute and hour counters for setting alarms 1 and 2, and message counters for alarms 1 and 2 ( 1/100 counter for stopwatch (1/100 counter) to display the purpose of setting the alarm time in a picture on the dot matrix liquid crystal display.
These include seconds, 1/10 seconds, seconds, minutes, and hour counters. Here, I would like to briefly touch on the operation test of the counter group. A counter is generally a circuit that counts according to an input signal.
The input signal is 1 in a decimal counter that counts up to "9".
If it comes in every second, "0" to "9"
It will take 10+a seconds to check the counting operation. Therefore, if the input signal is set every 0.1 seconds, the check time for a similar counting operation is 1+a
It will only take seconds. Therefore, if the detection speed of the tester for checking the counting operation is fast, the input signal to the counter, that is, the test signal, can be made as fast as possible. A test circuit is a circuit for testing a group of counters in a short period of time.

Furthermore, if this test operation is used when setting the time, etc., corrections can be made in a short time.

Next, a conventional test circuit is shown in FIG. In the figure, 201 to 208 are seconds, 10 seconds, minutes,
10 minute, hour, day, day, and month counter circuits, 2
19 to 221 are minutes for setting the alarm time, 10 minutes,
and time counter circuits, 225 to 231 are 1/100 seconds, 1/10 seconds, seconds, 10 seconds,
Minute, 10 minute, and hour counter circuits, 239 is a terminal for a correction switch C, 240 is a test terminal, and 241 to 242 are anti-chattering circuits. This refers to a circuit that prevents the chattering prevention circuit mentioned here from malfunctioning, and is designed so that it will not be treated as a switch signal unless it is on for more than a certain time constant as a switch signal.

Note that this circuit has a circuit configuration that ensures that if the period of logic level (hereinafter referred to as L/L) "1" is approximately 14 milliseconds or longer, it is taken in as a switch signal.

In the test operation prohibited state in the conventional test circuit, the test terminal input 272 is L/L "1", so the output 273 of the chattering prevention circuit 242
becomes L/L "0" through the inverter 274, and the test clock 245 becomes L/L "0". Therefore, no test clock is supplied to the counter group, and each counting operation is performed using a 1-second clock signal 247 in the basic clock mode and a 100 hertz (hereinafter referred to as Hz) signal 263 in the stopwatch mode. In the time correction mode, the minute set signal 255, hour set signal 256, date set signal 257, day set signal 258, and month set signal 259 are set for the clock, and in the alarm time correction mode, the minute set signal 260 and hour set signal for the alarm are set. signal 26
2 performs a similar counting operation.

Next, when the test terminal is operated to enter the test operation state, the test terminal input 272 is L/L "0", so the output 27 of the chattering prevention circuit 242
3 becomes L/L “1” via the inverter 274. In this state, when the test signal 270 is input from the switch C terminal 239, the NAND gate 24
3 and an inverter 244 are formed to generate a test clock 245. This test clock 2
Since 45 is input to all counters, all counters start test operations at the same time.

As is clear from Figure 2, the test circuit with this configuration has the disadvantage that the test clock is supplied to all the counters, which increases the number of wiring lines and makes the pattern complex. 270 is input to correction switch C, it is input to the chattering prevention circuit 241 of correction switch C, and the frequency is approximately 36Hz (1/0.014×2≒36).
Even if the above clock is applied as a test signal to the switch C terminal 239, the period of L/L "1" will be 14.
Since the time is less than milliseconds, the chattering prevention circuit does not generate a test clock as described above, and it also has the disadvantage that it is impossible to perform high-speed determination.

The purpose of the present invention is to improve the test circuit so that the tester can quickly judge the test operation and make corrections in a short time even when setting the time. The goal is to simplify the wiring pattern by minimizing the number of signal lines used.

Hereinafter, the present invention will be explained in detail based on Examples. FIG. 1 is a block diagram of an electronic timepiece, and the present invention is directed to a counter group 10 for the timepiece in this block diagram.
4 to 108 and 110, counter groups 111 to 114 for time setting of alarms 1 and 2, message counters 115 and 1 for alarms 1 and 2
16. Stopwatch counter group 119~
122, switch C145, test terminal 147,
and the chattering prevention circuit 148. In FIG. 1, each block is as follows.

That is, 101 is an oscillator, 102 is an oscillation circuit, 1
03 is a frequency divider, 104 is a second counter circuit for a watch, 105 is a minute counter circuit for a watch, 106 is an hour counter circuit for a watch, 107 is a day counter circuit, and 108 is a day counter circuit. Also, 10
9 is a month-end processing circuit, 110 is a month counter circuit, 1
11 is a minute counter circuit for alarm 1, 112 is an hour counter circuit for alarm 1, 113 is a minute counter circuit for alarm 2, 114 is an hour counter circuit for alarm 2, 115 is a message counter circuit for alarm 1, 116 is a message counter circuit for alarm 2, 117 is a stopwatch control circuit, 118 is a clock forming circuit for the stopwatch, and 119 is a 1/1/2 block for the stopwatch.
100 and 1/10 second counter circuits, 120 is a second counter circuit for stopwatch, 121 is a minute counter circuit for stopwatch, 122 is an hour counter circuit for stopwatch, 123 is a data bus selection and alarm coincidence detection circuit, 124 is a display Decoder, 125 is an alarm control circuit, 12
6 is a piezoelectric or electromagnetic buzzer, 127 is a ring stop control circuit, 128 is a power-on clear circuit, 12
9 is a liquid crystal 7 segment driver circuit, 130 is a liquid crystal 7 segment display, 131 is a common waveform generation circuit for liquid crystal 7 segment display, and 132 is a latch clock control circuit for liquid crystal 7 segment display. 133 is a display scan signal generation circuit for the liquid crystal dot matrix section, 134 is a display mode control circuit for the liquid crystal dot matrix section, 135 is a display data storage A for the liquid crystal dot matrix section, 136
137 is a display data storage C of the liquid crystal dot matrix section; 138 is a read timing signal forming circuit for various data; 139 is a display drive signal forming circuit for the liquid crystal dot matrix section; 140 is a common waveform generator circuit for displaying the liquid crystal dot matrix section, 141 is a display driver circuit for the liquid crystal dot matrix section, 142 is a liquid crystal dot matrix display body, 143 is a switch A, 144 is a switch B,
145 is switch C, 146 is switch D, 14
7 is a test terminal, 148 is a switch group chattering prevention circuit, 149 is a system control signal forming circuit, 150 is a data bus line for clock, 15
1 each represents a data bus line for alarm.

FIG. 3 is a test circuit of the present invention, and 305 to 312 in the figure are seconds for a clock, 10 seconds,
Minute, 10 minute, hour, day, day, and month counter circuits, 325 to 327 are alarm 1, 328 to 33
0 is each minute, 10 minute, and hour counter circuit for setting the alarm 2 time, 331 is each message counter circuit for alarm 1, 332 is each message counter circuit for alarm 2, 339-
345 is 1/100 second, 1/10 for stopwatch.
Seconds, seconds, 10 seconds, minutes, 10 minutes, and hour counter circuits. First, when the test operation is prohibited in this circuit, both the test clock signal 355 and the test operation signal 356 become L/L "0".
AND gate 313, 315, 317, 319,
321, 323, 333, 334, 335, 33
6,337,338,346,348,350,
All outputs of 352 and 352 become L/L "0". Therefore, the counter circuit groups 305 to 312 for the timepiece are counted by the one-second signal 357 for the timepiece, and the other counter circuits also perform normal counting operations. Next, the formation of the test clock signal will be explained using FIG. 4. In the figure, 401 is the switch C, 402 is the test terminal, and 403 to 40
6 and 419 to 422, respectively, are protection circuits against excessive input, and the parts surrounded by dotted lines A and B are chattering prevention circuits for each input signal 443 and 452, NAND gates 438, 439, and
NOR gate 440 is a gate for transferring a normal one-shot correction signal and a test clock, and when test terminal 402 is operated to enter test operation, a system reset signal for instantaneously resetting various counter circuits is sent to terminal 465. The system reset signal generating circuit 437 generates a system reset signal. First, in this circuit, the test terminal is not operated when the test operation is prohibited, so the test input signal 451 remains at L/L "1" and the inverter 42
The output 452 of 4 becomes L/L "0". Therefore, the data input 454 of the delay type flip-flop (hereinafter referred to as F/F) 430 becomes L/L "0", and the operation of the sampling clock 444 causes its output 456 to be inverted and set to L/L "1". Ru. Furthermore, the output 4 is transmitted through an inverter 432.
Since 57 becomes L/L "0", AND gate 4
39 is not formed and the output becomes L/L "0",
Even if a test acceleration clock is input from the switch C terminal 401, no acceleration test clock signal is generated from the terminal 464. On the other hand, inverter 43
Since the output 459 of 4 becomes L/L "1", the input signal 442 of L/L "1" from the switch C terminal 401 passes through the NAND gate 408, and the input signal 443 of the chattering prevention circuit is generated. . At this time, the input signal 443 is the sampling clock 4
Period of L/L “1” with 2 or more shots of 44 (Fig. 5,
443 operation timing diagram)),
Switch data 449 and 450 are not generated.

Therefore, in the test operation prohibited state, that is, in the normal state, input from switch C becomes possible, and a one-shot correction signal (Fig. 5, 46
2) is generated at the terminal 464. Next, the operation timing when the test operation is executed is shown in FIG. 6 and will be explained. When the test terminal 402 is operated, the test input signal 451
When L/L is set to “0”, inverter 4
Since the output 452 of F/F 430 becomes L/L "1", the latch output 453 is held at L/L "1" and the output 456 of delay type F/F 430 becomes L/L.
It becomes "0". Further, the output goes through the inverter 432 to the delay type F/F 433, and when the sampling clock 444 changes from L/L "1" to "0", the delay type F/F 4
The output 458 of 33 changes from L/L "1" to "0". Therefore, output 4 from chattering prevention circuit B
57 and 458 are applied as a reset signal 460 to the F/F of the chattering prevention circuit A via a NAND gate 435 and an inverter 436.
Further, since the output 459 becomes L/L "0" via the inverter 434, the NAND gate 408 is not formed and input signals are prohibited even if the switch C terminal 401 is operated. Therefore, the switch data output 44 from the anti-chattering circuit of switch C
Since 9 is L/L "0" and 450 is L/L "1", the output of AND gate 438 is L/L "0".
This means that the function of the chattering prevention circuit is locked.

On the other hand, the output 457 of the inverter 432 is L/L
Since it is set to "1", the switch C terminal 401
If we add a test input signal 442,
AND gate 439 is formed and NOR gate 44
0, and a test clock signal is generated at terminal 464 via inverter 441.

Therefore, this test clock signal is supplied to the test circuit, and how it operates will be explained with reference to FIG. 355 in the figure is a test clock signal, and AND gates 313 and 31 in the front stage of the counter
5,317,319,321,323,333～
338, 346, 348, 350, and 352. These AND gates also have signals that select the counters to test, in order: seconds test 366, minutes test 367, hours test 36.
8. Day test 369, Day test 370, Month test 371, Alarm 1 minute test 374, Alarm 1 hour test 375, Alarm 2 minute test 37
6. Test 377 at alarm 2, message 1
character test 378, message 2 character test 379, stopwatch 1/
100 seconds test 387, stopwatch seconds test 388, stopwatch minutes test 389,
The test 390 signal is input during stopwatch. Therefore, the seconds digit counter 305 for the clock,
The state of the test will be explained by taking up the and 10 second digit counter 306. First, when the test operation is executed, the test operation signal 356 becomes L/L "1",
In this state, if the second test selection signal 366 is set to L/L "1", the AND gate 31
3 is formed to generate the seconds test clock. This clock is a 1 second signal 357 at the OR gate 314.
is logically summed with and supplied to the second counter circuit. Therefore, each time the clock and the 1 second signal 357 are input, the counter advances, and a carry signal 358 from the seconds digit counter is also generated to output seconds and second data 0 to 59 from the 10 seconds digit counter. Therefore, by using a high-speed test clock signal, the 10-second digit can be tested by increasing the digits from the second digit without directly supplying the test clock to the 10-second digit. Further, an inverter 301 and an AND gate 302 are provided so that the second counter circuit is not reset by the test clock signal 355 at this time, and the reset signal 365 of the second counter circuit is set to L/L "0" during the test operation. There is. Similarly, test operations such as the second counter can be performed on other counters as well. Furthermore, in the present invention, when the test operation is prohibited, a signal generated by operating switch C is output from terminal 464 as a correction signal, so this correction signal is supplied to each digit as a correction signal through terminal 355 in FIG. At this time, the signals 366 to 371 and 374 to 379 become selection signals, and the test circuit and the correction circuit are shared.

From the above, the test circuit according to the present invention can directly apply the test clock to the gate of the test circuit without passing it through the anti-chattering circuit, so it is possible to test the counter in a short time using a faster test clock than before. , 10 seconds digit, etc. can be tested consecutively, and the 10 seconds digit can be tested using the carry signal, so there is no need for test wiring for the 10 seconds digit, and similarly, there is no need for wiring for the 10 minute digit, etc. This makes it possible to reduce the number of test clock signal lines wired to the counter in the electronic timepiece circuit, and also has the effect of simplifying the wiring pattern.

[Brief explanation of the drawing]

Figure 1...Block diagram of an electronic clock, Figure 2...
Conventional test circuit, FIG. 3 Test circuit of the present invention, FIG. 4 Test clock control circuit of the present invention, FIG. 5 Operation timing diagram of the test clock control circuit of the present invention 1, FIG. 6... ...Operation timing diagram 2 of the test clock control circuit of the present invention.

Claims (1)

[Claims] 1 Hour, 10 minutes, minutes, 10 seconds, seconds counter 305~
312, switch input terminals 145, 4 input a correction signal from a time correction switch or a test clock signal input from the outside.
01. Test terminal 14 for inputting a test operation signal specifying whether the test operation is prohibited or in the test state.
7,402, a first anti-chattering circuit A that is connected to the switch input terminal and prevents chattering of the correction signal from the switch input terminal; a second anti-chattering circuit A that prevents chattering of the test input signal from the test terminal; Circuit B inputs the signal from the switch input terminal and the signal from the first chattering prevention circuit;
a first gate circuit that inhibits the signal from the first chattering prevention circuit in a test state in accordance with the output from the chattering prevention circuit of the switch input terminal, selects the test clock signal from the switch input terminal, and outputs it to the output terminal 464; 438 to 440, and the signal from the first gate circuit, and the second,
a second gate circuit 313, 315, 317, 31 that supplies the test clock signal to the minute and hour digits;
9,321,323.