JPS6239861B2 - - Google Patents

Info

Publication number
JPS6239861B2
JPS6239861B2 JP56153971A JP15397181A JPS6239861B2 JP S6239861 B2 JPS6239861 B2 JP S6239861B2 JP 56153971 A JP56153971 A JP 56153971A JP 15397181 A JP15397181 A JP 15397181A JP S6239861 B2 JPS6239861 B2 JP S6239861B2
Authority
JP
Japan
Prior art keywords
output
signal
received signal
polarization
interference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56153971A
Other languages
Japanese (ja)
Other versions
JPS5856545A (en
Inventor
Junji Namiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56153971A priority Critical patent/JPS5856545A/en
Priority to US06/416,112 priority patent/US4479258A/en
Publication of JPS5856545A publication Critical patent/JPS5856545A/en
Publication of JPS6239861B2 publication Critical patent/JPS6239861B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B7/00Radio transmission systems, i.e. using radiation field
    • H04B7/002Reducing depolarization effects
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/02Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06Demodulator circuits; Receiver circuits

Description

【発明の詳細な説明】 この発明は、無線伝送の直交偏波共用にともな
い生じる交差偏波干渉補償技術に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technology for compensating for cross-polarization interference that occurs when orthogonal polarizations are shared in wireless transmission.

マイクロ波帯の無線通信は地上通信並びに衛星
通信を中心に急速に発展している。無線通信の需
要は今後移動通信サービスの拡大等の理由で更に
増大していくことが予想され、準ミリ波以上の周
波数帯開拓と共に、実用的価値の高い現用の周波
数帯のいわゆる周波数再利用の考えが高まつてい
る。すでにCCIR(国際無線通信諮問委員会)の
4〜6GHzのFM無線周波数配置に関する勧告に
は、直交偏波を使用することが明記されている。
また、衛星通信においてもINTELSAT(国際電
気通信衛星機構)は、V号系衛星で単一偏波で用
いられてきた4〜6GHz帯での直交偏波共用技術
を実用化する模様である。
Microwave band wireless communications are rapidly developing, centering on terrestrial communications and satellite communications. The demand for wireless communications is expected to further increase in the future due to the expansion of mobile communication services, etc., and along with the development of sub-millimeter wave and higher frequency bands, so-called frequency reuse of current frequency bands with high practical value is expected. Thoughts are growing. The use of orthogonal polarization is already specified in the CCIR (Consultative Committee on International Radio Communications) recommendations regarding FM radio frequency allocation in the 4 to 6 GHz range.
In addition, in satellite communications, INTELSAT (International Telecommunication Satellite Organization) is expected to commercialize orthogonal polarization sharing technology in the 4 to 6 GHz band, which has been used with single polarization on V-series satellites.

本来、自由空間は直交する2偏波に対して独立
で、両偏波を同時に伝送できる伝送線路である
が、実際の伝搬路には降雨などの媒質の異方性が
存在し、直交偏波共用方式を採用すると、交差偏
波の発生による偏波間の結合が異偏波チヤンネル
干渉を起すことになる。
Originally, free space is independent of two orthogonal polarized waves, and is a transmission line that can simultaneously transmit both polarized waves. However, in actual propagation paths, there is anisotropy in media such as rain, and orthogonal polarized waves If a shared system is adopted, coupling between polarized waves due to the generation of cross-polarized waves will cause interference between different polarization channels.

これら直交偏波共用化の達成には、アンテナや
給電装置などの偏波特性の改善と共に降雨などに
よる電波伝搬上の偏波特性の劣化を補償する交差
偏波補償回路の開発も重要な課題となつている。
In order to achieve this shared use of orthogonal polarization, it is important to improve the polarization characteristics of antennas and power supply equipment, as well as develop cross-polarization compensation circuits that compensate for deterioration of polarization characteristics during radio wave propagation due to rain, etc. This has become an issue.

交差偏波補償技術は、かかる偏波間の結合をア
ンテナ給電装置や無線機器内に補償回路を設けて
自動的な補償を行なうものである。
Cross polarization compensation technology automatically compensates for such coupling between polarized waves by providing a compensation circuit within an antenna feeder or wireless device.

従来、マイクロ波帯通信はFMを中心とするア
ナログ伝送が中心であつたが近年、マイクロ波帯
においても、デイジタル伝送が使用される様にな
り交差偏波補償方式についてもデイジタル伝送の
特徴を生かしたより効率の良い方式の提案が要請
されている。
Conventionally, microwave band communication has centered on analog transmission, mainly FM, but in recent years, digital transmission has come to be used in the microwave band as well, and cross-polarization compensation methods have also been developed to take advantage of the characteristics of digital transmission. Proposals for more efficient methods are requested.

従来、この種の回路は、相互に直交する2つの
偏波を受信し、一方(干渉側)の受信信号に補償
係数を乗じて他方(受信希望側)の受信信号から
減ずることによつて干渉成分を除去するようにし
ている。例えば、水平偏波と垂直偏波とを考え、
各々に独立なデータH、Vを乗せると、伝播中に
生じた偏波干渉αV、βHにより、水平偏波の受
信信号H0および垂直偏波の受信信号V0は、 H0=H+αV ……(1) V0=V+βH ……(2) となる。今、データHを受信したい場合を考える
と、垂直偏波の受信信号V0に補償係数Ωをを乗
じて水平受信信号H0に加えて干渉除去信号Heを
得るようにするのが一般的である。すなわち、 He=H0+ΩV0 ……(3) 従つて、 He=H+αV+Ω(V+βH)=H+(α +Ω)V+Ω・β・H≒H+(α+Ω)V
……(4) すなわち、α=−Ωとすることによつて He≒H ……(5) となり、偏波干渉が除去される。このときΩの制
御は、一般に Ω(i+1)=Ω(i)−kV0 *・(He−H^e) ……(6) となるように制御される。ここにH^eはHeの識
別値であり、He−H^eは識別誤差eであつて垂
直偏波からの干渉が含まれている。従つてeと
V0との相関を最小化する方向にΩを制御すれ
ば、α=−Ωとなり、干渉が除去されることにな
る。
Conventionally, this type of circuit receives two mutually orthogonal polarized waves, multiplies the received signal of one (the interfering side) by a compensation coefficient, and subtracts it from the received signal of the other (the desired receiving side) to eliminate the interference. We are trying to remove the ingredients. For example, considering horizontal polarization and vertical polarization,
When independent data H and V are placed on each, due to the polarization interference αV and βH that occurred during propagation, the horizontally polarized received signal H 0 and the vertically polarized received signal V 0 become H 0 = H + αV …… (1) V 0 =V+βH ...(2) Now, if we consider the case where we want to receive data H, it is common to multiply the vertically polarized received signal V 0 by a compensation coefficient Ω and add it to the horizontal received signal H 0 to obtain the interference cancellation signal He. be. That is, He=H 0 +ΩV 0 ...(3) Therefore, He=H+αV+Ω(V+βH)=H+(α+Ω)V+Ω・β・H≒H+(α+Ω)V
...(4) That is, by setting α=-Ω, He≒H ...(5) and polarization interference is removed. At this time, Ω is generally controlled so that Ω (i+1) = Ω (i) −kV 0 * ·(He−H^e) (6). Here, H^e is the discrimination value of He, and He-H^e is the discrimination error e, which includes interference from vertically polarized waves. Therefore, e and
If Ω is controlled in a direction that minimizes the correlation with V 0 , α=−Ω, and interference will be removed.

しかし、V0 *・eは複素乗算であつて、高価
なアナログ乗算器を必要とし、特に伝送レートが
高速の場合は非常に高価である。
However, V 0 * ·e is a complex multiplication and requires an expensive analog multiplier, which is very expensive especially when the transmission rate is high.

本発明の目的は、上述の従来の欠点を解決し、
複数乗算器を使用しないで、上記V0 *・eに比
例する値を得ることができる安価な偏波干渉除去
回路を提供することにある。
The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
The object of the present invention is to provide an inexpensive polarization interference cancellation circuit that can obtain a value proportional to the above V 0 * ·e without using multiple multipliers.

本発明の干渉除去回路は、相互に直交する2つ
の偏波を受信し、一方の受信信号に補償係数を乗
じて他方の受信信号に加えることにより偏波干渉
成分を除去する偏波干渉除去回路において、補償
後の受信信号とその識別値との誤差を検出する識
別誤差検出器と、該誤差検出器の出力する識別誤
差信号の実数部と虚数部との和および差を出力す
る加算器および減算器と、干渉偏波側受信信号の
実数部と虚数部の絶体値が等しいことを検出しか
つどの象限に属するかに従つて制御信号を出す干
渉側識別器と、該干渉側識別器の出力する制御信
号に対応して前記加算器と減算器の出力信号の符
号組合せを変えて出力する開閉器と、該開閉器の
出力を平滑する低域波器とを備えて、該低域
波器の出力により前記補償係数を得るようしたこ
とを特徴とする。
The interference cancellation circuit of the present invention receives two mutually orthogonal polarized waves, multiplies one received signal by a compensation coefficient, and adds it to the other received signal to remove the polarization interference component. , an identification error detector that detects an error between the compensated received signal and its identification value; an adder that outputs the sum and difference between the real part and the imaginary part of the identification error signal output from the error detector; a subtracter, an interference side discriminator that detects that the absolute values of the real part and the imaginary part of the received signal on the interference polarization side are equal and outputs a control signal according to which quadrant it belongs to; and the interference side discriminator. a switch that changes the sign combination of the output signals of the adder and the subtracter in response to a control signal output from the switch, and a low-frequency wave generator that smooths the output of the switch; The present invention is characterized in that the compensation coefficient is obtained from the output of the wave generator.

次に、本発明について、図面を参照して詳細に
説明する。
Next, the present invention will be explained in detail with reference to the drawings.

先ず、本発明の原理について説明する。今、受
信信号V0の実数部をVR、虚数部をVI、識別誤
差号eの実数部をeR、虚数部をeIとすると、 V0=VR+jVI ……(7) e=eR+jeI ……(8) であるから、 V0 *・e=(VR−jVI)(eR+jeI) =(VRR+VII)+j(VRI−VIR) である。ここで、 VR=VI>0 ……(9) の時は、 V0 *e∝(eR+eI)+(eI−eR) ……(10) となるから、上記(10)式は加算器のみで求めること
ができる。従つて、(9)式を満足する時にのみ(10)式
の値を出力させ、これによつて補償係数を制御す
ることにより干渉波成分を除去することができ
る。
First, the principle of the present invention will be explained. Now, let V R be the real part of the received signal V 0 , V I be the imaginary part, e R be the real part of the identification error signal e, and e I be the imaginary part, then V 0 = V R +jV I ...(7) e=e R +je I ...(8) Therefore, V 0 *・e=(V R −jV I )(e R +je I ) =(V R e R +V I e I )+j(V R e I − V I e R ). Here, when VR = V I > 0 ... (9), V 0 * e∝ (e R + e I ) + (e I − e R ) ... (10), so the above (10 ) can be obtained using only an adder. Therefore, the interference wave component can be removed by outputting the value of equation (10) only when equation (9) is satisfied and thereby controlling the compensation coefficient.

例えば、第1図に示すような16値振幅位相変調
(16QAM)の信号のうち、黒丸印の信号は(9)式を
満足している。
For example, among the 16-level amplitude phase modulation (16QAM) signals shown in FIG. 1, the signals marked with black circles satisfy equation (9).

第2図は、(9)式を満足するとき出力信号を出す
ようにした干渉側識別器の一例を示す回路図であ
る。すなわち、端子300,301へは、干渉側
受信信号の実数部VRおよび虚数部VIがそれぞれ
入力し、減算器31で減算し、折返し回路32で
差の絶体値を出力し、比較回路33で比較するこ
とにより|VR|≒|VI|が検出される。VR
0は比較器30で検出される。比較器30と34
の両出力はアンド回路34で論理積がとられて出
力端子302に出力される。
FIG. 2 is a circuit diagram showing an example of an interference side discriminator that outputs an output signal when formula (9) is satisfied. That is, the real part V R and the imaginary part V I of the interfering received signal are respectively input to the terminals 300 and 301, subtracted by the subtracter 31, outputted as the absolute value of the difference by the folding circuit 32, and then sent to the comparator circuit. By comparing at 33, |V R |≒|V I | is detected. V R >
0 is detected by comparator 30. Comparators 30 and 34
Both outputs are ANDed by an AND circuit 34 and output to an output terminal 302.

第3図は、上述の回路を使用した偏波干渉除去
回路の一例を示すブロツク図である。すなわち、
偏波干渉減算回路6の入力端子600に例えば水
平偏波受信信号H0を入力させ、入力端子601
には垂直偏波受信信号V0を入力させる。垂直偏
波受信信号V0は乗算器61で補償係数Ωが乗ぜ
られて加算器60において水平偏波受信信号H0
に加えられる。従つて出力端子602には、干渉
除去信号Heが出力する。すなわち(3)式が実現さ
れる。干渉除去信号Heは、識別誤差検出器1の
入力端子100に接続され、識別器10によつて
識別値H^eが出力され、減算器11によつて前記
eとの差がとられて識別誤差eが端子101か
ら出力する。識別誤差eの実数部eRと虚数部eI
は、相関器2の内蔵する加算器22によつて加算
され、減算器23によつて減算される。加算器2
2の出力は、(10)式右辺の(eR+eI)を与え、減
算器23の出力は(10)式右辺の(eR−eI)を与え
ている。これらの出力は開閉器4(スイツチ4
0,41)が閉じたときにそれぞれ積分器50お
よび51に供給され、(6)式に示した積分動作が行
なわれ、平滑化される。開閉器4は干渉側識別器
3の出力によつて閉じる開閉器であり、干渉側識
別器3は、前述の第2図に示すように構成されて
いて、(9)式を満足するときのみ出力を出す。従つ
て、開閉器4は(9)式が満足されるときだけ導通す
るから、このときの相関器2の出力は、(10)式によ
り前記V0 *eに比例する。加算器22の出力は積
分器50によつて平滑化されて補償係数Ωの実数
部ΩRとされ、減算器23の出力は、積分器51
によつて平滑化されて補償係数Ωの虚数部ΩI
される。積分器50,51で複素低域波器5を
構成している。すなわち、(6)式のΩを乗算器を用
いないで得ることができる。上記補償係数Ωは前
述の通り乗算器61によつて垂直偏波受信信号
V0に乗ぜられて水平偏波受信信号H0に加えるこ
とにより偏波干渉が打消される。補償残りは、識
別誤差信号eとなつて上述の動作により次の補償
係数を修正する。
FIG. 3 is a block diagram showing an example of a polarization interference removal circuit using the above-described circuit. That is,
For example, the horizontally polarized received signal H 0 is input to the input terminal 600 of the polarization interference subtraction circuit 6, and the input terminal 601
The vertically polarized received signal V 0 is input to . The vertically polarized received signal V 0 is multiplied by a compensation coefficient Ω in the multiplier 61, and the horizontally polarized received signal H 0 is outputted in the adder 60.
added to. Therefore, the interference cancellation signal H e is output to the output terminal 602. In other words, equation (3) is realized. The interference cancellation signal H e is connected to the input terminal 100 of the discrimination error detector 1 , the discriminator 10 outputs the discrimination value H^e, and the subtractor 11 calculates the difference from the above H e. The identification error e is output from the terminal 101. Real part e R and imaginary part e I of identification error e
are added by an adder 22 built in the correlator 2 and subtracted by a subtracter 23. Adder 2
The output of the subtracter 23 gives (e R +e I ) on the right side of equation (10), and the output of the subtracter 23 gives (e R −e I ) on the right side of equation (10). These outputs are connected to switch 4 (switch 4
0, 41) are respectively supplied to integrators 50 and 51, where the integral operation shown in equation (6) is performed and smoothed. The switch 4 is a switch that is closed by the output of the interference side discriminator 3, and the interference side discriminator 3 is configured as shown in FIG. Give output. Therefore, since the switch 4 becomes conductive only when the equation (9) is satisfied, the output of the correlator 2 at this time is proportional to the V 0 * e according to the equation (10). The output of the adder 22 is smoothed by the integrator 50 to become the real part Ω R of the compensation coefficient Ω, and the output of the subtracter 23 is smoothed by the integrator 50.
The compensation coefficient Ω is smoothed by the imaginary part Ω I of the compensation coefficient Ω. Integrators 50 and 51 constitute a complex low-pass filter 5. That is, Ω in equation (6) can be obtained without using a multiplier. The compensation coefficient Ω is calculated by the multiplier 61 as described above for the vertically polarized received signal.
Polarization interference is canceled by multiplying by V 0 and adding it to the horizontally polarized received signal H 0 . The remaining compensation becomes the identification error signal e, and the next compensation coefficient is corrected by the above-described operation.

しかし、上述では、例えば第1図に示した16値
振幅位相変調(16QAM)の信号のうち、わずか
2点しか利用していないので制御スピードが遅
い。制御スピードを上げる為にはより多くの信号
を利用する必要がある。そこで、本発明において
は|VR|=|VI|を満足する信号点群をすべて
利用することにより制御スピードの上昇を図つ
た。例えば16QAMの場合には、第4図に●、
▲、■、▼で示した8点(4組)を使用する。●
印の信号は前述(9)式を満足し、(10)式右辺によつて
V0 *・eに比例した信号が得られることは前述
した。■印の信号は、実数が負で虚数が正である
から、 V0 *e∝−(eR−eI)−j(eR+eI)……(11) となり、▼印の信号は、 V0 *∝−(eR+eI)+j(eR−eI) ……(12) ▲印の信号は V0 *e∝(eR−eI)+j(eR−eI
……(13) となる。式(10)〜(13)が成立する信号点群の検出
は例えば第5図に示すような干渉側識別器によつ
て行なうことができる。すなわち、例えば垂直偏
波受信信号V0の実数部VRを端子300に入力さ
せ、虚数部VIを端子301に入力させる。正負
比較器35,36で実数部VRと虚数部VIの符号
を判定し、その出力をアンド回路39a〜39d
に入力させる。アンド回路39aは、第1象限の
信号に対してハイレベルを出力し、アンド回路3
9b〜39dはそれぞれ第2〜第4象限の信号に
対してハイレベルを出力する。一方実数部VR
虚数部VIを折返し回路37,38に入力させ、
それらの出力を減算器31に入力させて減算す
る。減算器31の出力を折返し回路32を介して
比較器33によつて一定レベルと比較し、|VR
|≒|VI|を判定し、比較器33の出力はアン
ド回路34a〜34dの一方の入力とする。アン
ド回路34a〜34dのもう一方の入力には、そ
れぞれ前記アンド回路39a〜39dの出力が接
続されている。従つて、第4図に●印で示した信
号に対してはアンド回路34aがハイレベルを出
力し、アンド回路34b〜34dはそれぞれ■
印、▼印、▲印で示した信号に対してハイレベル
を出力する。従つて、これらの出力を制御信号と
して、識別誤差信号を組合わせることにより式(10)
〜(13)の右辺を作成することができる。
However, in the above method, only two points of the 16-value amplitude phase modulation (16QAM) signal shown in FIG. 1 are used, so the control speed is slow. In order to increase control speed, it is necessary to use more signals. Therefore, in the present invention, the control speed is increased by using all the signal points satisfying |V R |=|V I |. For example, in the case of 16QAM, in Figure 4 ●,
Use the 8 points (4 sets) indicated by ▲, ■, and ▼. ●
The signal marked satisfies Equation (9) above, and according to the right side of Equation (10),
As mentioned above, a signal proportional to V 0 * ·e can be obtained. In the signal marked ■, the real number is negative and the imaginary number is positive, so V 0 * e∝−(e R −e I )−j(e R +e I )……(11), and the signal marked ▼ is , V 0 * ∝−(e R +e I )+j(e R −e I ) ……(12) The signal marked with ▲ is V 0 * e∝(e R −e I )+j(e R −e I )
...(13) becomes. Detection of a signal point group for which equations (10) to (13) hold can be performed, for example, by an interference side discriminator as shown in FIG. That is, for example, the real part V R of the vertically polarized received signal V 0 is input to the terminal 300, and the imaginary part V I is input to the terminal 301. Signs of the real part V R and the imaginary part V I are determined by the positive/negative comparators 35 and 36, and the outputs are sent to AND circuits 39a to 39d.
input. The AND circuit 39a outputs a high level for the signal in the first quadrant, and
9b to 39d output high level signals for the second to fourth quadrants, respectively. On the other hand, the real part V R ,
Input the imaginary part V I to folding circuits 37 and 38,
These outputs are input to a subtracter 31 and subtracted. The output of the subtracter 31 is compared with a constant level by a comparator 33 via a folding circuit 32, and |V R
|≒|V I | is determined, and the output of the comparator 33 is used as one input of the AND circuits 34a to 34d. The outputs of the AND circuits 39a-39d are connected to the other inputs of the AND circuits 34a-34d, respectively. Therefore, the AND circuit 34a outputs a high level for the signal indicated by a circle in FIG. 4, and the AND circuits 34b to 34d each output
Outputs high level for the signals indicated by marks, ▼ marks, and ▲ marks. Therefore, by using these outputs as control signals and combining the identification error signals, equation (10) can be obtained.
The right-hand side of ~(13) can be created.

第6図は、本発明の一実施例を示すブロツク図
である。すなわち、水平偏波受信信号H0は端子
600に入力させ、垂直偏波受信信号V0は端子
601,603を介して干渉側識別器3″に入力
させる。干渉側識別器3″は第5図に示した構成
であり、入力信号の条件に応じた制御信号を出力
して開閉器4′の開閉を制御する。
FIG. 6 is a block diagram showing one embodiment of the present invention. That is, the horizontally polarized received signal H 0 is input to the terminal 600, and the vertically polarized received signal V 0 is inputted to the interference side discriminator 3'' via the terminals 601 and 603.The interference side discriminator 3'' It has the configuration shown in the figure, and controls the opening and closing of the switch 4' by outputting a control signal according to the conditions of the input signal.

一方、垂直偏波受信信号V0は偏波干渉除去回
路6内で端子604から入力した補償係数Ωと乗
ぜられたのち水平偏波受信信号H0に加えられ、
干渉除去信号Heが端子602から出力される。
干渉波除去信号Heは識別誤差検出器1の端子1
00に入力させ、端子101から識別誤差信号e
が出力する。識別誤差信号eの実数部eRおよび
虚数部eIはそれぞれ相関器2,2′,2″,2
内において(eR+eI)および(eR−eI)が算
出され、各相関器からはそれぞれ式(10)〜(13)の
右辺に相当する信号が出力する。開閉器4′は前
記干渉側識別器3″の出力する制御信号に対応し
て上記各相関器の出力を択一的に選択して低域
波器5の入力端子500に入力させる。低域波
器5は入力信号を平滑化して出力端子501から
補償係数Ωとして出力する。
On the other hand, the vertically polarized received signal V 0 is multiplied by the compensation coefficient Ω input from the terminal 604 in the polarization interference removal circuit 6, and then added to the horizontally polarized received signal H 0 .
The interference canceled signal He is output from the terminal 602.
The interference wave cancellation signal He is connected to terminal 1 of identification error detector 1.
00, and the identification error signal e is input from the terminal 101.
outputs. The real part e R and imaginary part e I of the identification error signal e are correlators 2, 2', 2'', and 2, respectively.
(e R +e I ) and (e R −e I ) are calculated within the equation, and each correlator outputs a signal corresponding to the right side of equations (10) to (13). The switch 4' selectively selects the output of each of the correlators in response to the control signal output from the interference side discriminator 3'' and inputs the selected output to the input terminal 500 of the low frequency filter 5. The waveform generator 5 smoothes the input signal and outputs it from an output terminal 501 as a compensation coefficient Ω.

本実施例では、第4図に示した16個の信号中8
個の信号を係数Ωの制御に利用することができる
ため、迅速な制御が可能である。すなわち、干渉
偏波の変動がはげしい場合にも応動することが可
能であり、第3図の構成による場合に比して約4
倍の制御スピードが得られる。従つて、例えば衛
星通信における宇宙空間のフアラデー・ローテー
シヨンによる偏波干渉変化にも迅速、精確に追従
することが可能である。
In this example, 8 out of 16 signals shown in FIG.
Since these signals can be used to control the coefficient Ω, rapid control is possible. In other words, it is possible to respond even when the interference polarization fluctuates significantly, and the response time is approximately 4
Double the control speed. Therefore, it is possible to quickly and precisely follow changes in polarization interference due to Faraday rotation in outer space, for example in satellite communications.

なお、上述では相関器2,2′,2″,2内に
おいてそれぞれ加算器と減算器を設けて、相関器
内で式(10)〜(13)の右辺を求めたが、例えば相関
器2の2個の出力(eR+eI)および(eR−e
I)を開閉器4′内において制御信号に応じて加算
又は減少するように構成すれば相関器2′,2″,
2は省略することができる。
In addition, in the above, adders and subtracters were provided in correlators 2, 2', 2'', and 2, respectively, and the right sides of equations (10) to (13) were found in the correlators, but for example, correlator 2 The two outputs (e R +e I ) and (e R −e
I ) If configured to add or decrease in accordance with the control signal in the switch 4', the correlators 2', 2'',
2 can be omitted.

以上のように、本発明においては、識別誤差信
号の実施例と虚数部とを加算する加算器と、減算
する減算器を設けて、干渉偏波受信信号の実数部
と虚数部の大きさが等しいとき、その属する象限
に対応して前記加算器および減算器の出力組合せ
を変化させることにより補償係数を制御するよう
に構成したから、補償係数制御に利用できる信号
点数が多くなり迅速な制御スピードを得ることが
できる。また、乗算器を使用しないで補償係数を
最適かつ自動的に変化させることができるから構
成が簡単である。
As described above, in the present invention, an adder that adds the embodiment of the identification error signal and the imaginary part, and a subtracter that subtracts are provided, so that the magnitudes of the real part and imaginary part of the interference polarization received signal are When they are equal, the compensation coefficient is controlled by changing the output combination of the adder and subtracter in accordance with the quadrant to which they belong, so the number of signal points that can be used for compensation coefficient control increases, resulting in rapid control speed. can be obtained. Furthermore, the configuration is simple because the compensation coefficient can be optimally and automatically changed without using a multiplier.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は16値振幅位相変調信号の各信号点およ
び特定の条件を満たす信号点を示す図、第2図は
上記特定の条件を検出する干渉側識別器の一例を
示す回路図、第3図は上記特定の条件時に補償係
数を変化させるようにした偏波干渉除去回路の一
例を示すブロツク図、第4図は16値振幅位相変調
信号のうち実数部と虚数部の大きさが等しい信号
点群を示す図、第5図は本発明に使用するための
上記条件を検出する干渉側識別器の一例を示す回
路図、第6図は本発明の一実施例を示すブロツク
図である。 図において、1……識別誤差検出器、2,
2′,2″,2……相関器、3,3″……干渉側
識別器、4,4′……開閉器、5……低域波
器、6……偏波干渉減算回路、10……識別器、
11……減算器、22…加算器、23……減算
器、30,33,35,36……比較器、32,
37、38……折返し回路、34,34a〜34
d,39a〜39d……アンド回路、40,41
……開閉器、50,51……積分器、60……加
算器、61……乗算器。
Fig. 1 is a diagram showing each signal point of a 16-level amplitude phase modulation signal and a signal point that satisfies a specific condition, Fig. 2 is a circuit diagram showing an example of an interference side discriminator that detects the above specific condition, and Fig. 3 The figure is a block diagram showing an example of a polarization interference removal circuit that changes the compensation coefficient under the above specific conditions. Figure 4 shows a signal in which the real part and imaginary part of a 16-value amplitude phase modulation signal are equal in size. FIG. 5 is a circuit diagram showing an example of an interference side discriminator for detecting the above conditions for use in the present invention, and FIG. 6 is a block diagram showing an embodiment of the present invention. In the figure, 1...discrimination error detector, 2,
2', 2'', 2... Correlator, 3, 3''... Interfering side discriminator, 4, 4'... Switch, 5... Low frequency device, 6... Polarization interference subtraction circuit, 10 ...discriminator,
11...Subtractor, 22...Adder, 23...Subtractor, 30, 33, 35, 36...Comparator, 32,
37, 38... Return circuit, 34, 34a to 34
d, 39a to 39d...AND circuit, 40, 41
... Switch, 50, 51 ... Integrator, 60 ... Adder, 61 ... Multiplier.

Claims (1)

【特許請求の範囲】[Claims] 1 相互に直交する2つの偏波を受信し、一方の
受信信号に補償係数を乗じて他方の受信信号に加
えることにより偏波干渉成分を除去する偏波干渉
除去回路において、補償後の受信信号とその識別
値との誤差を検出する識別誤差検出器と、該誤差
検出器の出力する識別誤差信号の実数部と虚数部
との和および差を出力する加算器および減算器
と、干渉偏波側受信信号の実数部と虚数部の絶体
値が等しいことを検出しかつどの象限に属するか
に従つて制御信号を出す干渉側識別器と、該干渉
側識別器の出力する制御信号に対応して前記加算
器と減算器の出力信号の符号組合せを変えて出力
する開閉器と、該開閉器の出力を平滑する低域
波器とを備えて、該低域波器の出力により前記
補償係数を得るようにしたことを特徴とする偏波
干渉除去回路。
1 In a polarization interference removal circuit that receives two mutually orthogonal polarized waves and removes the polarization interference component by multiplying one received signal by a compensation coefficient and adding it to the other received signal, the received signal after compensation is an identification error detector that detects an error between the identification error signal and its identification value; an adder and a subtractor that output the sum and difference between the real part and the imaginary part of the identification error signal output by the error detector; and an interference polarization detector. An interfering side discriminator that detects that the absolute values of the real part and imaginary part of the side received signal are equal and outputs a control signal according to which quadrant it belongs to, and corresponds to the control signal output from the interfering side discriminator. a switch that changes the sign combination of the output signals of the adder and the subtracter and outputs the output signals, and a low-frequency wave generator that smoothes the output of the switch, and the compensation is performed using the output of the low-frequency wave generator. A polarization interference removal circuit characterized in that a coefficient is obtained.
JP56153971A 1981-09-30 1981-09-30 Eliminating circuit for polarized wave interference Granted JPS5856545A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP56153971A JPS5856545A (en) 1981-09-30 1981-09-30 Eliminating circuit for polarized wave interference
US06/416,112 US4479258A (en) 1981-09-30 1982-09-09 Cross-polarization crosstalk canceller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56153971A JPS5856545A (en) 1981-09-30 1981-09-30 Eliminating circuit for polarized wave interference

Publications (2)

Publication Number Publication Date
JPS5856545A JPS5856545A (en) 1983-04-04
JPS6239861B2 true JPS6239861B2 (en) 1987-08-25

Family

ID=15574072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56153971A Granted JPS5856545A (en) 1981-09-30 1981-09-30 Eliminating circuit for polarized wave interference

Country Status (1)

Country Link
JP (1) JPS5856545A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004057783A1 (en) * 2002-12-19 2004-07-08 Fujitsu Limited Ofdm transmission/reception apparatus
US7551678B2 (en) 2002-12-19 2009-06-23 Fujitsu Limited OFDM transceiver apparatus

Also Published As

Publication number Publication date
JPS5856545A (en) 1983-04-04

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