JPS6239337U - - Google Patents
Info
- Publication number
- JPS6239337U JPS6239337U JP12999385U JP12999385U JPS6239337U JP S6239337 U JPS6239337 U JP S6239337U JP 12999385 U JP12999385 U JP 12999385U JP 12999385 U JP12999385 U JP 12999385U JP S6239337 U JPS6239337 U JP S6239337U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- gate
- base
- type
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Logic Circuits (AREA)
Description
第１図はこの考案の実施例を示す回路図、第２
図はＮＡＮＤゲートの従来例を示す回路図である
。
符号説明、Ｑ１〜Ｑ６……トランジスタ、Ｄ１
〜Ｄ４……ダイオード、Ｒ１〜Ｒ６……抵抗、Ａ
，Ｂ……ゲート入力端子、Ｖ１……電源電圧、Ｖ
０……ゲート出力端子。
Figure 1 is a circuit diagram showing an embodiment of this invention, Figure 2 is a circuit diagram showing an embodiment of this invention.
The figure is a circuit diagram showing a conventional example of a NAND gate. Explanation of symbols, Q 1 to Q 6 ...transistor, D 1
~ D4 ...Diode, R1 ~ R6 ...Resistance, A
, B... Gate input terminal, V 1 ... Power supply voltage, V
0 ...Gate output terminal.
Claims (1)
トランジスタからなるトーテムポール回路を出力
回路としてもつＴＴＬ形ＮＡＮＤゲートにおいて
、エミツタは接地される一方、コレクタは前記シ
ンク用トランジスタのベースに、またベースは抵
抗およびダイオードを介して前記ソース用トラン
ジスタのベースにそれぞれ接続される他のトラン
ジスタを設けてなることを特徴とするＴＴＬ形Ｎ
ＡＮＤゲート。 (2) 実用新案登録請求の範囲第１項に記載のＴ
ＴＬ形ＮＡＮＤゲートにおいて、前記各トランジ
スタおよびダイオードをそれぞれシヨツトキーバ
リア型のものとすることを特徴とするＴＴＬ形Ｎ
ＡＮＤゲート。[Claims for Utility Model Registration] (1) In a TTL type NAND gate having a totem pole circuit consisting of a current source transistor and a sink transistor as an output circuit, the emitter is grounded, while the collector is connected to the base of the sink transistor. In addition, the TTL type N transistor is further provided with another transistor whose base is connected to the base of the source transistor through a resistor and a diode, respectively.
AND gate. (2) T stated in paragraph 1 of claims for utility model registration
In the TL type NAND gate, each of the transistors and diodes are of a shot key barrier type.
AND gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12999385U JPS6239337U (en) | 1985-08-28 | 1985-08-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12999385U JPS6239337U (en) | 1985-08-28 | 1985-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6239337U true JPS6239337U (en) | 1987-03-09 |
Family
ID=31027071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12999385U Pending JPS6239337U (en) | 1985-08-28 | 1985-08-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6239337U (en) |
-
1985
- 1985-08-28 JP JP12999385U patent/JPS6239337U/ja active Pending
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