JPS6238914B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a registration adjustment error detection device for a solid-state imaging device comprising at least two solid-state imaging devices each having a plurality of picture elements arranged in a matrix.

For example, in an imaging device equipped with multiple image sensors, such as a color television camera configured to capture a subject image with multiple image sensors to obtain three primary color signals, the image signals obtained from each image sensor are mixed. Since the image pickup signal represents one image, unless the spatial arrangement positional relationship of each image pickup element is maintained accurately, it is not possible to output an image pickup signal of good quality. Therefore, conventionally,
By adjusting the registration (overlay),
The spatial position of each image sensor is adjusted mechanically and electrically so that the subject images captured by each image sensor completely match.

By the way, in a solid-state imaging device equipped with a solid-state imaging device such as a charge coupled device that performs photoelectric conversion by direct optical sampling of a subject image, it is common to experience the problem that the above-mentioned registration adjustment is not performed correctly. , Sideband components are generated by the above sampling, and when these sideband components are superimposed on the baseband component, they cause aliasing distortion.

The present invention provides a novel registration error detection device that utilizes sideband components resulting from the above-mentioned sampling to detect registration errors in a solid-state imaging device. In a solid-state imaging device comprising at least two arrayed solid-state imaging devices, one image is captured for each pixel arranged in a positional relationship that is shifted by one pixel between one image sensor and the other image sensor. A registration error detection device for a solid-state imaging device is provided, which detects registration errors by detecting sideband components contained in a signal obtained by mixing each imaging signal obtained by performing random sampling. This is a summary.

Hereinafter, the present invention will be described in detail using drawings showing one embodiment.

First, a solid-state imaging device and a solid-state imaging element to which the present invention is applied will be explained.

FIG. 1 is a schematic plan view showing the general structure of a frame transfer type CCD image sensor 1 used as a solid-state image sensor, and each frame transfer type CCD image sensor 1 corresponds to one pixel. A light-receiving area 3 is formed by arranging the light-receiving parts 2 in a matrix, and each imaging charge obtained in the light-receiving area 3 is sequentially transferred in the vertical direction and is arranged in a matrix in order to temporarily store the imaging charges. An accumulation region 5 consisting of an array of accumulation sections 4 and a horizontal transfer register section 6 which transfers imaging charges from this accumulation region 5 in the horizontal direction for each horizontal line and outputs continuous imaging signals from an output terminal 7. , is constructed using CCD. Note that 8 in FIG. 1 is a first clock input terminal to which a horizontal transfer clock signal φ _H for driving the horizontal transfer register section 6 is supplied, and 9 is a first clock input terminal to which a horizontal transfer clock signal φ H for driving the horizontal transfer register section 6 is supplied. This is a second clock signal input terminal to which each vertical transfer clock signal _φV for transferring the obtained imaging charge to the storage section 4 is supplied. In reality, the horizontal transfer clock signal φ _H and the vertical transfer clock signal φ _V each consist of a two-phase (or three-phase) clock pulse train.

FIG. 2 is a schematic plan view showing the general structure of an interline CCD image sensor 11 used as a solid-state image sensor, and each interline CCD image sensor 11 corresponds to a picture element. A plurality of light receiving sections 12 arranged in a matrix
, each vertical transfer register section 13 provided between the rows of these light receiving sections 12, and each vertical transfer register section 1
Horizontal transfer register section 1 provided at each terminal side of 3.
4 is constructed using a CCD, and the imaging charge corresponding to the amount of light received by each of the light receiving sections 12 is transferred to the horizontal transfer register section 14 through the vertical transfer register section 13 corresponding to each vertical line, This horizontal transfer register section 14 transfers the image pickup charges for each horizontal line in the horizontal direction, and outputs a continuous image signal from the output terminal 15. In FIG. 2, 16 is a first clock input terminal to which the horizontal transfer clock signal φ _H is supplied, and 17 is a second clock input terminal to which each vertical transfer clock signal φ _V is supplied.

Each of the above-mentioned CCD image sensors 1 and 11 uses the horizontal transfer clock signal φ _H supplied to each first clock input terminal 8 and 16 as a readout pulse, and sequentially reads out each pixel of the subject image to perform continuous imaging. Output is being output. Further, the vertical transfer clock signal φ _V supplied to the second clock input terminals 9 and 17 is inverted in phase so as to correspond to each vertical scanning period of the television signal. The above-mentioned interlacing is performed by skipping every horizontal line in the vertical direction.

Furthermore, FIG. 3 shows solid-state image sensors 21G, 21
1 is a schematic plan view showing the basic structure of a color solid-state imaging device 20 including three lenses R and 21B;
2. A three-color separation optical system formed by combining prisms 23A and 24, and three solid-state image sensors 21G, 21R, and 21B provided in each optical path of the primary color light separated by the three-color separation optical system. Each of the solid-state image sensors 21A, 21
A color imaging signal of good quality can be obtained in a state where the registration is adjusted so that the respective subject images captured by B and 21C completely match each other. In order to perform the above registration adjustment, the optical path axis of the primary color light is aligned vertically between the prism 23A and the solid-state image sensor 21R for capturing red images, and between the prism 23B and the solid-state image sensor 21B for capturing blue images. and each optical path axis adjustment plate 24A, 24B, 25 such as a thin plate glass that changes in the horizontal direction.
A and 25B are respectively provided. Registration adjustment in the solid-state imaging device 20 is performed by finely adjusting the arrangement angles of the optical path axis adjusting plates 24A, 24B, 25A, 25B, etc., so that each solid-state imaging device 21G, 21R, 21B can perfectly match the subject. What is necessary is to take an image.

Next, by applying the present invention, the above-mentioned solid-state imaging device 2
Each solid-state image sensor 21G, 21R, 21 at 0
An example in which the horizontal registration adjustment of B is performed will be specifically described.

Figure 4 shows each solid-state image sensor 21G, 21R, 21
3 is a block diagram showing the configuration of a control system for controlling the transfer operation in B and a detection system for detecting registration adjustment errors. FIG. In this embodiment, each solid-state image sensor 21G, 21R, 2
1B is similar to the transfer operation of image pickup charges in a general CCD image sensor, and is obtained for each horizontal line by sequentially sampling each pixel in a matrix for the three primary colors of the subject: red, blue, and green. The transfer clock generator 30 outputs each primary color imaging signal in which each imaging charge of
The transfer operation is controlled by a horizontal transfer clock signal _φH and a vertical transfer clock signal _φV from.

The green primary color signal (G signal) obtained from the first solid-state image sensor 21G is supplied to the signal mixer 33 via a first sampling hold circuit 31A and a first process processing circuit 32A connected in series. Ru. Further, the red primary color imaging signal (R signal) and the blue primary color imaging signal (B signal) obtained from the second and third solid-state imaging devices 21R and 21B are similarly connected to the second and third solid-state imaging devices connected in series. The signal is supplied to the signal mixer 33 via sampling and holding circuits 31B and 31C and second and third process processing circuits 32B and 32C.

The first to third sampling and hold circuits 31A, 31B, and 31C receive a sampling command signal supplied via a switch 34 that is switched between the registration adjustment operation and the normal imaging operation in this embodiment. The operation is controlled by. The switch 34 has a movable terminal 34a connected to the transfer clock generator 30, and transmits a sampling command signal having a frequency equal to the horizontal transfer clock signal to the first fixed terminal 3.
4A to the 1/2 frequency divider circuit 35, or
The sampling command signal is sent to the second fixed terminal 34.
B to each sampling hold circuit 31A, 31
It is supplied to one of the sampling input terminals of B and 31C. The 1/2 frequency divider circuit 35 divides the frequency of the sampling command signal by 1/2 and supplies it to the other sampling input terminal of the first sampling hold circuit 31A, and also outputs the 1/2 frequency divided sampling command signal. The signal is supplied via a 180° phase shift circuit 36 to the other sampling input terminal of the second and third sampling and holding circuits 31B and 31C.

In the setting state in which the movable terminal 34a of the switch 34 and the second fixed terminal 34B are electrically connected, each sampling hold circuit 31A, 3
1B and 31C perform a sampling and hold operation at a sampling frequency equal to the horizontal transfer clock signal _φH , so that each solid-state image sensor 21G and 21
A green primary color imaging signal (G signal) and a red primary color imaging signal (R signal) obtained by successively outputting each imaging charge from each pixel of R and 21B.
and blue primary color signal (B signal) to the signal mixer 3.
3, and a normal imaging operation such as outputting a color imaging signal of the object from the output terminal 39A can be performed.

Further, in a setting state in which the movable terminal 34a of the switch 34 and the first fixed terminal 34A are electrically connected, horizontal registration adjustment can be performed by the following operation.

That is, if the sampling frequency equal to the horizontal transfer lock signal φ _H is _c , then in each of the solid-state image sensors 21G, 21R, and 21B, sampling is performed for all pixels.
Each sampling hold circuit 31A, 31B, 3
At 1C, the frequency is 1/ _2c , and the second and third
The sampling hold circuits 31B and 31C of
Since the sampling and holding operation is performed with a phase shift of 180°, each pixel is sampled every 1 pixel 21'g in the horizontal direction from the first solid-state image sensor 21G, as shown by diagonal lines in FIG. A green primary color imaging signal (G signal) based on the imaging charge obtained by the imaging charge 21g is supplied to the signal mixer 33, whereas a green primary color imaging signal (G signal) is supplied to the signal mixer 33 from the second and third solid-state imaging devices 21R and 21B. Each picture element 21r', 2 at a position corresponding to each picture element 21g thinned out in 21G
A red primary color imaging signal (R signal) and a blue primary color imaging signal (B signal) resulting from each imaging charge obtained at 1b' are supplied to the signal mixer 33. Therefore, _c /
Using a registration adjustment test chart with an achromatic vertical stripe pattern that gives a baseband component with a frequency _s higher than 4 and lower than _c /2,
When this test chart is imaged, the image signal obtained through the signal mixer 33 contains a sideband component with a frequency _f of _f = 1/2 _c - _s , as shown in the frequency distribution in Fig. 6. is included. To explain Fig. 6 in more detail, it is equivalent to sampling and holding the baseband component (input frequency component) of frequency _s with a frequency of 1/2 _c , and the upper and lower sidebands of frequency 1/2 _c ± _s . produces components. And here, among these sideband components, the lower sideband component _f ( _f
= 1/2 _c − _s ). Furthermore, since each pixel of the solid-state image sensor 2 1G and the solid-state image sensors 21R and 21R is sampled with a phase shift of 180 degrees from each other, the lower sideband component can be seen in the drawing.
_f ( _f = 1/2 _c - _s ) is the relationship between the positive axis generated from the solid-state image sensor 21G and the solid-state image sensors 21R and 21B.
is expressed by the negative axis generated from both elements. The sideband components are each of the solid-state image sensors 21G and 2.
If the signal level of each primary color imaging signal obtained by 1R and 21B is set in advance so that L _G = L _R + L _B , the second and Each picture element 21 of the third solid-state image sensor 21R, 21B
Since r' and 21b' are horizontally shifted by 1/2 of the pixel pitch τ, their phases are in opposite directions as mentioned above, and their magnitudes are equal, so they cancel each other out completely. can do. Furthermore, if the solid-state image pickup devices 10G, 10R, and 10B are arranged out of position and the phase relationship between the positive and negative sideband waves is not maintained correctly, aliasing distortion will appear. Therefore, by extracting the sideband components using a bandpass filter 37 having a center frequency equal to _f and detecting the signal level of the sideband components using a detection circuit 38, each of the solid-state image sensors 21G, 21R, and 21B is It is possible to detect a registration adjustment error indicating whether or not the positional relationship in the horizontal direction is correct. Therefore, the detection circuit 3 obtained at the output terminal 39B
By observing the signal level of the detection output signal from 8, horizontal registration adjustment can be easily performed.

In addition, the above-described solid-state imaging device 2 can also be used by applying the present invention.
Each solid-state image sensor 21G, 21R, 21 at 0
An example of vertical registration adjustment of B will be described in detail.

FIG. 7 is a block diagram showing the configuration of a control system for controlling the transfer operation of each of the solid-state image sensors 21G, 21R, and 21B and a detection system for detecting registration errors in this embodiment. In this embodiment, each solid-state image sensor 21G,
21R and 21B are interleaved by sampling with interlaced scanning for each horizontal line for each pixel in a matrix corresponding to the subject image, similar to the transfer operation of image charges in a general CCD image sensor. The horizontal transfer clock signal φ _H and the vertical transfer clock signal φ _V from the transfer clock generator 30 are used to output the three primary color imaging signals.
₁ , φ _V2 controls the transfer operation.
That is, the transfer clock generator 30 generates the pixels 21go, 21ro, 21ro, 21go, 21ro, 21go, 21ro, etc. of each of the solid-state image sensors 21G, 21R, 21B in each odd-numbered column, which are indicated by solid diagonal lines in FIG.
21bo is sampled, and in the even field, the positions are reversed every vertical scanning period so that each of the picture elements 21ge, 21re, and 21be in each even column, which are indicated by diagonal dashed lines in FIG. 8, is sampled. At the same time, the first and second
It outputs vertical transfer clock signals _φV1 and _φV2 .

The first solid-state image sensor 21G includes the first solid-state image sensor 21G.
and second vertical transfer clock signals φ _V1 and φ _V2 are directly supplied to each clock input terminal. Further, the second and third solid-state image sensors 21R,
21B, the first and second vertical transfer clock signals φ _V1 and φ _V2 are applied via the gate circuit 40.
Each is supplied to a clock input terminal. The gate circuit 40 has first to fourth gates whose gates are controlled to open and close depending on the setting state of the switch 41.
Each vertical transfer clock signal φ _V1 , selectively supplied via NAND gates 42, 43, 44, 45
Fifth and sixth NAND gates 46 and 4 supplying _φV2 from each output terminal to each clock input terminal of the second and third solid-state image sensors 21R and 21B.
7, the second and third solid-state image sensing devices 21 are arranged according to the setting state of the switch 41
The supply states of the vertical transfer clock signals φ _{V1 and φ V2 supplied} to one clock input terminal and the other clock input terminal of R and 21B are inverted.
That is, in this embodiment, the first to third solid-state image sensors 21 are
One vertical transfer clock signal _φV1 is supplied to one of the clock input terminals of G, 21R, and 21B, and the other vertical transfer clock signal _φV2 is supplied to each of the other clock input terminals to perform interlacing using normal interlaced scanning. Then, in the registration adjustment state, one vertical transfer clock signal _φV1 supplied to one of the first solid-state image sensors 21G is applied to the other clock input terminal of the second and third solid-state image sensors 21R and 21B. and supplies the other vertical transfer clock signal _φV2 to the first solid-state image sensor 21.
G, and one of the clock input terminals of the second and third solid-state image sensors 21R and 21B.
G and the second and third solid-state image sensors 21R, 21
Interlacing with B is done in reverse. the first to third solid-state image sensors 21G in which mutually reverse interlacing is performed;
21R and 21B are, for example, the first solid-state image sensor 21G, as shown by solid diagonal lines in FIG.
When each picture element 21go in an odd-numbered column is sampled, the second and third solid-state image sensors 21
Each picture element 21re, 21 in each even-numbered column of R, 21B
be sampling will be done. Therefore, the three primary color signals from the solid-state image sensors 21G, 21R, and 21B are sent to the process processing circuits 32A and 3, respectively.
2B, 32C to the signal mixer 33,
The imaging signal obtained from this signal mixer 33 includes:
As in the above embodiment, sideband components are included in the baseband component in the vertical direction of the subject image. By extracting the sideband components using the bandpass filter 37 and detecting them using the detection circuit 38, it is possible to detect registration adjustment errors in the vertical direction. In this case, the position of each picture element indicated by the solid line in FIG. /2 picture element pitch τ
The above-mentioned sideband components can be canceled out in a state where they are deviated by a certain amount. Therefore, registration adjustment in the vertical direction can be performed by an extremely simple operation of simply adjusting the registration so as to minimize the signal level of the detection output signal from the detection circuit 38 obtained at the output terminal 39B. .

Note that by combining the above-described embodiments, it is also possible to simultaneously detect registration adjustment errors in the horizontal and vertical directions. In this case, as shown with diagonal lines in FIG. 10, each image pickup signal is received from each pixel 21H on one horizontal line and each pixel 21V on one vertical line that intersect at the center of the solid-state image sensor 21. To detect the horizontal registration adjustment error, each pixel 2 on one horizontal line is extracted.
The imaging signal from 1H is used, and the imaging signal from each pixel 21V on one vertical line is used to detect the registration adjustment error in the vertical direction. If the registration adjustment is performed using the output information of each central portion of the image pickup device, adjustment errors due to chromatic aberration in the optical system of the imaging device can be reduced, and more accurate registration adjustment can be performed. Also,
In each of the embodiments described above, the present invention is applied to a solid-state color imaging device equipped with three-chip solid-state imaging devices, but the present invention may also be applied to a solid-state color imaging device equipped with two-chip solid-state imaging devices. .

As described above, according to the present invention, in a solid-state imaging device comprising at least two solid-state imaging devices each having a plurality of picture elements arranged in a matrix, each of one solid-state imaging device and the other solid-state imaging device A sampling means for sampling picture elements at positions shifted by one picture element from each other and every other picture element, a signal mixing means for mixing each imaging signal obtained by the sampling, and a mixed output signal from the mixing means. and detecting means for detecting a sideband component included in the solid-state image sensor, and detects a registration adjustment error of the solid-state image sensor from the sideband component. Registration adjustment errors in the horizontal or vertical direction in the solid-state imaging device can be detected accurately with high sensitivity, and registration adjustment operations can be simplified.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing the general structure of a frame transformer type CCD image sensor as an example of a solid-state image sensor included in a solid-state image sensor to which the present invention is applied. FIG. 2 is a schematic plan view showing the general structure of an interline CCD image sensor as a solid-state image sensor. FIG. 3 is a schematic plan view showing the basic structure of a solid-state imaging device to which the present invention is applied. FIG. 4 is a block diagram showing an embodiment of the present invention in which registration adjustment is performed in the horizontal direction. FIG. 5 is a plan view showing the sampling state of each group image sensor in the above embodiment. FIG. 6 is a frequency distribution diagram of the imaging signal in the above embodiment. FIG. 7 is a block diagram showing the structure of an embodiment in which the present invention is applied to perform registration adjustment in the vertical direction. FIG. 8 is a plan view showing the sampling state of each solid-state image sensor when performing a normal imaging operation in this embodiment. FIG. 9 is a plan view showing the sampling state of each solid-state image sensor when registration adjustment is similarly performed.
FIG. 10 is a plan view showing a sampling pattern of a solid-state image sensor that is optimal for detecting registration adjustment errors in the horizontal and vertical directions. 1, 11, 21, 21G, 21R, 21B...
Solid-state imaging device, 20... Solid-state imaging device, 30...
Transfer clock generator, 31A, 31B, 31C...
...Sampling hold circuit, 33... Signal mixing circuit, 34, 41... Operation mode changeover switch,
36... Phase shift circuit, 37... Band pass filter, 38... Detection circuit, 40... Gate circuit.

Claims (1)

[Scope of Claims] 1. In a solid-state imaging device comprising at least two solid-state imaging devices each having a plurality of picture elements arranged vertically and horizontally, each pixel of one solid-state imaging device and the other solid-state imaging device , a sampling means that performs sampling every other picture element at a position shifted by one picture element from each other, a signal mixing means that mixes each imaging signal obtained by the sampling, and a signal contained in the mixed output signal from this mixing means. What is claimed is: 1. A registration adjustment error detection device for a solid-state imaging device, comprising: detection means for detecting a sideband component of the solid-state imaging device; 2. A frequency dividing circuit that divides the signal frequency for sampling the output of each solid-state image sensor into 1/2, a phase shift circuit that shifts the phase of the frequency-divided output signal from this frequency dividing circuit by 180°, and the above-mentioned frequency-divided output. One sampling and holding circuit operates using a signal as a sampling command signal, and the other sampling and holding circuit operates using a frequency-divided output signal phase-shifted by 180° by the phase shift circuit as a sampling command signal, and each solid-state image sensor A patent claim characterized in that each image signal obtained by sampling each pixel of each of the pixels is supplied to a signal mixing circuit via each of the sampling and hold circuits, and a horizontal registration adjustment error is detected. range 1
A registration adjustment error detection device in a solid-state imaging device according to 2. 3. In a solid-state imaging device comprising a sampling means configured to output each image signal interlaced by sampling with interlaced scanning for each pixel of each solid-state imaging device, interlace in one solid-state imaging device and interlace in the other Registration adjustment error in a solid-state imaging device according to claim 1, characterized in that means is provided for mutually inverting interlace in the solid-state imaging device, and registration adjustment error in the vertical direction is detected. Detection device.