JPS6238597A - Sample holding circuit - Google Patents

Abstract

PURPOSE:To reduce the generation of an error current due to an absorption current by providing an auxiliary circuit specifying the error of a signal current voltage converting circuit composed of a sampling output circuit outputting an input when a switch circuit is turned off. CONSTITUTION:In terms of the sample holding circuit, a transistor with a current including a signal current component, which is superimposed with a noise current and whose generating point is known, connected to a collector, a capacitor connected to a space across the base and emitter of a transistor, a differential amplifier whose input terminals are connected to the collector of the transistor and a reference voltage, respectively, a switching circuit connecting the output of the differential amplifier to the base of the transistor and each circuit are connected to the collector of the transistor. An error DELTAI shown by the equation of the signal current voltage converting circuit composed of the sampling output circuit outputting an input when the switching circuit is turned on after a power source is entered is minimized by approximating the error to zero.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a sampling and holding circuit that samples and holds a signal current component present in a noise current that fluctuates relatively slowly.

(Prior Art) A circuit as shown in FIG. 7N) can be considered as a sampling and holding circuit that samples and holds a signal current component present in a noise current that fluctuates relatively slowly.

FIG. 7(n) is a waveform diagram for explaining the operation of the circuit.

As shown in (A), the circuit starts operating from the time it is connected to the operating power supply Vcc.

An input current (B) containing a signal current component is connected to input terminal 5.

The input terminal is connected to the collector of the transistor 4, the inverting input terminal of the differential amplifier 1, and the input terminal of the signal current-voltage conversion circuit 7.

A reference voltage source 10 is connected to a non-inverting input terminal of the differential amplifier S1.

The output terminal of the differential amplifier 1 is connected to the drain of a MOS transistor 2 whose gate is connected to an S/H (sampling hold) control signal.

The source of MOS transistor 2 is connected to capacitor 3 and the base of transistor 4.

When the MOS transistor 2 is turned on by the sampling hold control signal, a negative feedback loop of the signal current line 9 - differential amplifier 1 - MoSI - range meta 2 - transistor 4 - signal current line 9 is formed.

Assume that a current that does not include a signal current component is being applied to the input terminal.

In this state, feedback is applied so that the collector voltage of the transistor 4 becomes the same voltage as the reference voltage source voltage (Vref) of the differential amplifier 1.

Then, the capacitor 3 accumulates a charge that provides the base potential of the transistor 4 corresponding to this state, thereby forming an equilibrium state of the system.

In this state, when MOS transistor 2 is turned off by the sampling hold control signal (C), transistor 4
continues to flow the collector current that was flowing in the balanced state unless the current level that does not include the signal current component changes.

After that, when the signal current component enters, the level of the current including the signal current increases, but since transistor 4 cannot flow a current higher than the collector current determined by the previously fixed base potential, the signal current component The signal current is input to the signal current voltage conversion circuit 7 via the signal current line 9, and a voltage corresponding to the signal current component is outputted to the output terminal 8.

(Problems to be Solved by the Invention) In the sampling and hold circuit described above, there is a problem in that the fHa charge accumulated in the capacitor is gradually discharged through the transistor 4, and the base potential changes.

In addition, the current absorbed by the capacitor due to the signal current to be handled must also be taken into account.

In the circuit shown in FIG. 7, it is assumed that a potential corresponding to VBH is applied to the capacitor 3 before the MO3) run lister 2 is turned off.

At this time, the absorption current Is flowing through the holding capacitor is given by the following equation.

l5=At (11A, n: constant determined by the capacitor t: time after voltage is applied to the capacitor (charging time) Charging time t is shown in FIG. 8(C).

This absorbed current is supplied from the differential amplifier 1, but M
OS) After the run lister is turned off, the charge in the capacitor 3 decreases due to the absorption current determined by the charging period.

This charge is △Q= f” I s d t # I 5h-Th
=・(21 where Th: hold period Ish: average value of Is during Th) Due to this decrease in charge, the base voltage V of the transistor 4
BE decreases to VBE', so a part of the collector current is input to the signal current voltage conversion circuit 7 as a signal current,
It becomes an error component.

This error component is given by the following formula.

VBB= (kT/q) in (Io/
l5at) - (31q: Electron charge: Boltzmann constant T: Absolute temperature l5at: Reverse leakage current △V= (VBE-VBE') = I5h-Th
/C-(4) VBE': Base voltage after a drop of △V due to absorption current When the base potential drop △■ with respect to the collector current ■o of the transistor 4, the error △I flowing into the signal line is (5
) becomes the formula.

ΔI = T o C1-exp (-ΔV /'h
) ) ・+5l-Io (1-exp (-l5
h-Th/Ch))h Ni blank constant Io: Collector current C: Capacity of memory capacitor Ish: Average value of absorbed current during sampling hold time Th: Sampling hold time This is not a problem if the current component is close to the signal component, but it becomes a problem if the current component approaches the signal component.

For example, the capacitance is 0.47 μF (generally a tantalum capacitor), the hold time is 0.5 ms, and the bias current is I. =4 μA and the absorption current is 20 pA, the error current ΔI is 3.23 nA.

Therefore, when the signal current reaches this level, it becomes a big problem.

An object of the present invention is to provide a sampling and holding circuit that can reduce the occurrence of error current due to the above-mentioned absorption current.

(Means for Solving the Problem) In order to achieve the above object, a sampling and holding circuit according to the present invention includes a signal current component whose generation time is known and which is superimposed on a relatively slowly fluctuating noise current. a transistor with a current connected to its collector;
a capacitor connected between the base and emitter of the transistor; a differential amplifier having one input terminal connected to the collector of the transistor and the other input terminal connected to a reference voltage; A signal current voltage consisting of a switching circuit connected to the base, and a sampling output circuit, each of which is connected to the collector of the transistor, and which outputs the input when the switching circuit is turned off after the power is turned on. Error of conversion circuit Δ■ [ΔI = exp (-1
It is configured to reduce the error by making sh-Th/Ch) as close to 0 as possible.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings and the like.

FIG. 1(r) is a circuit diagram showing a first embodiment of the sampling and hold circuit according to the present invention, and FIG. 1(■) is a waveform diagram for explaining the operation.

This embodiment is configured to reduce Δ■ by increasing Ish in the equation representing ΔI by lengthening the charging period.

Before connecting the power supply Vcc to the circuit, a constant current 12 is supplied from the power supply Vccl14, and a charging current is passed through the transistor 4 until the next power supply 15's Vcc2 changes to L-H and the gate of PMO3II becomes H. By the way, V CCI
The charging period is lengthened by the difference in the application time of the voltage of 4 V cc2.

FIG. 2 shows a second sample-and-hold circuit according to the present invention.
It is a circuit diagram showing an example of.

In this embodiment, as in the previous embodiment, Ish in the equation representing Δ■ is made smaller by lengthening the charging period.
This structure is designed to reduce I.

Before connecting the power supply Vcc to the circuit, supply a constant current to the capacitor via the diode from the power supply Vcc414,
By changing the V CC2 of the next power supply 15 from L to H, the NPN) run lister is made conductive and the charging time is effectively lengthened during that period.

FIG. 3 is a circuit diagram showing a third embodiment of the sampling and holding circuit according to the present invention.

This is a conventional circuit system with two new precharge inputs.

The precharge circuit includes a transistor 16 and a current source 12.
．． It is composed of a diode 18, and is configured so that two precharge inputs 20 and 21 can be inputted by a NOR circuit 19.

One precharge circuit is used for normal operation, and the other is used for control to reduce absorbed current.

One precharge is used for the first operation, the absorbed current is reduced by precharging for a long period of time, and the other is used for normal precharging.

FIG. 4 shows the fourth sample and hold circuit according to the present invention.
It is a circuit diagram showing an example of.

In this example, by reducing I sh/C,
This is to reduce ΔI.

The capacitor 3 is connected to the base of the l-run lister 4 via a NULL amplifier 22 shown in the figure.

With such a configuration, it is possible to reduce the capacitance of the capacitor 3.

As the capacitor 3, a small capacitance film capacitor can be used instead of a tantalum capacitor.

Film capacitors and mica capacitors have a smaller Ish/C than tantalum capacitors, so the drop in base potential can be reduced.

FIG. 5 shows the fifth sample and hold circuit according to the present invention.
It is a circuit diagram showing an example of.

Capacitor 3 is connected to the base of transistor 4 via a PNP run resistor 23.

PNP) The base of the run lister 23 is NPN for precharging.) The base of the run lister 24 is the buffer circuit 25.
connected via.

The precharge human power 28 is ANDed via the inverter 26.
connected to the circuit 27, and the output of the AND circuit 27 is a MOS
Connected to the gate of the l-run lister 2.

A precharge circuit 28 applies a voltage of Vcc-Vst to the memory capacitor, so that the absorbed current becomes small in a short time.

6 is a signal used to turn on the AND circuit 27.

When the precharge input 28 is H, the PNP l-run lister 23 is turned off, and the MOS transistor 2 is also turned off. Therefore, NPN) from the run lister 24 to Vcc
-Vst (24) is applied to the capacitor 3, and then when the precharge input 28 becomes L, the PNP) run lister 23 is turned on and the conventional operation resumes.

In operation, after precharging at terminal 28, input 6 is controlled to turn gate 2 on and off for normal operation.

FIG. 6 shows the sixth sample and hold circuit according to the present invention.
It is a circuit diagram showing an example of.

In this embodiment, by increasing the steady voltage level of the signal current line 9, Th is shortened and errors are reduced.

The reference voltage Vref' of the differential amplifier 1 is determined by the dividing resistor 30 and the NULL amplifier 31.

The NULL amplifier 32 is a circuit that provides a constant voltage Vref'' to the signal current voltage conversion circuit 7.

The transistor 33 of the signal current voltage conversion circuit 7 is a bias current extraction transistor.

The circuit 34 consisting of a plurality of transistors is a signal current/voltage conversion circuit that logarithmically converts the signal current.

When the steady voltage level of the signal current line 9 is increased in this circuit, the operation of the sampling circuit system becomes faster, and therefore the hold period Th can be shortened.

However, setting the steady voltage of the signal current line 9 to a large value allows a current that can be considered to be a certain noise, so that current is reduced to the reference voltage V of the comparator l.
Since it is determined by ref' and its input offset voltage Vof, the offset voltage Vo is determined by the volume of Vref' voltage.
f is added, and a current corresponding to this voltage is subtracted from the signal current/voltage conversion circuit 34.

(Effects of the Invention) Since the sampling and hold circuit according to the present invention is configured as described above, it is possible to eliminate the influence of absorbed current.

In particular, this absorbed current is affected by the time applied to the capacitor, the voltage, etc., so data tends to vary due to insufficient charging and discharging, making it a very unstable factor for data measurement. there were.

In the present invention, Δ1 of the above-mentioned error in the equation %) can be reduced by using various auxiliary circuits for the purpose.

[Brief explanation of the drawing]

FIG. 1 (1) is a circuit diagram showing a first embodiment of a sampling and holding circuit according to the present invention, and FIG. 1 (IT) is a timing chart for explaining the operation of the circuit. FIG. 2 shows a second sample-and-hold circuit according to the present invention.
It is a circuit diagram showing an example of. FIG. 3 shows the third sample-and-hold circuit according to the present invention.
It is a circuit diagram showing an example of. FIG. 4 shows the fourth sample and hold circuit according to the present invention.
It is a circuit diagram showing an example of. FIG. 5 shows the fifth sample and hold circuit according to the present invention.
It is a circuit diagram showing an example of. FIG. 6 shows the sixth sample and hold circuit according to the present invention.
It is a circuit diagram showing an example of. FIG. 7 is a circuit diagram of the problematic sampling and holding circuit, and FIG. 8 is a timing chart for explaining the operation of the circuit. 1... Comparator 2... MOS1-run lister 3... Capacitor 4... Transistor 5... Input terminal for current including signal current 7... Signal current voltage conversion circuit 9... Signal current Line 10... Reference voltage source 12... Constant current source 13... Inverter 14.15... Power supply 16... Transistor 17... Resistance divider 19... NOR circuit 22... Amplifier (NULL amplifier) 23. 24... Transistor 27... AND circuit 31. 32... Amplifier 33... Transistor 34... Logarithmic compression circuit Patent applicant Hamamatsu Photonics Co., Ltd. Agent Patent attorney Inoro Figure 1 (II) Figure 2 Figure M3 Figure M4 Figure 5 Figure 6 Figure 8

Claims (1)

[Scope of Claims] (1) A transistor whose collector is connected to a current containing a signal current component whose generation point is known and which is superimposed on a noise current that fluctuates relatively slowly; and a base-emitter of the transistor. a capacitor connected between
a differential amplifier having one input terminal connected to the collector of the transistor and the other input terminal to a reference voltage; a switching circuit connecting the output of the differential amplifier to the base of the transistor; When the error ΔI of a signal current voltage conversion circuit consisting of a sampling output circuit connected to the collector of a transistor and outputting the input when the switching circuit is turned off after the power is turned on is given by the following formula. and a sampling hold circuit configured by providing an auxiliary circuit to bring the term exp(-Ish·Th/Ch) of this equation close to 1. Note ΔI=I_0 [1-exp(-Ish・Th/Ch)]
Here, I_0: Collector current Ish of the transistor: Average value of absorbed current during sampling hold time Th: Sampling hold time C: Capacity h of the capacitor: Planck's constant (2) The auxiliary circuit The sampling and holding circuit according to claim 1, which is a circuit that effectively increases charging time. (3) The sampling and holding circuit according to claim 1, wherein the auxiliary circuit is a circuit that can reduce the capacitance of the capacitor and reduces Ish/C in the equation. (4) The sampling hold circuit according to claim 1, wherein the auxiliary circuit reduces Th in the equation.