JPS6237912B2 - - Google Patents

Info

Publication number
JPS6237912B2
JPS6237912B2 JP17604781A JP17604781A JPS6237912B2 JP S6237912 B2 JPS6237912 B2 JP S6237912B2 JP 17604781 A JP17604781 A JP 17604781A JP 17604781 A JP17604781 A JP 17604781A JP S6237912 B2 JPS6237912 B2 JP S6237912B2
Authority
JP
Japan
Prior art keywords
layer
groove
type
refractive index
ingaasp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17604781A
Other languages
Japanese (ja)
Other versions
JPS5877275A (en
Inventor
Tomoki Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17604781A priority Critical patent/JPS5877275A/en
Publication of JPS5877275A publication Critical patent/JPS5877275A/en
Publication of JPS6237912B2 publication Critical patent/JPS6237912B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • H01S5/2232Buried stripe structure with inner confining structure between the active layer and the lower electrode

Landscapes

  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 本発明は半導体レーザの製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor laser.

基本横モード発振を可能とした半導体レーザに
は種々の型式があるが、その1つに電流狭窄平凸
型レーザがある。
There are various types of semiconductor lasers capable of fundamental transverse mode oscillation, one of which is a current confinement plano-convex laser.

第1図にn型基板を用いたInP―InGaAsP電流
狭窄平凸型レーザの例を示す。上記素子は、スト
ライプ状の溝を形成したn型InP基板1上に屈折
率が基板より大きく活性層より小さくなるように
組成を選んだn型InGaAsPガイド層2を形成す
ることにより、溝領域と溝領域外の基板表面を平
坦とし、さらに上記ガイド層上に、InGaAsP活
性層3、p型InPクラツド層4、n型InP層5を
形成したのち、上記n型InP層5を溝領域上部の
みエツチングにより除き、しかるのちp型InP型
InP層6及びp型InGaAsPキヤツプ層7を形成し
た構造を有していた。
Figure 1 shows an example of an InP--InGaAsP current-confined plano-convex laser using an n-type substrate. The above element is constructed by forming an n-type InGaAsP guide layer 2 whose composition is selected such that its refractive index is larger than that of the substrate and smaller than that of the active layer on an n-type InP substrate 1 on which striped grooves are formed. After flattening the substrate surface outside the groove area and further forming an InGaAsP active layer 3, a p-type InP cladding layer 4, and an n-type InP layer 5 on the guide layer, the n-type InP layer 5 is formed only on the upper part of the groove area. Removed by etching, then p-type InP type
It had a structure in which an InP layer 6 and a p-type InGaAsP cap layer 7 were formed.

上記素子においてP型InGaAsPキヤツプ層7
に注入された電流はp型InP層6、p型InPクラ
ツド層4、InGaAsP活性層3、及びn型
InGaAsPガイド層2を経てn型InP基板1中に流
れ、n型InP層5は電流狭窄の役目を果たしてい
る。また、n型InGaAsPガイド層2は、溝上部
の活性層発光領域に接する部分の方が溝領域外上
部の活性層非発光領域に接する部分より厚くなつ
ている為、InGaAsP活性層3のうち溝上部の発
光領域の方が非発光領域より等価屈折率が高くな
り、これにより基本横モード発振を可能としてい
る。
In the above device, the P-type InGaAsP cap layer 7
The current injected into the p-type InP layer 6, the p-type InP cladding layer 4, the InGaAsP active layer 3, and the n-type
The current flows through the InGaAsP guide layer 2 into the n-type InP substrate 1, and the n-type InP layer 5 plays the role of current confinement. In addition, since the n-type InGaAsP guide layer 2 is thicker at the part of the upper part of the groove that is in contact with the active layer light emitting region than the part of the n-type InGaAsP guide layer 2 that is in contact with the active layer non-emissive region at the upper part outside the trench, the n-type InGaAsP guide layer 2 is The equivalent refractive index of the light-emitting region is higher than that of the non-light-emitting region, thereby enabling fundamental transverse mode oscillation.

しかし、上記素子は、その製作において2回の
結晶成長工程を必要とし、すなわち第1回目の結
晶成長においてn型InGaAsPガイド層2、
InGaAsP活性層3、p型InPクラツド層4、n型
InP層5を形成し、2回目の成長で、p型InP層
6、p型InGaAsPキヤツプ層7を形成してい
た。ここで2回の結晶成長を必要とすることは、
第1図に示すn型InP5のような電流狭窄を目的
として形成した層に電流通路を設ける為のエツチ
ング工程を必要とすることに起因していた。以上
の事により従来素子は多くの製造工程が必要とな
りこれが従来素子の欠点であつた。
However, the above device requires two crystal growth steps in its fabrication, that is, in the first crystal growth, the n-type InGaAsP guide layer 2,
InGaAsP active layer 3, p-type InP cladding layer 4, n-type
An InP layer 5 was formed, and in the second growth, a p-type InP layer 6 and a p-type InGaAsP cap layer 7 were formed. The need for two crystal growths means that
This is due to the fact that an etching process is required to provide a current path in a layer formed for the purpose of current confinement, such as n-type InP5 shown in FIG. As a result of the above, the conventional device required many manufacturing steps, which was a drawback of the conventional device.

このため、従来素子と同等の特性を有し、かつ
より少ない製造工程で製作できる構造の素子、す
なわち、第1図に示すn型InP層5のような電流
狭窄を目的として形成した電流ブロツキング層を
形成しても、電流通路を設ける為のエツチング工
程を必要としない構造の素子の実現が要求され
た。
For this reason, an element with a structure that has characteristics equivalent to those of conventional elements and can be manufactured with fewer manufacturing steps, that is, a current blocking layer formed for the purpose of current confinement, such as the n-type InP layer 5 shown in FIG. There was a need to realize an element with a structure that does not require an etching process to provide a current path even when a current path is formed.

本発明の目的は、従来素子の欠点を改善し、従
来素子と同等の特性を有し、かつ、従来素子より
少ない製造工程で製作可能な構造の素子、すなわ
ち、1回の結晶成長で製作可能な構造の素子を実
現することにある。
The purpose of the present invention is to improve the drawbacks of conventional elements, to provide an element having characteristics equivalent to those of conventional elements, and having a structure that can be manufactured in fewer manufacturing steps than conventional elements, that is, it can be manufactured by one crystal growth. The goal is to realize an element with a unique structure.

本発明によれば、半導体基板に形成されたスト
ライプ状の溝側面の一部がストライプ状に露出さ
れて残るように溝中及び溝外の基板表面に上記半
導体基板と反対の導電型を有するクラツド層が形
成され、さらに露出されて残つている半導体基板
の溝側面と接触し、かつ基板表面全体が平坦とな
るように上記半導体基板と同じ導電型を有し、か
つ活性層より小さく、クラツド層より大きい屈折
率を有するガイド層が溝中及び溝外に形成され、
さらに活性層、クラツド層、キヤツプ層が順次基
板全面に形成された構造とすることにより、本発
明の目的を実現することが可能となる。
According to the present invention, a cladding having a conductivity type opposite to that of the semiconductor substrate is formed in the groove and on the surface of the substrate outside the groove so that a part of the side surface of the striped groove formed in the semiconductor substrate remains exposed in a striped manner. A layer is formed, and a cladding layer is formed, which has the same conductivity type as the semiconductor substrate, is smaller than the active layer, and is in contact with the exposed side surface of the groove of the semiconductor substrate remaining, and so that the entire surface of the substrate is flat. a guide layer with a larger refractive index is formed in and outside the groove;
Furthermore, the object of the present invention can be achieved by forming an active layer, a cladding layer, and a cap layer sequentially over the entire surface of the substrate.

以下図面にしたがつて本発明を説明する。 The present invention will be explained below with reference to the drawings.

第2図に本発明のn型基板を用いたInP―
InGaAsPレーザの例を示す。第2図においてn
型InP基板1に形成された溝のうちの基板内部側
の一部と、溝領域外の基板上にp型InPクラツド
層5が形成されているが溝側面のうちの基板表面
側の一部とは接触していない。そしてp型InPク
ラツド層5が接触していない溝側面にはn型
InGaAsPガイド層2が接しており、かつ上記ガ
イド層2は溝上方と溝領域外上方の上記ガイド層
の表面が平坦となるように形成され、さらに
InGaAsP活性層3、p型InPクラツド層4及びp
型InGaAsPキヤツプ層7が順次形成されてい
る。したがつて上記素子において、p型
InGaAsPキヤツプ層7に注入された電流はp型
InPクラツド層4、InGaAsP活性層3、n型
InGaAsPガイド層2を経て、n型InP基板1の溝
側面のうち、n型InGaAsPガイド層2と接触し
ている部分より、n型InP基板1中へ流れること
になる。そしてInGaAsP活性層3のうち、溝領
域上方の部分が発光領域となる。
Figure 2 shows InP using the n-type substrate of the present invention.
An example of an InGaAsP laser is shown. In Figure 2, n
A part of the groove formed in the InP type substrate 1 on the inside of the substrate, and a part of the side surface of the groove on the substrate surface side where the p-type InP cladding layer 5 is formed on the substrate outside the groove area. has not been in contact with. Then, on the groove side surface that is not in contact with the p-type InP cladding layer 5, there is an n-type
The InGaAsP guide layer 2 is in contact with the guide layer 2, and the guide layer 2 is formed so that the surface of the guide layer above the groove and above the outside of the groove area is flat, and
InGaAsP active layer 3, p-type InP cladding layer 4 and p
A type InGaAsP cap layer 7 is successively formed. Therefore, in the above element, p-type
The current injected into the InGaAsP cap layer 7 is p-type.
InP cladding layer 4, InGaAsP active layer 3, n-type
It flows through the InGaAsP guide layer 2 and into the n-type InP substrate 1 from the portion of the groove side surface of the n-type InP substrate 1 that is in contact with the n-type InGaAsP guide layer 2 . A portion of the InGaAsP active layer 3 above the groove region becomes a light emitting region.

また、n型InGaAsPガイド層2はその屈折率
が、InGaAsP活性層3の屈折率より小さく、InP
クラツド層5の屈折率より大きくなるように組成
が選ばれており、また、上記ガイド層2は溝領域
と溝領域外上方の上記ガイド層の表面が平坦とな
るように形成されている為、溝領域の方が、溝領
域外よりも層厚が厚くなつている。このことよ
り、InGaAsP活性層4の等価屈折率は溝領域上
方の方が溝領域外上方よりも大きくなつており、
安定な基本横モード発振を可能としている。
In addition, the n-type InGaAsP guide layer 2 has a refractive index smaller than that of the InGaAsP active layer 3, and
The composition is selected so that the refractive index is higher than that of the cladding layer 5, and the guide layer 2 is formed so that the groove region and the surface of the guide layer above the groove region are flat. The layer thickness is thicker in the groove region than outside the groove region. From this, the equivalent refractive index of the InGaAsP active layer 4 is larger above the groove region than above the outside of the trench region.
This enables stable fundamental transverse mode oscillation.

以上のことにより本発明の素子は従来素子と同
様、電流阻止層を設けることにより活性層の発光
領域外に流れる電流を少なくすることができ、か
つ、安定な基本横モード発振が可能な構造となつ
ている。
As described above, the device of the present invention has a structure in which the current flowing outside the light emitting region of the active layer can be reduced by providing a current blocking layer, and stable fundamental transverse mode oscillation is possible, as in the conventional device. It's summery.

一方第2図に示すp型InPクラツド層5を形成
しても上記のごとく電流はn型InP基板1の溝側
面のうちp型InPクラツド層5が接触していない
部分より流れることができる為、従来素子のよう
に電流阻止層を形成したのち、電流を流す通路を
作る為に電流阻止層の一部をエツチングする必要
がない。このことより、従来は電流阻止層エツチ
ングの為、素子製作には2回の結晶成長を必要と
したが本発明の素子は1回の結晶成長で素子の製
作が可能であり、本発明の構造の素子は従来素子
より少ない製作工程で製作が可能である。
On the other hand, even if the p-type InP cladding layer 5 as shown in FIG. Unlike conventional devices, there is no need to form a current blocking layer and then etch a portion of the current blocking layer to create a path for current flow. From this, the device of the present invention can be fabricated by only one crystal growth, whereas conventional devices require two crystal growths due to current blocking layer etching, and the structure of the present invention The device can be manufactured with fewer manufacturing steps than conventional devices.

本発明の実施例は図2に示すn型基板を用いた
InP―InGaAsPレーザの例であり、幅4μm深さ
2μmの溝を形成したn型InP基板1上にp型
InPクラツド層5が溝領域には深さ1.5μm、溝領
域外には厚さ1μm形成され、さらに溝領域外に
おいて厚さ0.6μmとなるように、n型InGaAsP
ガイド層2が、その表面が平坦となるように形成
され、さらに全面に厚さ0.2μmのInGaAsP活性
層3、厚さ2μmのp型InPクラツド層4及び厚
さ1μmのn型InGaAsPキヤツプ層7が形成さ
れた構造である。
The embodiment of the present invention uses an n-type substrate shown in FIG.
This is an example of an InP-InGaAsP laser, in which a p-type
An InP cladding layer 5 is formed to a depth of 1.5 μm in the groove region and a thickness of 1 μm outside the trench region, and is further formed using n-type InGaAsP so as to have a thickness of 0.6 μm outside the trench region.
A guide layer 2 is formed so that its surface is flat, and is further covered with an InGaAsP active layer 3 with a thickness of 0.2 μm, a p-type InP cladding layer 4 with a thickness of 2 μm, and an n-type InGaAsP cap layer 7 with a thickness of 1 μm. This is the structure formed.

上記素子は、従来の電流狭窄平凸型レーザと同
様の特性を有するが従来素子より少ない製作工程
で製作が可能となつた。
The above device has characteristics similar to those of conventional current confinement plano-convex lasers, but can be manufactured with fewer manufacturing steps than conventional devices.

以上、本発明はn型基板を用いたInP―
InGaAsPレーザについて述べたが、p型基板を
用いてもよい。
As described above, the present invention is an InP-
Although an InGaAsP laser has been described, a p-type substrate may also be used.

また、GaAs―GaAlAsレーザについても同様
の効果が得られる。例えばp型基板を用いた
GaAlAsレーザの場合、第2図の各記号は次のよ
うになる。1はp型GaAs基板、2はp型
GaAlAsガイド層、3はGaAlAs活性層、4はn
型GaAlAsクラツド層、5はn型GaAlAsクラツ
ド層、7はn型GaAlAsキヤツプ層となる。
Similar effects can also be obtained with GaAs--GaAlAs lasers. For example, using a p-type substrate
In the case of a GaAlAs laser, each symbol in FIG. 2 is as follows. 1 is p-type GaAs substrate, 2 is p-type
GaAlAs guide layer, 3 is GaAlAs active layer, 4 is n
5 is an n-type GaAlAs clad layer, and 7 is an n-type GaAlAs cap layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電流狭窄平凸型レーザの断面
図。第2図は本発明のレーザの断面図。 各図において、1は半導体基板、2はガイド
層、3は活性層、4はクラツド層、5は電流阻止
を目的としたクラツド層、6はクラツド層、7は
キヤツプ層である。
FIG. 1 is a cross-sectional view of a conventional current confinement plano-convex laser. FIG. 2 is a cross-sectional view of the laser of the present invention. In each figure, 1 is a semiconductor substrate, 2 is a guide layer, 3 is an active layer, 4 is a cladding layer, 5 is a cladding layer for the purpose of blocking current, 6 is a cladding layer, and 7 is a cap layer.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板にストライプ状の溝を形成する工
程と、該溝の側面の一部が露出されて残るように
溝中及び溝外の基板表面に上記半導体基板と反対
の導電型を有する第1のクラツド層を形成する工
程と、さらに前記露出されて残つている溝側面と
接触し、かつ、表面全域が平担となるように、前
記半導体基板と同じ導電型を有しかつ前記第1の
クラツド層の屈折率よりも大きな屈折率を有する
ガイド層を溝領域及び溝領域外に形成する工程
と、前記ガイド層上に前記ガイド層の屈折率より
も大きい屈折率を有する活性層を形成する工程
と、前記活性層上に前記ガイド層と同一導電型を
有しかつ前記活性層の屈折率より小さい屈折率を
有する第2のクラツド層を形成する工程とを有し
て前記活性層の発光領域が発光領域外より等価屈
折率が大きくなるように前記活性層の発光領域に
接するガイド層を発光領域外に接する部分より層
厚が厚くなるように形成したことを特徴とする半
導体レーザの製造方法。
1. Forming a striped groove in a semiconductor substrate, and forming a first groove having a conductivity type opposite to that of the semiconductor substrate in the groove and on the surface of the substrate outside the groove so that a part of the side surface of the groove remains exposed. forming the first cladding layer, which has the same conductivity type as the semiconductor substrate and has the same conductivity type as the semiconductor substrate, so as to be in contact with the exposed remaining groove side surface and to have a flat surface over the entire surface; a step of forming a guide layer having a refractive index greater than the refractive index of the layer in the groove region and outside the groove region; and a step of forming an active layer having a refractive index greater than the refractive index of the guide layer on the guide layer. and forming a second cladding layer on the active layer that has the same conductivity type as the guide layer and has a refractive index smaller than the refractive index of the active layer. A method for manufacturing a semiconductor laser, characterized in that the guide layer in contact with the light emitting region of the active layer is formed to be thicker than the portion in contact with the outside of the light emitting region so that the equivalent refractive index is larger than that outside the light emitting region. .
JP17604781A 1981-11-02 1981-11-02 Semiconductor laser Granted JPS5877275A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17604781A JPS5877275A (en) 1981-11-02 1981-11-02 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17604781A JPS5877275A (en) 1981-11-02 1981-11-02 Semiconductor laser

Publications (2)

Publication Number Publication Date
JPS5877275A JPS5877275A (en) 1983-05-10
JPS6237912B2 true JPS6237912B2 (en) 1987-08-14

Family

ID=16006784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17604781A Granted JPS5877275A (en) 1981-11-02 1981-11-02 Semiconductor laser

Country Status (1)

Country Link
JP (1) JPS5877275A (en)

Also Published As

Publication number Publication date
JPS5877275A (en) 1983-05-10

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