JPS6237535B2 - - Google Patents

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Publication number
JPS6237535B2
JPS6237535B2 JP52157997A JP15799777A JPS6237535B2 JP S6237535 B2 JPS6237535 B2 JP S6237535B2 JP 52157997 A JP52157997 A JP 52157997A JP 15799777 A JP15799777 A JP 15799777A JP S6237535 B2 JPS6237535 B2 JP S6237535B2
Authority
JP
Japan
Prior art keywords
electrode
potential
conductivity type
terminal
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52157997A
Other languages
Japanese (ja)
Other versions
JPS5491085A (en
Inventor
Mitsuru Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP15799777A priority Critical patent/JPS5491085A/en
Publication of JPS5491085A publication Critical patent/JPS5491085A/en
Publication of JPS6237535B2 publication Critical patent/JPS6237535B2/ja
Granted legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置にかかり、特に半導体のP
−n接合及び絶縁物質よりなる蓄電容量部と有す
る半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and in particular to
The present invention relates to a semiconductor device having a -n junction and a storage capacitor section made of an insulating material.

従来の半導体表面に形成される集積回路に於い
ては、これを形成する個々のトランジスタが
MOS(Unipolar)TrかBipolar Trかの何れに拘
らず、該集積回路内に現われる電位は、一般に使
用される二種の電源電圧値の間の値をとるもので
ある。しかし該集積回路でその回路構成に依り、
当電源電圧よりも高い又は低い電圧を必要とする
場合がある。このためこのような高い又は低い電
圧を該集積回路内で上記二種の電源電圧のもとで
発生させる方法が特別に考えられている。例えば
その使用する電源電圧の正値又は負値に拘らず集
積回路内に絶対値に関して電源電圧値より大きな
電位を必要とするとき、特別にブートストラツプ
回路を同集積回路内に構成する。又他例では、該
集積回路内に当電源の極性と逆の極性を有する一
定電位を発生するため、チヤージポンプ(文献:
IE3 VOL ED−16、NO 3 Charge Pumping
in Devicesにこのチヤージポンプの動作原理が述
べられている)と呼ばれる回路を構成する案が提
案され且つ製品化されている。
In conventional integrated circuits formed on the surface of semiconductors, the individual transistors that form them are
Regardless of whether it is a MOS (Unipolar) Tr or a Bipolar Tr, the potential appearing within the integrated circuit takes a value between two commonly used power supply voltage values. However, depending on the circuit configuration of the integrated circuit,
A voltage higher or lower than the current power supply voltage may be required. For this reason, special methods have been devised to generate such high or low voltages within the integrated circuit under the above two types of supply voltages. For example, when an integrated circuit requires a potential greater in absolute value than the power supply voltage value, regardless of whether the power supply voltage used is positive or negative, a bootstrap circuit is specially constructed within the integrated circuit. In another example, a charge pump (Reference:
IE 3 VOL ED−16, NO 3 Charge Pumping
In Devices, the operating principle of this charge pump is described.) A circuit configuration called ``In Devices'' has been proposed and commercialized.

本発明は、上記の2例に示された主旨と同じ思
想の下に半導体基体表面に形成される集積回路内
に同回路で使用される電源電圧とその極性が逆の
電位を得る半導体装置を提供せんとするものであ
る。即ち、少くもその極性が正の電圧と接地電圧
を電源電圧とする集積回路内に極性が負の電位を
再現性よく発生する。又は少くもその極性が負の
電圧と接地電圧を電源電圧とする集積回路内に極
性が正の電位を再現性よく発生する半導体装置を
提供することを目的とする。
The present invention is based on the same idea as shown in the above two examples, and provides a semiconductor device which obtains a potential in an integrated circuit formed on the surface of a semiconductor substrate, the polarity of which is opposite to the power supply voltage used in the circuit. This is what we intend to provide. That is, a potential with a negative polarity is generated with good reproducibility in an integrated circuit whose power supply voltages are at least a voltage with a positive polarity and a ground voltage. Or at least, it is an object of the present invention to provide a semiconductor device that generates a potential with positive polarity with good reproducibility in an integrated circuit whose power supply voltages are a voltage with negative polarity and a ground voltage.

本発明の特徴は、半導体基体表面上に該基体の
導電型と異る導電型を有する領域を少くとも2領
域形成し、この内の1領域を蓄電容量部の1対の
電極の1極とし、絶縁物質をはさんで相対した他
方の蓄電容量部の電極を形成し、当電極を先述し
た該基体の導電型と異る導電型を有する残りの領
域がダイオードの1電極となるダイオードの他方
電極に接続する構成としたことである。
A feature of the present invention is that at least two regions having a conductivity type different from that of the semiconductor substrate are formed on the surface of the semiconductor substrate, and one of the regions is used as one pole of a pair of electrodes of the capacitor. , forming the electrode of the other capacitor portion facing each other with an insulating material in between, and the remaining region having a conductivity type different from the conductivity type of the base described above serves as one electrode of the diode. The structure is such that it is connected to an electrode.

次に実施例で以つて本発明の詳細な説明を行
う。以下その導電型がP型の半導体基体の場合に
ついてのみ述べるが、N型の半導体基体の場合も
全く同様となることに前もつて言及しておく。但
し、この場合半導体の導電型は当実施例であられ
る導電型とは全て逆になる。
Next, the present invention will be explained in detail with reference to Examples. In the following, only the case of a semiconductor substrate whose conductivity type is P type will be described, but it should be mentioned in advance that the same applies to the case of a semiconductor substrate whose conductivity type is N type. However, in this case, the conductivity types of the semiconductors are all opposite to those in this embodiment.

第1図の如く導電型がP型の半導体基体101
の表面に比較的厚い膜厚を有する絶縁物質102
を形成し、該絶縁物質が形成されていない該半導
体基体表面部に導電型がN型の領域103,10
4を形成する。次に斯くの如きN型領域のうちの
1領域103がその1対の電極の一方となる蓄電
容量部の絶縁物質105(例えば二酸化シリコン
膜、シリコン窒化膜)を設け、当蓄電容量部の他
方の電極106を形成する。ここで当蓄電部の片
電極106はアルミ等の金属又は、高濃度有効不
純物(本実施例ではP型不純物)を含有する半導
体物質で構成されるか又は、アルミ等の金属と高
濃度有効不純物を含有する半導体物質を接続した
姿態の電極で構成される。斯くの如き蓄電容量部
の片側電極106はその導電型がP型の領域10
7とオーミツクに接続される。ここで該P型領域
107は先述したN型導電型領域の巾103と異
る領域104に構成されており、領域107,1
04は半導体のP−n接合111を有するダイオ
ードを形成する。次に先述したN型導電領域10
3部に電極108を、該蓄電容量部の片側電極1
06に取り出し電極109を、先述した他のN型
導電領域104部の電極110をそれぞれ形成す
る。斯くして本発明に於ける半導体装置は構成さ
れる。
As shown in FIG. 1, a semiconductor substrate 101 whose conductivity type is P type.
An insulating material 102 having a relatively thick film thickness on the surface of
, and regions 103 and 10 of N type conductivity are formed on the surface portion of the semiconductor substrate where the insulating material is not formed.
form 4. Next, one region 103 of such N-type regions is provided with an insulating material 105 (for example, a silicon dioxide film, a silicon nitride film) of a storage capacitor portion, which becomes one of the pair of electrodes, and the other region 103 of the storage capacitor portion is The electrode 106 is formed. Here, the single electrode 106 of the power storage unit is made of a metal such as aluminum, a semiconductor material containing a high concentration effective impurity (P-type impurity in this embodiment), or a metal such as aluminum and a high concentration effective impurity. It consists of an electrode connected to a semiconductor material containing . One side electrode 106 of such a storage capacitor has a region 10 whose conductivity type is P type.
7 and is connected to Ohmic. Here, the P-type region 107 is configured in a region 104 different from the width 103 of the N-type conductivity region described above, and the regions 107, 1
04 forms a diode having a semiconductor P-n junction 111. Next, the N-type conductive region 10 mentioned above
The electrode 108 is attached to the third part, and the electrode 108 is attached to one side of the storage capacitor part.
In step 06, the extraction electrode 109 and the electrode 110 of the other N-type conductive region 104 described above are formed. The semiconductor device according to the present invention is thus constructed.

次に第2図に本発明の半導体装置の等価回路概
略図を示す。この中でaの回路は半導体基体(第
1図の101)がP型の導電性を有する場合であ
り、bの回路は同基体がN型の導電性を有する場
合である。又第3図に本発明に於ける入力パルス
と出力パルスを示した。当第2図、第3図並びに
第1図を参照しながら本発明の動作方法及び原理
について説明する。ここで第2図の201(20
1′),202(202′),203(203′)は
それぞれ第1図の108,109,110に対応
するものである。第2図201(第1図108)
に第3図Aの如き矩形パルスを与える。本発明半
導体装置の作動初期では、端子203が接地され
ておりしかも端子201の電位が初め接地電位の
とき端子202の電位はP−n接合の内部発生電
位差だけ接地電位より低くなる。次に端子201
の電位が正に上昇すると容量204,204′を
介して容量カツプリングが起り端子202の電位
が正に上昇しようとする。しかしここでダイオー
ド205,205′が順方向にバイアスされるこ
とになり、容量カツプリングによる端子202の
電位上昇は阻止される。即ち、端子202部に接
地端子203より電子が注入されると等価のこと
が生じる。次に再び端子201に加えられる矩形
パルスの電位が接地電位になる時、再び容量20
4を介する容量カツプリングにより端子202の
電位は下がる。この時の電圧は(1)式で表わされ
る。
Next, FIG. 2 shows a schematic diagram of an equivalent circuit of the semiconductor device of the present invention. Among these, circuit a is a case where the semiconductor substrate (101 in FIG. 1) has P-type conductivity, and circuit b is a case where the same substrate has N-type conductivity. Further, FIG. 3 shows input pulses and output pulses in the present invention. The operating method and principle of the present invention will be explained with reference to FIGS. 2, 3, and 1. Here, 201 (20
1'), 202 (202'), and 203 (203') correspond to 108, 109, and 110 in FIG. 1, respectively. Figure 2 201 (Figure 1 108)
A rectangular pulse as shown in FIG. 3A is given to At the initial stage of operation of the semiconductor device of the present invention, the terminal 203 is grounded, and when the potential of the terminal 201 is initially at the ground potential, the potential of the terminal 202 becomes lower than the ground potential by the internally generated potential difference of the P-n junction. Next, terminal 201
When the potential of the terminal 202 increases positively, capacitive coupling occurs through the capacitors 204 and 204', and the potential of the terminal 202 tends to increase positively. However, the diodes 205, 205' are now biased in the forward direction, and an increase in the potential of the terminal 202 due to capacitive coupling is prevented. That is, when electrons are injected into the terminal 202 portion from the ground terminal 203, an equivalent phenomenon occurs. Next, when the potential of the rectangular pulse applied to the terminal 201 again becomes the ground potential, the capacitance 201
4, the potential at terminal 202 drops. The voltage at this time is expressed by equation (1).

V=−(|Vin|+Vo) ……(1)式 ここでVinはp−n接合の接触電位であり、Vo
は端子201に加えられる矩形パルスの高い方の
電位を示す。すなわち、第2図の201端子に第3
図Aの如き接地電位と正値電位の間の矩形パルス
を入力すると第2図端子202には第3図Bに示
した如き矩形パルス即ち接地電位と(1)式 V=−(|Vin|+Vo)の電位の矩形パルスが
発生する。以上第2図aについて述べたが、bの
場合には、端子203′を接地した状態で端子2
01′に接地電位と、負の極性電位をもつ矩形パ
ルスを与えると、aの場合とは逆に容量204′
に依る容量カツプリングにより端子202′部に
+|Vin|電位と{|Vin|+|Vo|)}電位の矩
形パルスが発生する。斯くの如く、本発明は、半
導体のp−n接合で以つて電流方向の非可逆性を
与えながら容量カツプリングで以つて電源電圧と
逆極性の信号パルスを再現性よく発生する。斯く
の如き逆極性の信号パルスは例えば集積回路内の
デプレツシヨン型MOS電界効果トランジスタの
作動に有効に使用できる。
V=-(|Vin|+Vo)...Equation (1) Here, Vin is the contact potential of the p-n junction, and Vo
indicates the higher potential of the rectangular pulse applied to terminal 201. In other words, the third terminal is connected to the 201 terminal in Figure 2.
When a rectangular pulse between the ground potential and positive potential as shown in Figure A is input, the terminal 202 in Figure 2 receives a rectangular pulse as shown in Figure 3B, that is, the ground potential, and the equation (1) V = - ( | Vin | A rectangular pulse with a potential of +Vo) is generated. As described above with respect to FIG. 2 a, in case b, the terminal 203' is grounded and the
When a ground potential and a rectangular pulse with a negative polarity potential are applied to 01', the capacitance 204' increases, contrary to the case of a.
A rectangular pulse of the +|Vin| potential and the {|Vin|+|Vo|)} potential is generated at the terminal 202' due to the capacitive coupling caused by. As described above, the present invention generates signal pulses with a polarity opposite to the power supply voltage with good reproducibility using capacitive coupling while providing irreversibility in the current direction using a semiconductor p-n junction. Such reverse polarity signal pulses can be effectively used, for example, to operate depletion type MOS field effect transistors in integrated circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す断面図であ
る。第2図は本発明における半導体装置の等価回
路概略図である。第3図Aは本発明の作動入力パ
ルスを示す図であり、第3図Bはその出力パルス
を示す図である。 尚、図において、101……半導体基体、10
2……厚い絶縁物質、103……半導体基体10
1と異なる導電型の半導体領域1、104……半
導体基体101と異る導電型の半導体領域2、1
05……蓄電容量用絶縁物質、106……蓄電容
量部の1電極、107……p−n接合ダイオード
の1電極、108……蓄電容量部の1取り出し電
極、109……蓄電容量部の1取り出し電極、1
10……p−n接合ダイオード1取り出し電極、
111……p−n接合、201,201′……第
1図の108に相当する蓄電容量部の電極、20
2,202′……第1図の109に相当する蓄電
容量部の電極、203,203′……第1図の1
10に相当するp−n接合ダイオード電極、20
4,204′……蓄電容量部、205,205′…
…半導体p−n接合ダイオードである。
FIG. 1 is a sectional view showing one embodiment of the present invention. FIG. 2 is a schematic diagram of an equivalent circuit of a semiconductor device according to the present invention. FIG. 3A is a diagram showing the actuation input pulse of the present invention, and FIG. 3B is a diagram showing its output pulse. In the figure, 101...semiconductor substrate, 10
2... Thick insulating material, 103... Semiconductor substrate 10
Semiconductor region 1, 104 of a conductivity type different from 1...Semiconductor region 2, 1 of a conductivity type different from that of the semiconductor substrate 101
05... Insulating material for storage capacity, 106... 1 electrode of electricity storage capacitor, 107... 1 electrode of p-n junction diode, 108... 1 extraction electrode of electricity storage capacitor, 109... 1 electrode of electricity storage capacitor Take-out electrode, 1
10... p-n junction diode 1 extraction electrode,
111...p-n junction, 201, 201'...electrode of the storage capacitor section corresponding to 108 in FIG. 1, 20
2,202'...Electrode of the storage capacitor section corresponding to 109 in Fig. 1, 203,203'...1 in Fig. 1
p-n junction diode electrode corresponding to 10, 20
4,204'...Electricity storage capacity section, 205,205'...
...It is a semiconductor p-n junction diode.

Claims (1)

【特許請求の範囲】[Claims] 1 一導電型半導体基体の一主表面に逆導電型領
域を少なくとも2個所設け、一方の該逆導電型領
域に一導電型領域を設け、他方の該逆導電型領域
を第1の電極とし第2の電極を前記一導電型領域
に接続した蓄電容量部を形成し、前記第1の電極
に印加した信号パルスと逆極性の信号パルスを前
記第2の電極から取り出すことを特徴とする半導
体装置。
1. At least two regions of opposite conductivity type are provided on one main surface of a semiconductor substrate of one conductivity type, a region of one conductivity type is provided in one of the regions of opposite conductivity type, and the other region of opposite conductivity type is used as a first electrode. A semiconductor device characterized in that a storage capacitor section is formed by connecting a second electrode to the one conductivity type region, and a signal pulse having a polarity opposite to a signal pulse applied to the first electrode is extracted from the second electrode. .
JP15799777A 1977-12-28 1977-12-28 Semiconductor device Granted JPS5491085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15799777A JPS5491085A (en) 1977-12-28 1977-12-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15799777A JPS5491085A (en) 1977-12-28 1977-12-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5491085A JPS5491085A (en) 1979-07-19
JPS6237535B2 true JPS6237535B2 (en) 1987-08-13

Family

ID=15661978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15799777A Granted JPS5491085A (en) 1977-12-28 1977-12-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5491085A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5222401A (en) * 1975-08-13 1977-02-19 Matsushita Electric Ind Co Ltd Tuner

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5222401A (en) * 1975-08-13 1977-02-19 Matsushita Electric Ind Co Ltd Tuner

Also Published As

Publication number Publication date
JPS5491085A (en) 1979-07-19

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