JPS6236440B2 - - Google Patents
Info
- Publication number
- JPS6236440B2 JPS6236440B2 JP54131877A JP13187779A JPS6236440B2 JP S6236440 B2 JPS6236440 B2 JP S6236440B2 JP 54131877 A JP54131877 A JP 54131877A JP 13187779 A JP13187779 A JP 13187779A JP S6236440 B2 JPS6236440 B2 JP S6236440B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog
- stereo
- output
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000284 extract Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04S—STEREOPHONIC SYSTEMS
- H04S1/00—Two-channel systems
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Acoustics & Sound (AREA)
- Signal Processing (AREA)
- Stereophonic System (AREA)
Description
【発明の詳細な説明】 本発明は、ステレオ信号処理回路に関する。[Detailed description of the invention] The present invention relates to a stereo signal processing circuit.
従来、テレビジヨン音声多重放送の音声再生の
ため、テレビジヨン受像機の左右のスピーカの間
隔が比較的小さいことを考慮して、ステレオ感を
拡大するため右チヤンネル信号Ｒ中に左チヤンネ
ル信号Ｌの逆相成分を若干入れ、また左チヤンネ
ル信号Ｌ中に右チヤンネル信号Ｒの逆相成分を若
干入れ、ステレオ音声再生することが提案されて
いる。 Conventionally, for audio reproduction of television audio multiplex broadcasts, taking into account the relatively small distance between the left and right speakers of a television receiver, the left channel signal L was added to the right channel signal R in order to expand the stereo feeling. It has been proposed to add some anti-phase components and also add some anti-phase components of the right channel signal R into the left channel signal L to reproduce stereo sound.
第１図は、従来より提案されているステレオ感
拡大のためのステレオ信号処理回路を示す。同図
において、テレビジヨン音声多重放送信号の主チ
ヤンネル信号である（Ｌ＋Ｒ）信号（すなわち左
チヤンネル信号Ｌと右チヤンネル信号Ｒとの和信
号）と副チヤンネル信号である（Ｌ−Ｒ）信号
（すなわち左チヤンネル信号Ｌと右チヤンネル信
号Ｒとの差信号）とがアナログ加算器１０とアナ
ログ減算器１１とに印加される。従つて、アナロ
グ加算器１０の出力から2L信号（すなわち左チ
ヤンネル信号Ｌの２倍の振幅を有する信号）が得
られ、アナログ減算器１１の出力から2R信号
（すなわち右チヤンネル信号の２倍の振幅を有す
る信号）が得られる。係数器１２，１３は制御電
圧ＶCによつて、減衰率ｎが可変となる制御回路
であるので、アナログ減算器１４，１５の各出力
からそれぞれ（2L−ｎ・Ｒ）信号と（2R−ｎ・
Ｌ）信号が得られる。かくして左チヤンネル信号
Ｌ中に右チヤンネル信号Ｒの逆相成分が若干入
り、右チヤンネル信号Ｒ中に左チヤンネル信号が
若干入るため、ステレオ音声再生時のステレオ感
が拡大され、ステレオ・ワイド化が実現できる。 FIG. 1 shows a conventionally proposed stereo signal processing circuit for expanding the stereo effect. In the figure, an (L+R) signal (i.e., a sum signal of a left channel signal L and a right channel signal R) which is a main channel signal of a television audio multiplex broadcast signal and an (L-R) signal (i.e., a sum signal of a left channel signal L and a right channel signal R) which is a sub channel signal A difference signal between the left channel signal L and the right channel signal R) is applied to an analog adder 10 and an analog subtracter 11. Therefore, a 2L signal (i.e., a signal with twice the amplitude of the left channel signal L) is obtained from the output of the analog adder 10, and a 2R signal (i.e., a signal with twice the amplitude of the right channel signal) is obtained from the output of the analog subtracter 11. ) is obtained. Since the coefficient multipliers 12 and 13 are control circuits in which the attenuation rate n is variable depending on the control voltage V C , the (2L-n·R) and (2R- n・
L) A signal is obtained. In this way, a small amount of the reverse phase component of the right channel signal R enters the left channel signal L, and a small amount of the left channel signal enters the right channel signal R, expanding the stereo feeling during stereo audio playback and realizing stereo widening. can.
一方、制御電圧ＶCを調整することによつて減
衰率ｎ＝０となり、アナログ減算器１４，１５の
各出力からそれぞれ2L信号と2R信号とが得ら
れ、通常のステレオ音声再生が行われる。 On the other hand, by adjusting the control voltage V C , the attenuation rate n=0, and a 2L signal and a 2R signal are obtained from each output of the analog subtracters 14 and 15, respectively, and normal stereo audio reproduction is performed.
しかしながら、従来より提案されているこのス
テレオ信号処理回路は、ステレオ・ワイド化の際
の全体の音量は（２−ｎ）（Ｌ＋Ｒ）となり、通
常時の全体の音量２・（Ｌ＋Ｒ）より減少するこ
ととなり都合が悪い。 However, in this conventionally proposed stereo signal processing circuit, the overall volume when widening the stereo becomes (2-n)(L+R), which is lower than the overall volume during normal use, which is 2·(L+R). This is inconvenient.
従つて、本発明の目的とするところは、通常時
およびステレオ・ワイド化の際の全体の音量の変
化の無いステレオ信号処理回路を提供することに
あり、以下実施例に沿つて本発明を具体的に説明
する。 Therefore, an object of the present invention is to provide a stereo signal processing circuit in which the overall volume does not change during normal operation and during stereo widening. Explain in detail.
第２図は、本発明の一実施例によるステレオ・
ワイド化のためのステレオ信号処理回路を示す。
テレビジヨン音声多重放送信号の（Ｌ＋Ｒ）信号
と（Ｌ−Ｒ）信号とはそれぞれ端子T1と端子T2
とに印加されている。演算増幅器２０の非反転入
力端子（＋）は上記端子T2に接続され、反転入
力端子（−）は抵抗Ｚfを介して出力端子T3に接
続されるとともに抵抗Ｚrを介して接地されてい
る。抵抗Ｚfの両端には、通常ステレオ−ステレ
オ・ワイド化切換えのためのスイツチ手段SWが
接続されている。 FIG. 2 shows a stereo system according to an embodiment of the present invention.
This shows a stereo signal processing circuit for widening.
The (L+R) signal and (L-R) signal of the television audio multiplex broadcast signal are terminal T 1 and terminal T 2 , respectively.
is applied to. The non-inverting input terminal (+) of the operational amplifier 20 is connected to the terminal T2 , and the inverting input terminal (-) is connected to the output terminal T3 via a resistor Zf and is grounded via a resistor Zr . ing. Switch means SW for stereo-stereo widening switching is normally connected to both ends of the resistor Z f .
スイツチ手段SWがオフの場合、端子T2−T3間
の電圧利得ＧVは下記のように定められる。 When the switch means SW is off, the voltage gain G V between terminals T 2 -T 3 is determined as follows.
ＧV＝１＋Ｚｆ／Ｚｒ＝１＋ｎ ……(1)
これに対し、スイツチ手段SWがオンの場合、
この電圧利得ＧV′はＺf＝０のため、１となる。G V =1+Z f /Z r =1+n...(1) On the other hand, when the switch means SW is on,
This voltage gain G V ' is 1 because Z f =0.
ステレオ・ワイド化がスイツチ手段SWをオフ
とすることによつて実行され、アナログ加算器２
１の出力より（２＋ｎ）Ｌ−ｎ・Ｒ信号が得ら
れ、アナログ減算器２２の出力から（２＋ｎ）Ｒ
−ｎ・Ｌ信号が得られる。 Stereo widening is performed by turning off the switch means SW, and the analog adder 2
A (2+n)L-n·R signal is obtained from the output of the analog subtracter 22, and a (2+n)R signal is obtained from the output of the analog subtracter 22.
−n·L signal is obtained.
通常のステレオ音声再生は、スイツチ手段SW
をオンとすることによつて実行され、アナログ加
算器２１の出力から2L信号が得られ、アナログ
減算器２２の出力から2R信号が得られる。 For normal stereo audio playback, switch means SW
A 2L signal is obtained from the output of the analog adder 21, and a 2R signal is obtained from the output of the analog subtracter 22.
従つて、本発明によればステレオ・ワイド化の
際の全体の音量は（２＋ｎ）Ｌ−ｎ・Ｒ＋（２＋
ｎ）Ｒ−ｎ・Ｌ＝２（Ｌ＋Ｒ）となり、通常時の
全体の音量２（Ｌ＋Ｒ）と等しくなり、初期の目
的を達成することができる。 Therefore, according to the present invention, the overall volume when stereo widening is (2+n)L-n・R+(2+
n) R-n·L=2(L+R), which is equal to the overall volume 2(L+R) during normal operation, and the initial objective can be achieved.
本発明は上記実施例に限定されるものではな
く、種々変形した実施形態を採用することが出来
る。 The present invention is not limited to the above embodiments, and various modified embodiments can be adopted.
第３図は、通常ステレオ−ステレオ・ワイド化
切換えのためのスイツチ手段SWをCMOSアナロ
グスイツチにより構成した実施例を示している。
ＮチヤンネルMOSトランジスタＱNとＰチヤンネ
ルMOSトランジスタＱPの各リースと各ドレイン
は共通に接続され、ゲート間にはインバータ回路
INVが接続されている。制御電圧ＶCがローレベ
ルの場合、トランジスタＱP，ＱNがオンとなり、
制御電圧ＶCがハイレベルの場合はトランジスタ
ＱP，ＱNがオフとなつて、上述の如き通常ステレ
オ−ステレオ・ワイド化の切換えを実行すること
ができる。 FIG. 3 shows an embodiment in which the switch means SW for normal stereo/stereo widening switching is constituted by a CMOS analog switch.
The leases and drains of the N-channel MOS transistor Q N and the P-channel MOS transistor Q P are commonly connected, and an inverter circuit is connected between the gates.
INV is connected. When the control voltage V C is low level, the transistors Q P and Q N are turned on, and
When the control voltage V C is at a high level, the transistors Q P and Q N are turned off, making it possible to perform the normal stereo-stereo widening switching as described above.
第４図は、本発明の他の実施例によるステレ
オ・ワイド化のためのステレオ信号処理回路を示
す。テレビジヨン音声多重放送信号の主チヤンネ
ル信号であるところの（Ｌ＋Ｒ）信号と（１＋
ｎ）の係数を有する副チヤンネル信号すなわち
（１＋ｎ）・（Ｌ−Ｒ）信号とが端子T4と端子T5と
に印加されている。端子T5には、トランジスタ
ＱC、抵抗R1，R2，R3から構成された切換回路４
０が配置されている。 FIG. 4 shows a stereo signal processing circuit for stereo widening according to another embodiment of the present invention. The (L+R) signal, which is the main channel signal of the television audio multiplex broadcast signal, and the (1+
A sub-channel signal having a coefficient of n), that is, a (1+n)·(LR) signal, is applied to terminal T4 and terminal T5 . A switching circuit 4 consisting of a transistor Q C and resistors R 1 , R 2 , and R 3 is connected to the terminal T 5 .
0 is placed.
この抵抗R3は、抵抗R1，R2より十分大きな抵
抗値に選定され、また抵抗R1，R2は次式を満足
するようにその抵抗値が設定されている。 This resistor R 3 is selected to have a sufficiently larger resistance value than the resistors R 1 and R 2 , and the resistance values of the resistors R 1 and R 2 are set so as to satisfy the following equation.
従つて、制御電圧ＶCを十分にハイレベルとす
るとトランジスタＱCは飽和領域にバイアスさ
れ、そのコレクタ・エミツタ間の交流インピーダ
ンスは実質的に零となる。かくして、端子T6に
現われる信号は、端子T5に印加された信号を抵
抗R1，R2で分圧されたものとなり、アナログ加
算器４１の出力より2L信号が得られ、アナログ
減算器４２の出力より2R信号が得られる。 Therefore, when the control voltage V C is set to a sufficiently high level, the transistor Q C is biased into the saturation region, and the AC impedance between its collector and emitter becomes substantially zero. In this way, the signal appearing at the terminal T 6 is obtained by dividing the signal applied to the terminal T 5 by the resistors R 1 and R 2 , and a 2L signal is obtained from the output of the analog adder 41 and the signal applied to the analog subtracter 42 A 2R signal is obtained from the output of
一方、制御電圧ＶCをローレベルとするとトラ
ンジスタＱCはオフとなり、抵抗R3の抵抗値は極
めて高いため、端子６に現われる信号は端子T5
に印加された信号（１＋ｎ）・（Ｌ−Ｒ）に実質的
に等しくなる。かくして、アナログ加算器４１の
出力より（２＋ｎ）Ｌ−ｎ・Ｒ信号が得られ、ア
ナログ減算器４２の出力より（２＋ｎ）Ｒ−ｎ・
Ｌ信号が得られる。 On the other hand, when the control voltage V C is set to low level, the transistor Q C turns off and the resistance value of the resistor R 3 is extremely high, so the signal appearing at the terminal 6 is transferred to the terminal T 5
It becomes substantially equal to the signal (1+n)·(LR) applied to. In this way, (2+n)L-n.R signal is obtained from the output of the analog adder 41, and (2+n)R-n.R signal is obtained from the output of the analog subtracter 42.
An L signal is obtained.
第１図は従来より提案されているステレオ信号
処理回路を示し、第２図は本発明の一実施例によ
るステレオ信号処理回路を示し、第３図は第２図
に示した実施例の一部を変形した実施例を示し、
第４図は本発明の他の実施例によるステレオ信号
処理回路を示す。
２１，４１……アナログ加算器、２２，４２…
…アナログ減算器。
FIG. 1 shows a conventionally proposed stereo signal processing circuit, FIG. 2 shows a stereo signal processing circuit according to an embodiment of the present invention, and FIG. 3 shows a part of the embodiment shown in FIG. An example is shown in which a modified example is shown,
FIG. 4 shows a stereo signal processing circuit according to another embodiment of the invention. 21, 41...Analog adder, 22, 42...
...Analog subtractor.
Claims (1)
備し、該アナログ加算手段の一方の入力端子と該
アナログ減算手段の一方の入力端子とに（Ｌ＋
Ｒ）信号を印加してなり、前記アナログ加算手段
の他方の入力端子と前記アナログ減算手段の他方
の入力端子に（Ｌ−Ｒ）信号を印加することによ
つて前記アナログ加算手段の出力より2L信号を
取り出し前記アナログ減算手段の出力より2R信
号を取り出して通常ステレオ再生出力信号を送出
し、前記アナログ加算手段の前記他方の入力端子
と前記アナログ減算手段の前記他方の入力端子に
印加される信号を（１＋ｎ）・（Ｌ−Ｒ）信号に切
換えることによつて前記アナログ加算手段の前記
出力より（２＋ｎ）Ｌ−ｎ・Ｒ信号を取り出し前
記アナログ減算手段の前記出力より（２＋ｎ）Ｒ
−ｎ・Ｌ信号を取り出してワイド化されたステレ
オ再生出力信号を送出することを特徴とするステ
レオ信号処理回路。1 comprises an analog addition means and an analog subtraction means, and one input terminal of the analog addition means and one input terminal of the analog subtraction means are connected to (L+
2L from the output of the analog addition means by applying a (LR) signal to the other input terminal of the analog addition means and the other input terminal of the analog subtraction means. A signal is taken out, a 2R signal is taken out from the output of the analog subtraction means, and a normal stereo reproduction output signal is sent out, and the signal is applied to the other input terminal of the analog addition means and the other input terminal of the analog subtraction means. By switching the signal to a (1+n).(L-R) signal, a (2+n)L-n.R signal is extracted from the output of the analog addition means and (2+n)R is extracted from the output of the analog subtraction means.
- A stereo signal processing circuit characterized in that it extracts n and L signals and sends out a widened stereo reproduction output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13187779A JPS5656100A (en) | 1979-10-15 | 1979-10-15 | Stereophonic signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13187779A JPS5656100A (en) | 1979-10-15 | 1979-10-15 | Stereophonic signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5656100A JPS5656100A (en) | 1981-05-16 |
| JPS6236440B2 true JPS6236440B2 (en) | 1987-08-06 |
Family
ID=15068222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13187779A Granted JPS5656100A (en) | 1979-10-15 | 1979-10-15 | Stereophonic signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5656100A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8686996B2 (en) | 1998-07-21 | 2014-04-01 | Landmark Graphics Corporation | System and method for analyzing and imaging three-dimensional volume data sets using a three-dimensional sampling probe |
-
1979
- 1979-10-15 JP JP13187779A patent/JPS5656100A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8686996B2 (en) | 1998-07-21 | 2014-04-01 | Landmark Graphics Corporation | System and method for analyzing and imaging three-dimensional volume data sets using a three-dimensional sampling probe |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5656100A (en) | 1981-05-16 |
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