JPS6236099A - Method for growing si in liquid phase - Google Patents

Abstract

PURPOSE:To obtain a reliable liq.-phase grown layer of Si without narrowing the operating frequency band by using a soln. of the raw solute of Si in a solvent consisting essentially of Al and the balance B and Sn or Ge and Ga and growing Si. CONSTITUTION:A raw solute of Si is dissolved in a solvent consisting essentially of Al and contg., as the balance, B as a P type impurity which is most highly soluble in Si and is used for increasing the carrier concn., Sn or Ge as a metal to increase the lattice constant in silicon and Ga as a metal to break the solvent when the soln. is solidified. A desired epitaxial growth layer is easily obtained by using the soln.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for liquid phase growth of Si.

[Prior art]

In recent years, there has been an increasing demand for improved performance of high frequency devices or high power devices. It is well known that the performance of high-frequency devices has dramatically improved due to advances in microfabrication technology or the adoption of compound semiconductors.For example, FETs using GaAs are characterized by high electron mobility. The performance has been improved year by year, and the noise figure has been rapidly improved.

On the other hand, it goes without saying that improvements in silicon and devices are progressing year by year, and it is no exaggeration to say that this is mainly supported by advances in wafer processing technology, centered on microfabrication technology. What is particularly desired are high-voltage, high-frequency devices such as PIN diodes, static induction transistors, and static induction thyristors that use silicon with a high purity that is difficult to achieve with compound semiconductors.

Silicon PIN diodes used in high frequency regions have many uses such as switches, attenuators, phase shifters, and limiters.

Static induction transistors and static induction thyristors are expected to be used as high-frequency power devices.

The present invention provides a liquid phase growth method for realizing the impurity distribution required to improve the performance of these silicon devices.

The theoretical intrinsic resistivity of silicon at room temperature is approximately 260 kg, ohm, centimeter, and the intrinsic carrier density at this time is 6.5 x 10 an'', which is the maximum value of resistivity that has been realized. is about 20 km, ohm,
centimeter, and the practical resistivity is about 5 kg, ohm, centimeter. The most common method for making PIN junctions using silicon with a resistivity of 5 kg, ohm, or sennamometer is the impurity diffusion method.

An impurity imparting one conductivity type is diffused from one main surface of a high resistivity silicon substrate to a depth that provides a final thickness that facilitates practical handling, for example, about 50 to 100 microns.

Then, the high resistivity side is polished to the desired thickness.
After mirror-finishing so that no polishing layer remains, a PIN structure is formed by diffusing impurities that provide a conductivity type opposite to the impurities beyond the main surface side. The well-known metal type electrode is then processed to form a PIN junction diode having the required breakdown voltage.

The method of forming another PIN structure is as follows. Extremely resistive e.g. 10/1000
A vapor phase epitaxial growth technique is used to deposit an epitaxial layer of the highest possible resistivity to the desired thickness on one major surface of a ~1/1000 ohm cm silicon substrate, and then this epitaxial layer is This method forms a PIN structure by diffusing impurities of a conductivity type opposite to that of the substrate from the grown second main surface.

Another method is to use a vapor phase epitaxial growth technique to grow arsenic atoms as an impurity element on a Si substrate with a high resistivity of about 5 kg, ohm, or cm.
150 N-type epitaxial layers containing about ax or more
The high resistivity silicon substrate is deposited on the order of microns, and then the high resistivity silicon substrate is removed by polishing to the desired thickness, and after the polishing layer is removed and a mirror finish is applied, a conductivity type opposite to that of the epitaxial layer, that is, P type, is diffused to form a PIN. This is a method of forming a bond.

The present invention has been made to overcome the drawbacks of the various methods of forming PIN junctions described above, and the drawbacks of the conventional methods will be explained in detail below with reference to the drawings.

First, the drawbacks of PIN junctions formed by the diffusion method will be explained. Since the thickness of the high resistivity layer in PIN junctions used in high frequency ranges is as thin as approximately 5 to 50 μ, impurity diffusion of at least one conductivity type is required in order to ensure ease of assembly of PIN diodes (see Figure 1). As shown in FIG. 3, for example, the N-type diffusion layer is formed by deep diffusion of about 100 μm, and then the opposite conductivity type is diffused relatively shallowly.

In this arrangement, the region of the high resistivity layer 1 is controlled with limited precision. Also, the resistivity of the high resistivity layer can vary to any desired height within the available range.

However, the PIN die made by this method has the following serious drawbacks. In other words, the semiconductor has resistivity ρ and E
,ε. (here, ``ha'' means the relative permittivity of the whole car, and ε means the permittivity of vacuum), so it has more resistive properties in the dielectric dispersion frequency 1 region peculiar to the material. It exhibits more dielectric-like properties in the region of the dielectric fatigue number higher than fd.

Therefore, when the impurity diffuses deeply through thermal diffusion and shapes the PIN junction, as shown in Figure 1, the impurity distribution in both the P-type conduction region and the N-type conduction region gradually changes, so that the resistivity ρ increases.
It also gradually changes spatially and has properties as a function of position. This means that the dielectric dispersion frequency is a function of location, and the junction capacitance of the PIN junction has frequency dependence depending on the frequency used, and impedance matching is particularly important in the microwave region. However, since the diode impedance exhibits frequency dependence, it has the disadvantage that the usable frequency band is narrowed.

Next, a high resistivity epitaxial layer is grown and deposited on a low resistivity substrate, and then an impurity having a conductivity type opposite to that of the substrate is diffused from the surface opposite to the substrate to form a PIN junction. Describe the shortcomings. First, as shown in Figure 2, the resistivity achieved in the gas phase of the high resistivity layer is on the order of 1 kilometer, ohm, or centimeter, and the PIN
As for bonding, the necessary and sufficient values have been achieved.

However, achieving this requires advanced technology, and the yield rate is extremely low because the reproducibility is poor and the resistivity easily fluctuates by several times more. It is almost impossible to receive a stable supply.

A more serious drawback is that impurities of the same conductivity type as the substrate are introduced in a distributed manner into the high resistivity layer, resulting in a distribution that causes dielectric dispersion, although less than in the case of deep diffusion. This is a phenomenon known as oxidation, and is a problem that almost always accompanies high-resistance vapor phase growth. Therefore, the PIN junction formed by this method also has the disadvantage that the usable frequency band is narrowed and the Q value tends to decrease, as in the case of the PIN junction formed by deep diffusion.

Furthermore, a vapor phase growth layer with high impurity density, that is, extremely low resistance, is deposited thickly on the high and low efficiency substrate, and the high resistivity substrate is polished to the required thickness and mirror-finished, and then the vapor phase growth and opposite conductivity type impurities are reversed. Disadvantages of PIN junctions formed by diffusion from the surface will be described. In this case, as shown in FIG. 3, a high resistivity substrate can be selected and used prior to vapor phase growth.

Moreover, due to rapid progress in the production method of SL single crystals in recent years, the residual impurity density has decreased from 1011/am' to 1012 dl1.
High purity such as 3 can be achieved relatively easily. On the other hand, if such high-purity SL is irradiated with fast neutrons, some of the Si atoms undergo nuclear conversion and become P.
Because it converts into atoms, it can pass through single crystal substrates that have an extremely uniform impurity distribution, and it has already come into widespread use in the manufacture of high-voltage rectifiers. Therefore, when forming a low-resistivity layer on a high-resistivity substrate, the uniformity and reproducibility of the impurity density of the high-resistivity layer is lower than when forming a high-resistivity layer on a low-resistivity substrate by vapor phase growth. is greatly improved. Further, in this case, no autodoping effect occurs, and only a slight amount of impurity seeps out due to outward diffusion, resulting in the best PIN junction in terms of performance. However, it can be pointed out that this method has two major drawbacks in terms of manufacturing technology. First of all, the impurity density of the high resistivity layer is on the order of 10''/cc, and the impurity density of the low resistivity layer grown by vapor phase growth is 1-0'' to 1021/cc, which is a large difference. A large strain occurs between the two layers as shown in FIG. For this reason, when attempting to polish the substrate to a required thickness, the thickness of each layer becomes uneven as shown in FIG. 5, resulting in variations in the performance of the PIN bond and an extremely low yield. In addition, when attempting to thickly deposit a vapor-grown layer with high impurity density, the surface of the grown layer tends to become uneven according to the crystal habit, and defects such as voids, protrusions, pins, and lamids are likely to occur. If arsenic (this is the most commonly used impurity that increases electrical conductivity) is used as a dopant for the purpose of growth, there is a problem in processing the toxic arsenic compound emitted during growth of 100 to 150 microns, and it is difficult to handle such thick epitaxy. The situation is such that there are virtually no suppliers of crystals with Al-grown layers.

[Specific measures to solve the problem]

As a result of intensive research into specific means for solving the above-mentioned problem, the present inventors determined that the main part of the solvent in which the raw material solute Si should be dissolved was aluminum, and the remaining part was gallium, boron, and tin or germanium. The present invention was completed based on the finding that the above-mentioned problems could be solved by using a solution containing the above-mentioned components, and a reliable liquid phase growth layer could be obtained.

[Effect]

The solvent used in the liquid phase growth method of SL according to the present invention can increase the solubility of Si and obtain a thick growth layer at a relatively low temperature by making the main portion of the solvent aluminum. In order to increase the solid solubility, boron needs to be included, and the inclusion of aluminum and boron prevents the reduction of the average lattice constant of Si with tin or germanium, and gallium prevents the reduction of the average lattice constant of Si. This is to prevent harmful effects.・ [Example] First, it is desirable to use a high resistivity Si substrate and perform epitaxial growth at a low temperature in order to form an impurity distribution as steep as possible. methods such as epitaxy and molecular beam epitaxy. However, considering the subsequent steps, the growth thickness is 100~
150 microns is desirable, so molecular beam epitaxy is not suitable, and liquid phase epitaxial growth is optimal.Aluminum is a suitable solvent metal because the solubility of 6Si is high enough to obtain a thick growth layer at a relatively low temperature. You can choose. According to the literature, the solubility of Si in Al is about 20 atomic percent at 700°C, about 27 atomic percent at 800°C, about 36 atomic percent at 900°C, and about 44 atomic percent at 1000°C. This indicates that it is a suitable solvent for producing sufficiently thick growths. However, the solid solubility of aluminum in Si is about 2X10"/cc at maximum, which is about two orders of magnitude lower than that of arsenic or phosphorus. Therefore, when growing Si using A1 as a solvent, it is possible to To increase the density, it is necessary to add a third impurity.The P-type impurity with the highest solid solubility in Si is boron.This boron has a solid solubility about 25 times higher than that in aluminum. It has for Si.

Therefore, a very small amount (5 at.%) is added to aluminum as a solvent.
(Below) Performing liquid phase epitaxial growth of SL by adding boron is extremely effective in increasing the P-type impurity concentration in the growth layer.

However, it is already known that if a large amount of boron or aluminum is incorporated into silicon, it has the effect of reducing the average lattice constant of SL by 71%. Therefore, if liquid phase growth of silicon is performed using boron-doped aluminum as a solvent, it is clear that the grown layer will have a smaller lattice constant than high-resistance silicon, so the grown wafer will shrink on the grown layer side and cause warpage. . This is exactly the same drawback that appears when vapor phase growth containing a large amount of impurities is performed on a high-resistance substrate as described above.The purpose of the present invention is to overcome this drawback by It is sufficient to deposit a high concentration growth layer with a constant constant. To accomplish this, a fourth metal may be added, but the fourth metal must be one that increases the lattice constant in silicon. Therefore, group Ⅰ metals such as In and TQ have been considered as possibilities, but none of them are usable. In is S
It has been experimentally shown that when alloyed with L, it exhibits N-type conductivity. The reason is unknown until now. Moreover, even if the level of In in Si shows P, it is 0.16av
Because of the depth, it has an unfavorable effect on temperature characteristics. Further, TQ is extremely toxic as a metal and cannot be used. On the other hand, the use of group (I) elements to alleviate lattice strain is excluded because it goes against the purpose of increasing the conductivity of P-type conductivity. Therefore, the fourth additive silver metal should be selected from Group I elements. Both tin and germanium are suitable. The solid solubility of tin in silicon exceeds that of aluminum, with a maximum of approximately 5.5
10"/ec, and Ge can form a continuous alloy with silicon. Therefore, tin or germanium is suitable as the fourth additive metal to alleviate the decrease in the lattice constant caused by the addition of group Ⅰ elements. It is.

Furthermore, although the growth layer obtained by liquid phase growth according to the above method has a lattice constant that is relatively matched to that of the high resistivity substrate, in reality it is necessary to further add a fifth metal. That is A
No. 1 becomes a solid at a melting point of 660° C. or less, and although the eutectic temperature is lowered by adding metals up to the fourth, the substrate and growth layer are solid as well, and their expansion coefficient has a value significantly different from that of metals. Therefore, if the substrate solidifies while still in contact with the solvent, the substrate and the growth layer will be damaged due to the difference in expansion coefficients.To avoid this, lower the melting point and at the same time make the alloy with A1 an extremely mechanically brittle material It is sufficient to add a metal such that the solvent destroys it during solidification. The most suitable metal of this type is gallium. If Ga is mixed with aluminum, the melting point will decrease with the amount of gallium, and the alloy will become extremely brittle when solidified. Also, as a side effect, Ga −
The A1 alloy reacts very well with acids and bases, facilitating removal of solvent metals after growth. The appropriate amount for this Ga-Al alloy to have such an effect is GaxAl&-
It was found that X (0≦X≦0.5).

In addition, the liquid phase growth method is a growth method that is closest to thermal equilibrium compared to other growth methods, so in this way, A1-Ga alloy is used as a solvent, boron is added to increase the carrier concentration, and Sn or Ge is added to the lattice. Even if complex growth is performed using a one-component metal solution with silicon added as a constant compensator and silicon as a solute, the growth will automatically produce the lowest energy state, resulting in the desired epitaxial growth. It can move through the growth layer relatively easily.

According to experiments, Al: Ga=99:1 (Al-Ga): Sn=99:1 ((Al
-Ga) -8n) : B =99.1 : 0.1
After saturated Si was dissolved in the above alloy at 900° C. in an H8 envelope, it was welded to a high resistivity substrate and slowly cooled to obtain a grown layer of about 150 micrometers, but almost no warping occurred.

The high resistivity substrate side of this wafer is coated to a desired thickness, e.g.
Diodes obtained by polishing to a mirror finish of 5 m to 50 m and diffusing N-type impurities have a yield of 5 m compared to conventional ones.
It has doubled.

In addition, in the above example, by adding gallium, A
1-Ga alloy is formed, but it goes without saying that an Al-Ga alloy may be used from the beginning. In short, it is sufficient that the solvent mainly contains aluminum and the remainder contains gallium, boron, and tin or germanium.

〔effect〕

As is clear from the above explanation, one S according to the present invention
According to the liquid phase growth method of L, a reliable liquid phase growth layer can be obtained.

[Brief explanation of the drawing]

Figures 1 to 3 are graphs showing impurity density distributions of semiconductor substrates formed by conventional liquid phase growth, respectively, and Figures 4 and 5 are side views showing defects of substrates formed by conventional liquid phase growth. be.

Claims (1)

[Claims] A method for liquid phase growth of Si, characterized in that the main part of the solvent in which Si as a raw solute is to be dissolved is aluminum, and the remainder is a solution containing gallium, boron, and tin or germanium.