JPS6235710A - Signal level decision circuit - Google Patents

Abstract

PURPOSE:To set the level of a reference voltage properly for each pulse signal even when different pulse signals differ in DC level by providing plural sample holding means and using the output signal of a sample holding means in a sampling operation period as the reference signal for an input pulse signal inputted in the sampling operation period. CONSTITUTION:The output voltage (e) of an arithmetic circuit 5 is supplied to sample holding circuits 6 and 7. The sample holding circuit 6 is switched between operation in which the input voltage (e) is sampled and outputted as it is and operation in which the voltage is held and outputted as it is with a control signal f1 from a flag detecting circuit 10. The sample holding circuit 7 is also switched between operation in which the input signal (e) is sample and outputted as it is and operation in which the voltage is held and outputted similarly with a control signal f2 from the flag detection circuit 10. The reference voltage whose level is to be compared with plural signals which differ in DC level and are supplied repeatedly in order is generated according to the DC levels of the respective signals and holding operation is carried out every time the reference voltage is generated.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a signal suitable for use in waveform shaping of a plurality of pulse signals that have different DC levels and are repeatedly supplied in sequence, such as reproduction signals of optical discs. The present invention relates to a level determination device.

[Background of the invention]

By irradiating an optical disk with a laser beam whose intensity is modulated by a digital data signal, a digital signal is recorded by changing the reflectance of the optical disk according to the intensity of the laser beam, and a laser beam of a constant intensity is applied to the optical disk. In optical recording and reproducing, which reproduces the digital data signal by emitting light and detecting changes in the amount of reflected light, high-density recording of digital data signals is possible, but this reduces the number of recorded bits. The diameter becomes close to the diameter of the reproduction laser beam. For this reason, the digital data signal during recording consists of a series of rectangular pulse trains of logic, ``1'', and oI'' levels, whereas the pulses reproduced from the recording pits of the above diameter are The rising and falling edges are blunted and the waveform approaches a sine wave.

Therefore, the reproduced signal is shaped by a waveform shaping circuit so that all pulses have a rectangular waveform.

In this waveform shaping method, the level of the reproduced signal is compared with the reference voltage of the bell based on a predetermined standard, and when the level of the reproduced signal is higher than this reference level, a logic "1" signal is output, and when it is lower than the reference level, a logic "1" signal is output. It outputs a logic ``0'' signal, so that each pulse of the reproduced signal has a rectangular waveform.

The value of this reference level is the @ of the output signal of the waveform shaping circuit.
It is necessary to set the time width of ``1'', ON so that it has the same value or the same ratio as the time width of ``1'', @O'' of the digital data signal during recording.

As is well known, the easiest way to achieve this is to
, a method using a level comparison circuit, one input of this level comparison circuit is a reproduction signal, the other input is a fixed nine DC voltage, and the level of this DC voltage is adjusted to p4 so as to satisfy the above-mentioned optimum conditions. It is. However, if the DC level of the signal fluctuates due to heat generated in the photodiode that detects the reflected light of the reproduced laser beam or the DC amplifier that amplifies the minute output signal obtained from this, or due to the material of the optical disc, the DC level of the reproduced signal When the level fluctuates, the above method cannot perform waveform shaping that satisfies the above optimum conditions.

The ninth way to solve this problem is to detect the maximum and minimum values (hereinafter collectively referred to as peak values) of the reproduced signal, and then calculate the voltage value of a predetermined ratio of these values (ideally, the intermediate value).
A method has been proposed to determine this and use this as the reference level. According to this, even if the DC level of the reproduced signal fluctuates,
Since the reference level also changes accordingly, it should be possible to always shape the waveform of the reproduced signal so as to satisfy the above-mentioned optimum conditions.

However, for this purpose, the problem is how to set the responsiveness of the peak value detection device.

In other words, if the response is made faster, it is possible to cope with fast-cycle DC level fluctuations, but it also responds to level fluctuations in the reproduced signal caused by K, such as scratches on the optical disk, and the level fluctuations required for dropout compensation later become unavoidable. Not only this, but also the reference level may fluctuate until it returns to the original correct reference level after this level fluctuation period ends, making it impossible to read data during this period.

On the other hand, if the response is slow, the reference level is fixed and close to the actual level, and it does not respond sufficiently to fluctuations in the DC level, and the time widths of '1'' and @0'' are significantly different from those at the time of recording. In the worst case, pulses may be missing, which may lead to reading errors.

As described above, as a conventional technique for obtaining a reference level from Regeneration No. 4, for example, Japanese Patent Application Laid-Open No. 57-10583
This is disclosed in Japanese Patent No. 0, and describes the responsiveness to a specific rotational speed of an optical disc.

Furthermore, in this patent publication, each track is divided into a plurality of areas (i.e., sectors), and each sector is further divided into a preformat section and an additional write section, and address signals, etc. are sent to the preformat section. An example of application to an optical disk with a write-once section and a groove will be described, in which a bit string (pre-pit) representing the present invention is recorded and information data is recorded on the write-once section. In such an optical disc, pre-pits are formed at the same time as the disc is manufactured, and when the optical disc is used, information data is recorded in the write-once part of a desired sector of a desired track using data in the preformat part.

When obtaining a playback signal from such an optical disc, the signal obtained from the preformat section and the signal obtained from the write-once section often have significantly different peak values, so the pre-format section and the write-once section are often played back in succession. Therefore, it is necessary to quickly and significantly change the reference level when playback moves from the preformat section to the additional write section, and vice versa. In the conventional technology disclosed in the above-mentioned patent publication, for this purpose, it is detected that the preformat section is to be reproduced from the reproduction signal, and when the reproduction moves from the preformat section to the postscript section, the passband of the low-pass filter is By widening the reference level, the responsiveness of the reference level setting circuit is improved, so that the reference level quickly responds to the peak value of the reproduced signal obtained from the additional writing section.

However, information data is not recorded in all sectors of all tracks, and in each track, information data is not recorded in each sector in the order in which they are arranged. Information data is recorded in selected sectors of each selected track. For this reason, K.
In each track, there are sectors in which information data is recorded, and there are sectors in which information data is not recorded, and these sectors are generally arranged irregularly.

In a sector where no information data is recorded, the peak value of the reproduced signal obtained from the preformat section and the signal obtained from the additional section where nothing is recorded (in this case, no signal is obtained, but , which can be seen as obtaining a signal at the minimum level) is significantly different from the peak value.

Therefore, in the above conventional technology, the preformat section,
Even if the response speed of the reference level setting circuit is increased by 9 when playback is transferred between the write sections, it is effective for sectors where information data is recorded, but not when information data is recorded in the write section. If not, the preformat section,
When the playback moves between additional recording sections, it is necessary to change the reference level to a large extent, which results in a very long settling time. This is not a problem when playback moves from the preformat section to the postscript section because no information data is recorded in this postscript section, but when the playback moves from the postscript section where no information data is recorded to the preformat section of the next sector. When the playback shifts, the reference level during that time is not correct due to the long settling time. For this reason, the reproduced signal from the preformat section will not be waveform-shaped correctly.

[Purpose of the invention]

An object of the present invention is to solve the problems of the prior art, and to provide a signal level determination method that makes it possible to appropriately set the reference voltage level for each pulse signal even if the DC level differs greatly between different pulse signals. We are in the process of providing equipment.

[Summary of the invention]

In order to achieve this object, the present invention forms a voltage at an appropriate level for each pulse signal according to the peak value of each pulse signal, uses this voltage as a reference voltage for the corresponding pulse signal, and , sample and hold the voltage, and hold the held voltage.

The present invention is characterized in that the reference voltage is used when the voltage at the appropriate level cannot be obtained from the pulse signal.

[Embodiments of the invention]

Hereinafter, an actual example of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a signal level determination device according to the present invention, in which 1 is a preamplifier, 2 is a 46-waveform circuit, 3 is a comparison circuit, 4 is a peak value detection circuit, and 5 is an arithmetic circuit. , 6 and 7 are sample and hold circuits, 8 is a switching circuit, 9 is a belly button detection circuit, and 10 is a flag detection circuit.

In the same figure, a playback signal with minute amplitude detected by an optical disk (not shown) and a photodiode (not shown) is amplified to a predetermined amplitude by a preamplifier 1, and then subjected to waveform distortion by a waveform equalization circuit 2. Processing such as removal of The output signal a of the waveform equivalent circuit 2 is supplied to the comparator circuit 3, and is supplied with a reference level voltage (hereinafter referred to as reference voltage) from the switching circuit 8.

The level is compared with b. For example, the comparator circuit 3 outputs logic "1" during a period in which the level of the signal a is higher than the reference voltage.
, and in the opposite period, it outputs a voltage of logic 1. The output 1 = a = c of the Hiyoko Ayu 3 is a waveform-shaped digital data signal, and is demodulated (not shown). The signal is supplied to a circuit, and the modulation performed during recording is demodulated to obtain original data.

Next, the means for generating the reference voltage will be explained.

The output signal a of the shaping equalization circuit 2 is also supplied to the peak value detection circuit 4. Here, the peak value refers to the maximum value and minimum value of a signal, and the peak value detection circuit 4 detects and outputs the maximum value amax and minimum value dmin from the signal a. The arithmetic circuit 5 calculates these maximum values dtrssx.

By performing addition and division processing on the minimum value dmln, a voltage e at a predetermined level between the maximum value dmax and the minimum value dmln is formed. Such arithmetic processing by the arithmetic circuit 5 is always the same; therefore, the level of the voltage e obtained is:
When the peak value of signal a changes, it changes accordingly. However, for any peak value, the maximum value dma
x, the ratio of the difference between the predetermined level and the minimum value dmln to the difference between the minimum value dmln is made constant. Ideally, this predetermined level should be set to an intermediate value between the maximum value dmax and the minimum value dmin, but since some waveform distortion remains in the output signal a of the waveform equalization circuit 2,
By slightly shifting the value from this intermediate value, the comparator circuit 3 obtains a digital data signal C whose waveform is shaped so as to better satisfy the above-mentioned optimal conditions.

The output voltage e of the arithmetic circuit 5 is determined by the sample hold circuit 6.7.
is supplied to The sample-and-hold circuit 6 is switched between an operation of sampling the input voltage e and outputting it as is, and an operation of holding and outputting it, according to a control signal f from the flag detection circuit 10. Sample hold circuit 7
The same applies to the control signal f from the flag detection circuit 10.
, it is possible to switch between an operation in which the input voltage e is sampled and output as is, and an operation in which the input voltage e is held and output.

The flag detection circuit 10 is supplied with the digital data signal C output from the comparator circuit 3, and receives the digital data signal C that is reproduced from the preformat part (hereinafter referred to as preformat part signal) of each sector of the optical disc and the part reproduced from the postscript part. The sample and hold circuit 6 detects the sample and hold circuit 6 during the preformat section signal period. There is a control (such as a system that allows the operation to operate and then holds the operation during other periods).
) Outputs the signal f, and also includes a sample hold circuit 7
A control signal f is output that causes sampling operation to occur during the write-once signal period, and causes holding operation to occur during other periods.

The output voltage g1+g* of the sample and hold circuits 6 and 7 is selected by the switching circuit 8 and supplied to the comparator circuit 3 as a reference voltage. The switching circuit 8 is controlled by the control signal output from the ladder detection circuit 9, and when the signal a supplied to the comparator 3 is the preformat section signal, the sample hold circuit 6 is in the sampling operation state.
The output voltage gl of the sample-and-hold circuit 7 in the sampling state is selected when this is the write-once signal. As a result, in the comparator circuit 3, the reference voltage for level comparison with the preformat part signal is the voltage e generated from the preformat part signal in the arithmetic circuit 5, and the reference voltage for level comparison with the postscript part signal is is the voltage e formed from this additional writing section signal. However, if the signal a supplied to the comparator circuit 3 is a write-on signal obtained from a write-on part in which no information data is recorded, the sample-and-hold circuit 7 is held in the hold operation state, and the previous write-on part is A voltage e obtained from the signal by the arithmetic circuit 5 is supplied to the comparator circuit 3 as a reference voltage.

A flag is used to determine whether the write-once signal supplied to the comparison circuit 3 is reproduced from the write-once section where information data is recorded or from the write-once section where information data is not recorded. This is done by the flag of the digital data signal C in the detection circuit 10.

Next, the operations of the header detection circuit 9 and the flag detection circuit 10 will be explained in more detail using a specific example of the output signal a of the waveform equalization circuit 2.

FIG. 2 is a schematic diagram showing a specific example of a sector configuration on an optical disc.

In the figure, each sector includes a preformat section 50 and an additional writing section 51, as described above. The preformat section 50 records a sector mark 50a with a specific bit pattern representing the beginning of a sector, and an address signal 50b such as a track number or sector number, and further includes:
Gap 50c representing the end of preformat section 50
is provided. The additional recording section 51 is an area where the user can record desired information data later, and the information data 51b
When a flag 51a is recorded, a flag 51a is also recorded at the beginning. When the information data 51b is not recorded, the flag 51'a is also not recorded, and therefore,
Information data 5 is stored in the parallel writing section 51 depending on the presence or absence of the flag 51a.
1b is recorded.

In the reproduced signal a for this sector, as shown in FIG. 3, the preformat part signal a.

Generally, the peak values of the write section signal a and the additional recording section signal a are significantly different, so if their reference levels b, , b are also significantly different, it is necessary to break them. However, there is not much difference in the reference level between the preformat part signals of each sector, and there is also not much difference in the reference level between the write-once parts signals reproduced from the write-once part in which information data is recorded. However, the reference level is significantly different between the write-once signal reproduced from the write-once portion where information data is recorded and the write-once signal reproduced from the write-once portion where information data is not recorded.

The header detection circuit 9 detects sector marks and gaps from the digital data signal Cn4 and the preformat part signal a, and outputs a control signal that is 1'' only during the period of the preformat part signal a, as shown in FIG. The switching circuit 8 selects the output voltage gl of the sample and hold circuit 6 during the period when the control signal is 11'', and selects the output voltage g2 of the sample and hold circuit 7 during the period when the control signal is 0. The circuit 9 sends the detected sector mark and gap to the flag detection circuit 10 as a signal i.

The flag detection circuit 10 outputs a control signal f which is "O" only during the period from the sector mark to the gap, as shown in FIG. 3, in response to the signal i also sent to the header detection circuit 9. The sample hold circuit 6 receives this control signal f
1 is in the sampling operation state i during the period of OI', and is "1"
The period is a hold operation period in which the level of the signal e at the end of the "0" period is held. In this case, the control signal f
The point at which 1 is reversed from 0'' to 1'' is slightly earlier. This is because if these points of time are made to coincide, a hold will be made at the level fluctuation portion of the output signal e of the arithmetic circuit 5 when moving to the preformat section signal a and the additional write section signal a.

Due to this operation, the sample-and-hold circuit 6 holds the reference voltage formed from the immediately preceding preformat signal a during the period when the write-once signal a is supplied to the comparator circuit 3. Next preformat part signal a,
is supplied to the comparator circuit 3, at the beginning of the voltage e supplied to the sample and hold circuit 6, the level is b.
1, so it is not at an appropriate level during this time, and for this reason, the falling edge of the control signal f is delayed by this period than the rising edge of the control signal f. This results in
For each preformat signal a1, an appropriate reference voltage is supplied to the comparator 3 from the beginning thereof.

Further, the flag detection circuit 10 receives the digital data signal C
The flag is detected from , and as shown in FIG. 3, a limit signal f is generated which is "1" during the period from the beginning of the preformat section signal a1 to the flag. The sample hold circuit 7 receives the signal e immediately before this control signal f1zo1'' period.
It is in a hold operation state to hold the level of 1l.
It is in the sampling operation state for lOj1 period. When the additional recording section signal a2 is reproduced from the additional recording section in which information data is recorded, the flag detection circuit 10 detects the flag and thereby sets the control signal f to '0''. When the signal a1 is supplied to the comparator circuit 3, the sample hold circuit 7 enters a sampling operation state, and the voltage C supplied thereto is directly supplied to the comparator circuit 3 as a reference voltage.

However, the additional write section signal a is supplied to the comparator circuit 3.

is not reproduced from a write-once section where no information data is recorded, the flag detection circuit IO cannot detect the flag from the digital data signal C. For this reason, the control signal f, is held at 1'' and the sample-and-hold circuit 7 continues its hold operation, and the voltage g, previously detected by the arithmetic circuit 5 and held in the sample-and-hold circuit 7, is It is supplied to the comparator circuit 3 as a reference voltage.

In this way, since the voltage is held in the sample and hold circuit 7, even if the postscript signal a is reproduced from either postscript, the postscript signal a is supplied to the comparator circuit 3. Sometimes, a reference voltage is always provided at the appropriate level.

Further, the time point at which the control signal f is inverted from 91m to '0'' is delayed from the same inversion point in the control signal f,
Set after the end of the flag. As a result, during the flag period of the postscript signal a, the reference voltage supplied to the comparator circuit 3 is the voltage previously sampled and held by the sample-and-hold circuit 7, but this voltage is not an appropriate voltage. be.

Also, during this flag period, the preformat section signal a
, and the postscript signal a, the level of the output voltage e of the arithmetic circuit 5 fluctuates. Therefore, if the level of this output voltage e is not stabilized even after the flag period, an appropriate voltage that has been sampled and held before the sample hold circuit 7 is used instead of this output voltage e until it becomes stable. By using it as a reference voltage, not only can the flag detection circuit 10 reliably detect the presence or absence of a flag, but also the reference voltage for the information data 51b can be appropriately set from the beginning.

As described above, in this embodiment, the preformat section signal a,
It is possible to obtain reference voltages at appropriate levels for each of the write section signal a and the write section signal a.

FIG. 4 is a block diagram showing another embodiment of the signal level determination device according to the present invention, in which 3' is a comparison circuit, 8' is a switching circuit, and parts corresponding to those in FIG. 1 are given the same reference numerals. to omit duplicate explanations.

In this embodiment, two comparison circuits 3 and 3' are provided, each of which is supplied with the output signal a of the waveform equalization circuit 2, and the output voltage g1 of the sample and hold circuit 6 is supplied to the comparison circuit 3. The output voltage g of the sample and hold circuit 7 is supplied to the terminals 3' as reference voltages, and the output signal c1mct of the comparator circuits 3 and 3' is selected by the switching circuit 8' controlled by the control signal 3', and the digital data signal It was designed to obtain C.

For this purpose, the switching circuit 8' outputs the output signal C of the comparator circuit 3.
A preformat part signal is selected from I, and the comparison circuit 3'
The additional write unit signal is selected from the output signal C1 of.

In the embodiment shown in FIG. 1, an analog switch for switching analog signals is used as the switching circuit 8, but in the embodiment shown in FIG. 4, the switching circuit 8' is for switching digital signals. Since a digital switch is used for switching, the switching speed can be increased.

Note that the present invention is applicable not only to a reproduction signal from an optical disc but also to a case where a plurality of pulse signals are repeatedly supplied in order.

〔Effect of the invention〕

As explained above, according to one aspect of the present invention, the reference voltage whose level is compared with a plurality of signals having different DC levels and which are repeatedly supplied in order is formed according to the If current level of each of the signals, and Since the reference voltage is held each time it is formed for each signal, the reference voltage is set to an appropriate level for each signal.
Even if there is a temporal no-signal period, the level of the reference voltage is maintained at an appropriate level not only during the no-signal period but also after the no-signal period has passed, and from the beginning of each signal repetition. Correct level comparison with the reference voltage becomes possible, the problems of the prior art described above can be solved, and a signal level determination device with excellent functionality can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a signal level determination device according to the present invention, FIG. 2 is a schematic diagram showing a specific example of a sector configuration in an optical disc, and FIG. 3 is a block diagram showing a specific example of a sector configuration of an optical disc. FIG. 4 is a timing chart showing the operation of the embodiment shown in FIG. 1, and FIG. 4 is a block diagram showing another embodiment of the signal level determining device according to the present invention. 3.3'...Comparison circuit, 4...Peak value detection circuit. 5... Arithmetic circuit, 6.7... Sample hold circuit, 8.8'... Switching circuit, 9...
・・・Header detection circuit diagram I Figure 2

Claims (3)

[Claims] (1) A plurality of types of input pulse signals and a reference voltage, which have different DC levels and are repeatedly input in order, are supplied to a level comparison means, and the level relationship between the input pulse signal and the reference voltage is determined. In the signal level determination device, a peak value detecting means for sequentially detecting a maximum value and a minimum value of the input pulse signal, and an arithmetic means for forming a voltage at a predetermined level determined by the maximum value and the minimum value. and,
a plurality of sample and hold means for sampling and holding the voltage at the predetermined level at the input timing of the input pulse signal; a selection means for selecting the reference voltage of an input pulse signal, and the signal level determination is configured such that the level of the reference voltage can be set for each input pulse signal according to the DC level. Device. (2) In claim (1), the level comparison means is a single comparison circuit to which both the input pulse signals are supplied, and the selection means performs a sampling operation when the input pulse signal is input. A signal level determination device characterized in that it is a switching circuit that selects an output voltage of the sampling means in a period. (3) In claim (1), the level comparison means includes a plurality of comparison circuits to which the input pulse signals are respectively supplied and to which different output voltages of the sample and hold means are supplied as reference voltages. A signal level determination device, wherein the selection means is a switching circuit that selects an output signal of the comparison circuit to which the output voltage of the sample and hold means during a sampling operation period is supplied.