JPS6235305B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an image signal conversion method for reducing the number of black pixels in a binary pattern in a lattice-like image area of n rows and m columns.

(Prior art and its problems) Conventional image encoding systems are based on encoding a one-dimensional array of black pixels based on line scanning.
For this reason, many compression methods for encoded information utilize one-dimensional correlation of black pixel arrangement, such as run-length encoding, and even when attempting to utilize two-dimensional correlation, multiple lines must be processed at once. Therefore, it cannot be said that the original two-dimensional correlation of the target image is effectively utilized.

(Object of the Invention) In order to solve this drawback of the prior art, the present invention provides an image signal conversion method that can reduce the number of black pixels representing the original pattern prior to encoding. The feature is that the correlation in the column direction is also extracted and used at the same time as the correlation in the row direction.

(Principle and Configuration of the Invention) The present invention will be described in detail below with reference to the drawings.

First, the principle of the present invention will be explained.

In the present invention, as shown in FIG. 1, an (n+1)th row and (m+1)th column are further added to the grid-like object area _A0 of n rows and m columns, thereby creating an expanded area A _e consisting of (n+1) and (m+1) sections. prepare.

Figure 2a shows an example of the black pixel arrangement appearing in the i-th row in the original (n, m) area _A0 , and Figure 2b shows how this is represented in the extended area _Ae . . In FIG. 2a, the X marks indicate black pixels. In Figure 2b, at the same time as marking the m+1th column with an
The black pixels in rows and columns 1 to m are erased, and X marks are placed where there are no black pixels. The X mark added by the above conversion is also treated as a black pixel. Figure 2b
It is possible to reproduce Fig. 2a from the original area A ₀
The i-th row pattern represented by four black pixels will be represented by three black pixels in the extended area A _e .

FIGS. 3a and 3b are examples in which the same processing as in FIG. 2 is performed on the j-th column, and four black pixels are effectively reduced to two.

FIG. 4b shows the conversion from the pattern of FIG. 4a when the section (lower right corner) of the (n+1)th row and (m+1)th column is marked with an X. At this time, all the black pixels in the areas n and m are erased, and at the same time an X mark is placed on the section where there are no black pixels.

The principle of the present invention is that the number of black pixels of the first pattern obtained as a result of the conversion processing (first processing) explained in FIGS. 2a, b and 3a, b, and the number of black pixels in FIGS.
The number of black pixels of the second pattern obtained as a result of the conversion process (second process) explained in section b is compared, and the conversion process result with fewer black pixels is used as an output signal. Here, in order to achieve this purpose, the conversion process (first process) shown in FIGS.
There is no order in the conversion process (second process) shown in FIG.

When performing transformations on both rows and columns, n, m
Figures 5 and 6 show how the original pattern within the region is changed. The original pattern can be recreated by retracing this process. In Figure 5a, a pattern consisting of nine black pixels first becomes two pixels in the second row as in Figure b, and then transforms in the second column to become one as in Figure c, resulting in a total of two pixels. This shows that it can be converted to black pixels. Further, in FIG. 6, a pattern consisting of 10 black pixels is represented by 3 black pixels. This is the same regardless of which matrix is used.

However, in general, for complex patterns, to decide which row or column to start with,
The difference in black pixels before and after conversion is calculated for each row and column in advance.

Figures 7a and 7b show examples of calculations in the row direction. a is the case of forward transformation, and b is the case of inverse transformation, and the difference in the number of black pixels is called the gain of transformation. A "+" sign in the gain indicates that the transform is valid, and a "-" sign indicates that the transform is not valid.

For a given pattern, when performing the first process described above with reference to Figures 2a, b and 3a, b, starting from the row or column with the highest gain, About “−”
The operation ends when the sign is indicated. A specific example is shown in FIG. Numbers written outside the area indicate gains in the row and column directions. At each stage, transform is performed on the row or column that shows the maximum gain circled. In Figure 8a, the third row first shows the maximum gain;
Perform the transformation on the third line to obtain b. As a result, the fifth
Column shows maximum gain. Perform the transformation on the fifth column and c
get. In c, all the gains have a "-" sign, which is the first pattern described above. Generally, the original pattern and the section of the (n+1)th row and (m+1)th column are placed with an X mark, and the n, m area A ₀
In the case of processing to obtain the second pattern as shown in FIGS. 4a and 4b, in which the entire conversion is performed, black pixels are independently reduced, the results of both are compared, and the one with fewer black pixels is selected.

Figure 9 shows a few special cases. FIG. 9a is an example in which no transformation is required, and b is an example in which the minimum expression is obtained by quadratic transformation. In addition, in a Chess board pattern like c, the number of black pixels generally ranges from [n ² /2] when n is an odd number to n-1, [n ² /
2] From +1 to n, and when n is an even number
It is reduced from n ² /2 to n.

(Embodiment) FIG. 10 shows a block diagram of an example of a circuit for reducing black pixels by the first process according to the present method.
a is a pattern storage matrix consisting of (n+1) and (m+1) binary storage elements, b and c are gain calculation circuits in the row and column directions, respectively, and are first memories that store the current number of black pixels; It consists of a second memory that stores the number of black pixels when it is inverted, and a subtraction circuit that calculates the difference between the contents of both memories. For example, d is a gain storage circuit such as a shift register, and e is a maximum gain detection circuit. For example, when d is a shift register, it has one memory cell and the contents of the memory cell are sequentially read while the contents of the shift register are cycled through. This circuit detects the maximum gain by replacing . Further, f is a control circuit that controls the states of the storage elements of the pattern storage matrix a. Although the details of the parts related to the input and output of the pattern have been omitted, it is possible to connect a required number of known circulating shift registers as described for d to each row or column of the pattern storage matrix a, and to circulate these registers. Either inputting or outputting parallel image information by directly coupling to the shift registers, or inputting or outputting serial image information through large capacity circulating shift registers which are all coupled to these circulating shift registers. This can be realized using a well-known configuration such as. The output may optionally be applied to an encoder and encoded as shown, for example, or further subjected to other transformations.

The operation of this embodiment will be explained below.

The patterns stored in the pattern storage matrix a are read out section by section in the row or column direction. As mentioned above, it is the same whether priority is given to the row direction or the column direction, but here, reading is performed in the row direction. First, the section (1, 1) is read out, followed by (1, 2.), (1, 3), ... (1, j),
...(1, m), (1, m+1) are read out in this order. This is performed in series or in parallel for the first to nth rows. The first memory in the gain calculation circuit b counts and stores the number of black pixels, and the second memory counts and stores the number of white pixels as black pixels when the pattern is reversed. In this way, after all sections of the row have been read, subtract the contents of the second memory from the contents of the first memory to obtain the gain;
This is stored in the corresponding row position of the gain storage circuit d.

The above operation is also performed for columns. As a result, the gains of each row and each column are stored in the gain storage circuit d.

The maximum gain detection circuit e detects the row or column that gives the maximum value while cycling through the contents of the gain storage circuit d. This means that if the maximum gain detection circuit e is a shift register, the row or column having the maximum gain can be easily detected by comparing the stored contents every time they are shifted and simultaneously counting the number of shifts. The row or column number found and the maximum gain value (or may just be a sign indicating whether the value is positive or negative)
is output to the control circuit f. The control circuit f identifies the sign of the maximum gain value, and if it is "-", determines that the pattern stored in the pattern storage matrix a is the optimal pattern, and outputs that pattern. An extreme example of this is the case in Figure 9a, where each row has 0 black pixels and (m+1) white pixels, giving {0-(m+1)}, and each column similarly has {0-(n+1) }give. If the maximum gain is "+", after converting the pixel in the row or column having the maximum value, repeat the above-mentioned counting operation for black and white pixels in each row and each column. Maximum gain detection circuit e
When the maximum gain value detected by becomes "-", the pattern stored in the pattern storage matrix a is determined to be optimal and is output.

The above are the basic operations, but the following additional operations are required for the unique patterns shown in FIGS. 9b and 9c.

For Figure 9b, the gain value in each row is (1-
m), the gain value of each column is (1-n), so the maximum gain detection circuit c determines whether all rows give (1-m) or all columns give (1-n). The information is determined and given to the control circuit f, and the control circuit f converts the (m×n) area of the pattern storage matrix a and writes and outputs x in the section (m+1, n+1). In addition, in the case of FIG. 9c, if the area (m×n) is m=n and m is an even number, the gains of each row and each column all give -1, so identify this and After converting the columns, you can proceed as usual. Furthermore, when m is an odd number, the gains of 0 and -2 appear mutually in the row and column directions, but 0
If it is treated as +, normal operation will suffice.

Although the specific circuit for executing the second process described with reference to FIGS. 4a and 4b is not shown, for example, the pattern shown in FIG. 4a stored in the pattern storage matrix a in FIG. By sequentially reading each column, inverting the state of each pixel using a NOT circuit, and rewriting, the black pixels in the m and n regions can be inverted.
Furthermore, the block black pixels in the (n+1)th row and (m+1)th column may be set in advance.

The number of black pixels of the second pattern obtained in this way is, for example, the number of black pixels of the first pattern in the gain calculation circuits b and c.
is obtained as the memory contents of .

Therefore, the number of black pixels in the first pattern and the number of black pixels in the second pattern obtained by providing such a circuit separately from the circuit in FIG. 10 or using only a portion of the circuit in FIG. The first pattern or the second pattern having a smaller number of black pixels can be selected as the output pattern by comparing the number of black pixels using a comparison circuit.

As described above, the present invention can reduce the number of black pixels representing a pattern by moving the pattern in areas n and m to extended areas (n+1) and (m+1). Note that whether the correlation in the row and column directions can be used effectively is also influenced by how n and m are selected. Generally, if n and m are small, the reduction rate will be small even if the correlation is strong, and
When n and m are set large, the black pixel distribution along a row or column is randomized and the correlation becomes weak.
n and m should be selected in relation to the characteristics specific to the target image; when targeting a large screen, the screen may be divided into n and m areas, or the entire screen may be divided into n x m partial areas. A conceivable method is to further divide the partial area including black pixels into n×m areas, and finally designate each black pixel.

(Effects of the Invention) As explained in detail above, the method of the present invention contributes to compressing the amount of encoded information as a preprocessing prior to encoding image information by reducing the number of black pixels expressing a pattern. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an original image area and an extended area used in the present invention, FIGS. 2 and 3 are diagrams for explaining respective transformations regarding rows and columns in the present invention, and FIG. 5a, b, c and 6 are diagrams showing specific examples of the conversion according to the present invention. FIGS. 7a, b and 8
9a, b, and c are diagrams for explaining gain calculation used in the present invention, FIGS. 9a, b, and c are diagrams showing examples of unique patterns, and FIG. 10 is a block diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1 Newly target the binary pattern in the m/n grid-like image area consisting of n rows and m columns, and
Add the m+1th column to prepare (n+1) and (m+1) expansion areas, and change the arrangement of the black pixel in the i-th row (1 inch) to the section in the i-th row and m+1th column at the same time by erasing the black pixel. A new black pixel is placed in the section where there is no black pixel in the i-th row, and
m) The operation of erasing the black pixel and simultaneously placing a new black pixel in the section of the j-th column of the n+1 row and the section where there is no black pixel in the j-th column is performed in the expanded area. means for first processing to obtain a first pattern in the expanded area while the number of pixels is expected to decrease;
A second pattern is obtained by placing a new black pixel in the section in the m+1 column of the row and in the section where there is no black pixel in the n, m area.
processing means, and the first pattern or the second pattern has a minimum number of black pixels in the expanded area.
An image signal conversion system configured to reduce the total number of black pixels representing the binary pattern by obtaining a pattern of 2 as an output pattern.