JPS623526A - Generating for circuit one-shot multivibrator pulse output signal - Google Patents

Abstract

PURPOSE:To simplify the circuit with only one time constant element by using a cycle by one time charge/discharge of a specific element after a trigger signal is inputted as a unit and generating an output signal of a one-shot multivibrator pulse circuit whose output is finished after a time being optional integral number of times of the said cycle. CONSTITUTION:A means 103 outputting a one-shot multivibrator pulse output signal consists of a NOR gate 11 and an inverter 12. An output of a D-F/F1 and an output of an inverter 9 are given to an input of the NOR gate 11 and its output connects to an output terminal OUT via the inverter 12. The one-shot multivibrator pulse signal starts outputting by the application of a trigger signal TRIG and completes the output by the end of charging of a time constant element 105 after a reset input signal is generated. In other word, the completion of the output of the one-shot multivibrator pulse output signal depends on the time for on charge/discharge and the number of times of repetition of charge/ discharge of a charge/discharge means 102 controlled by a control signal outputted from a control means 101 to which the counter output signal is fed back.

Description

Detailed Description of the Invention (Field of Industrial Application) This invention uses one input signal as a trigger to terminate output after a time determined by the charging and discharging of a time constant element of a set of resistors and capacitors. The present invention relates to a one-shot and pulse output signal generation circuit that outputs two pulses.

(Prior Art) Conventionally, this type of circuit has been used in the I10 circuit between a floppy disk, etc., and a signal processing processor in a computer system, and has been used in the Motorola CMOS data (MO
7-45 z-< of TOROLA 0MO8DATA)
There are already many examples, as described in -.

FIG. 3 shows an example of a one-shot pulse output signal generation circuit that is different but similar to this one, and includes a D-type flynog flop circuit (hereinafter referred to as D-F/F) 31 whose D input is connected to the power supply voltage VDD, and - Source-grounded N-type MO3) transistor (hereinafter referred to as NMOS) connected to the output of F/F31
32 and connected to the drain of NMO832 and connected to the power supply voltage V
A time constant element consisting of a resistor R and a capacitor C that divides DD, an inverter 33 whose input is connected to the drain of NMO832 and whose output is connected to the reset terminal of DF/F'32, and whose input is connected to the drain signal. and an inverter 34 whose output is the output terminal OUT.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the time chart shown in FIG. When the trigger signal TRIG for starting the generation of the one-shot pulse signal is not input, the output signal Q of the DF/F31 is NM at the "L" level.
The drain signal 35 of O832 is pulled up to vDD level, and the reset input signal RESET of DF/F31
And the output signal OUT is in a standby state at the "L" level.

When the trigger signal TRIG is applied here, the output signal Q of the D-F/F 31 rises from the "L# level" to the "H# level" and the output signal Q of the D-F/F 31 is "L" level M ≥ "H" level. Become. When the output signal Q reaches the t Hw level, the NMO 832 changes from non-conductive to conductive, and the voltage level of the drain signal 35 begins to attenuate due to the time constant of the conduction resistance of the NMO 832 and the capacitor C.

When the voltage level of the drain signal 35 becomes equal to or lower than the threshold value VT2 of the inverter 34, the output signal OUT is inverted from the "L" level to the "H" level. When the voltage level of the drain signal 35 further decreases and becomes lower than the threshold voltage VTI (VTI (VT2)) of the inverter 33, 1)-F/
The reset input signal RESET of F31 becomes H" level, D-F/F 31 is reset and the output signal Q becomes "L" level. When the output signal Q becomes "L" level, NMO832 becomes non-conductive again. Then, the drain signal 35 starts to be charged toward the stain source voltage VDD by the time constant of the resistor R and the capacitor C.

When the drain signal 35 returns to vTl, D-F/F3
The reset input signal RESET 1 changes from “H” level to “
When the drain signal 35 rises further and becomes equal to or higher than the threshold voltage VT2 of the inverter 34, the output signal OUT changes from the ``H'' level to the ``L'' level and enters the standby state. Return to

In this way, when the trigger signal TRIG rises, the OU
The T terminal has a one-shot pulse output signal OUT whose pulse width is determined by one charge/discharge of the capacitor, that is, the output ends after a time determined by one charge/discharge of the time constant element after the trigger signal TRIG is input. is obtained.

(Problem to be Solved by the Invention) However, in such a circuit, a time constant element, that is, a resistor or It is necessary to change the value of the capacitor, and two or more types of one-shot in the same circuit) i? In order to obtain a pulse output signal, it is necessary to increase the number of capacitors and resistors mentioned above and to switch them using a switch or the like. Since such capacitors and resistors must be externally attached as individual elements, the mounting area increases. Moreover, the cost increases due to external attachment.

(Means for Solving the Problem) This invention uses a counting means to count the number of charges and discharges by one time constant element, so that the number of charges and discharges determined by one cycle of charges and discharges after a trigger signal is input is determined.・It is designed to generate a signal that terminates the one-shock pulse output after an arbitrary cycle that is an integral multiple of the pulse width.

(Operation) This invention uses a counting means to count the number of charges and discharges caused by one time constant element, and ends the output after a time that is an integer multiple of one cycle of charge and discharge after a trigger signal is input. By specifying an integral multiple of the cycle due to charging and discharging using the counting means, it is possible to obtain an output signal that terminates output after an arbitrary cycle.

(Embodiment) FIG. 1 is a circuit diagram for explaining an embodiment of the present invention.

The one-shot pulse output signal generation circuit roughly includes a control means 101, a charging/discharging means 102, a means 103 for outputting a one-shot pulse output signal, and a counting means 10.
4, a time constant element 105, and a feedback means 106.

First, the control means 101 will be explained. This is D-F
/Fl and 0Re-to2. Trigger signal terminal T
RIG is a D-F/
Connected to FZ. The output of this DF/Fl is connected as a control signal to the input of ANDy-)4 together with the output of the inverter 3 of the charging/discharging means 102.

Further, the reset terminal of DF/Fl is connected to the output of an OR gate 2 whose one input is connected to the initialization signal terminal INI.

Next, the charging/discharging means 102 will be explained. This is AN
Df-)4, D-F/F5, NMO8e, and inverters 7.8.9 and 3. The input is AND e
The output of DF/F5, which has its D input connected to the power supply voltage, is connected on the one hand to the source-grounded NMO 86 that controls the time constant element 105, and on the other hand to the inverter 7. connected to the input of

The output of this inverter 7 is connected to the clock input terminal φ of the counter 10 of the counting means 1θ4.

Inverter 8 has a threshold voltage VTI and an input of N
The drain and output of MO86 are connected to the reset input terminal of DF/F5. The inverter 9 has a threshold voltage v
'r has a threshold voltage VT2 greater than 1, the input is the drain of NMO86, the output is connected via inverter 3 to the input of AND ff -) 4 on the one hand, and D-F on the other hand.
It is connected to the input of N0Rff-to 11 of means 103 for outputting a one-shot pulse output signal together with the output of /Fl.

Next, the time constant element 105 will be explained. The time constant element 1θ5 is the same as the circuit in FIG. 3, and the power supply voltage VDD
NMO8 consists of a resistor R and a capacitor C that divides the
Connected to 6.

Next, means 10 for outputting a one-shot pulse output signal
3 will be explained. This is NORf-to11 and
It consists of an inverter 12. The output of DF/Fz and the output of the inverter 9 are connected to the input of the NO1'l''-to 11, and the output is connected to the output terminal OU via the inverter 12.
Connected to T.

Next, the counting means 104 will be explained.

It consists of a counter 10 and a switch 13.

The output of each state of the counter 10 which receives the output of the inverter 7 of the charging/discharging means 102 is output from the output terminals 14 to 17, and the state of this output is selected by the switch 13. Note that it is preferable that the switch 13 be made programmable by operating it circuit-wise using a decoder or the like.

Note that the reset terminal of the counter 1θ is connected to the NOR'y''-to 1 of the means 103 for outputting the one-shot pulse output signal.
Connected to the output of 1.

Next, the feedback means 106 will be explained. switch 13
The output of is connected to the other input of an OR gate 2 whose one end is connected to the initialization terminal INI. OR date 2
The output of the control means 1 is connected to the reset input terminal of the D-F/F 1 as a reset input signal RESET 1.
Returned to 01.

The operation of this embodiment will be explained with reference to FIG.

When the initialize signal INI is input while the trigger signal TRIG is not input at the "H" level, D-F
/F2 is reset and output signal Q1 of D-F/FJ
is at L" level, the output signal Q2 of DF/F5 is at L" level, the drain signal 18 of NMO36 is at vDD level, and the output signals 19 and 20 of inverters 8 and 9 are at "L" level, respectively.
'L'' level, D-F/F 5 reset input signal RE
The SET 2 is initialized to the "LN" level, the reset input signal RESET 3 of the counter 10 is initialized to the "H" level, and the output signal OUT is initialized to the "L" level, and enters a standby state.

In this standby state, when the trigger signal TRIG goes high, the output signal Q1 of the DF/FJ goes high with the rise of the trigger signal TRIG. AN
AN because the other input of D-key card 4 is at “H# level”
The D dart 4 outputs the ``H# level'' as the output signal 21, and the output signal Q2 of the DF/F 5 is sent to the ``H'' level by the rising edge of the output signal Q1. Output signal Q
2 becomes "H" level, the NMO 86 changes from non-conducting to conducting, and the drain signal 18 of the NMO 86 becomes VD with the conduction resistance of the NMO 36 and the capacitance value of the capacitor C as a time constant.
Attenuation begins in the direction of the ground level from D.

Also, when the output signal Q1 rises, the NOR gate 1
1 output signal 22, that is, resetting the counter 10) Signal RESET 3 goes from "H" level to "Ln level, and the counter 10 is released from reset. Output signal O
The UT inverts this output signal 22 by the inverter 12 to attain the "H" level.

When the voltage level of the drain signal 18 becomes lower than the threshold voltage VT2 of the inverter 9, the output signal 20 of the inverter 9 becomes H" level, and the AND date 4
The output signal 21 of the inverter 8 becomes L" level, and the trigger of the D-F/Fs is released. When the voltage level of the drain signal 18 further decreases and becomes below the threshold voltage VT1 of the inverter 8, the output signal of the inverter 8 becomes low. 19 i.e. D-F, /
When the reset input signal RESET 2 of F5 becomes "H# level," D-F/F5 is reset. D-F/F5
When the output signal Q2 is reset, the output signal Q2 changes from the "H" level to the "L" level.
When the L'' level falls, the counter 10 counts up and the NMO 86 changes from a conductive state to a non-conductive state, and the voltage level of the drain signal 18 returns to the H# level due to charging in the VDD direction by the resistors R and C. When the voltage level of the drain signal 18 returns to VT1, the output signal 19 of the inverter 8, that is, the reset input signal RESET2 goes to L'' level, and the pD-F/F5 enters a trigger waiting state. When the voltage level of the drain signal 18 further increases and exceeds VT2, the output signal 20 of the inverter 9 becomes the "L#" level.

At this time, if the output signal 23 of the switch 13 is still at the "L" level, the DF/F1 is not reset, so the output signal Q1 of the DF/Fl remains at the "H# level". As the output signal 20 of the inverter 9 changes from the ``H'' level to the ``L'' level, the output signal 21 of the D-F/F 5 is set to the ``H'' level, and a re-trigger is established. This re-trigger causes the output signal Q2 to go “H”.
When the level is reached, the NMO 86 becomes conductive again and the voltage level of the drain signal 18 begins to attenuate.

The above cycle of discharging and charging the capacitor C is performed while the control signal Q1 of the control means 101 is being output, that is, after the trigger signal is input, the output signal 23 obtained by selecting the contents of the counter 10 with the switch 13 is high. ” level, and this signal is used as the reset signal RESET l to D-F/FJ.
It will start repeatedly until it returns to the original state. The final retrigger is established and the voltage level of drain signal 18 is VT.
When it becomes less than 1, the output signal 19 of the input signal 8 becomes “H”.
``level, and the I)-F/F 5 is reset.As the output signal Q2 falls, the counter 10 counts up, the state of the counter 10 reaches the specified state, and the output signal 23 of the switch 13 becomes 1H.'' level, 01
'l' - Output signal R1 of tote 2 is at 'H' level and DLF
/FJ is reset and the output signal Q1 becomes "L" level.

Here, when D-F/F 5 is reset, NMO86
becomes non-conductive and capacitor C begins to be charged through resistor R. When the level of the drain signal 18 returns to VTI, the reset input signal RESET2 of the D-F/Fs becomes N.
It becomes Ls level. When the level of the drain signal 18 further increases to VT2, the output signal 20 of the inverter 9
is at the "I." level. However, the output signal Q1 of the D-F/F1 is already at the "L" level, and the output signal 21 of the AND gate 4 does not become the "H" level.
F/F5 is not retriggered even though the output signal 2o falls. In addition, output signal Q1 and output signal 2
Output signal 2 of the NOR gate 11 from the "L" level of 0
2 is at "H" level, the counter 10 is reset, the contents of the counter 10 are cleared, and the output signal 23 is "H" level.
The output signal OUT, which is output after inverting the output signal 22 of the NOR dart 11 by the inverter 12, is reset to the "L" level because the output signal 20 becomes the "L" level.
"Return to level 2. At this point, the output of the one-shot ij pulse output signal ends.

Note that even if the voltage level of the drain signal 18 exceeds VT2, it continues to be further charged until it reaches VDD, and the trigger signal TRI
G (r) All operations of the Norrus generation circuit are completed.

That is, in this embodiment, the one-shot cruise output signal starts to be output when the trigger signal TRIG is applied, and ends when the charging of the time constant element 105 ends after the reset input signal is generated.

In other words, the end of the output of the one-shot cruise output signal depends on the charging/discharging time and the charging/discharging means 102 which is controlled by the control signal output from the control means 101 to which the output signal of the counter is fed back. It is determined by the number of repetitions of discharge.

By the way, the means for generating the one-shot cruise output signal may be configured as shown below. That is, N0R)
It is also possible to use the output of the switch 13 directly and use it as a one-shot pulse output signal without using the f''-gate 11 and the inverter 12. In this case, the reset signal RESET 3 of the counter 10 is separately output from the output signal Q1 and the output signal 2.
It is preferable to input 0 to NORr -) and input this output signal. In this case, the pulse width of the one-shot pulse output signal is not an integer multiple of the charging/discharging time of the time constant element 105, but the end of output of the one-shot pulse output signal takes some time after the trigger signal is input. This occurs after a time that is an integral multiple of the number of charges and discharges of the constant element.

(Effects of the Invention) As explained above, according to the present invention, after a trigger signal is input, the output is performed after an arbitrary integer multiple of the cycle of one charging/discharging of one time constant element. Since it is possible to generate a one-shot signal that terminates, the following effects can be obtained.

α) The circuit according to the present invention requires only one time constant element and does not require an increase in the number of externally attached individual elements.Therefore, the mounting area does not increase and the cost is reduced.

■) Since the above integer multiple is set by the counter built into this circuit, it can be set to an almost unlimited number, and the output can be terminated after an arbitrary number of cycles, making it possible to apply it to a wide range of areas. You will be able to do this.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment for explaining this invention,
FIG. 2 is a time chart thereof, FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is a time chart thereof. 1, 5-D-F/F 12 ・ORf −), 3
,7,8゜9.12...Inverter, 4...AND
r-t, 6...NMO8110...Counter, J
J-NORl''-), 13-... switch, 101...
- Control means, 102... Charging/discharging means, 103... Means for outputting a one-shot/gurus output signal, 104.
...Counting means, 105...Time constant element, 106.
...Feedback means, C...capacitor, R...resistance, T
RIG...Trigger signal, INI...Initialize signal, RESET 1, RESET 2, l5
ET 3...Reset input signal. Patent Applicant: Oki Electric Industry Co., Ltd. Circuit Diagram (Figure 3) (A) Kinto Shin 1 Fuimunaito Figure 4 (Procedural Amendments Exported) 1. Indication of the case 1985 Patent Application No. 141534 2 Name of the invention One shot 9 pulse output signal generation circuit 3 Person making the amendment Relationship to the case Patent application Life Place (
1-7-12-12 Toranomon, Minato-ku, Tokyo 1-7-14 Agent address (105) 1-7-1 Toranomon, Minato-ku, Tokyo
No. 2, 5. Subject of amendment The column "Detailed Description of the Invention" in the specification and 6. Contents of amendment (1) "Each" in the first line of page 10 of the specification are completely deleted. (2) On the second line of the same page in the same book, “20 is “L” level.”
(3) Correct "R1" on page 13, line 10 of the same book to "REST I J." (4) Correct "REST I J" in the drawing "1st Figure” “Figure 2”? Correct as shown in the attached sheet. More fried

Claims (1)

[Claims] In an output signal generation circuit that has a time constant element, starts a cycle consisting of a set of discharging and charging of the time constant element upon input of a trigger signal, and finishes outputting a one-shot pulse at the end of this cycle. control means for outputting a control signal from input to input of a reset input signal, and charging/discharging means for repeatedly starting a cycle consisting of a set of discharging and charging of the time constant element based on the control signal. , a counting means for counting the number of charges and discharges and generating an output signal at a predetermined number, and means for feeding back this output signal to the control means as the reset input signal. Shot pulse output signal generation circuit.