JPS623519B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to monolithic I ² L integrated circuits, particularly I ² L integrated circuits.
The present invention relates to a two-phase shift register using technology.

West German Patent Publication (DE-OS) No. 2442773 describes the so-called I ² L (integrated injection logic)
A circuit embodied by the technology is disclosed. It concerns a master-slave flip-flop circuit with two storage cells having two injectors separated from each other.
These storage cells are used with clocked two-phase shift registers. The invention has separately clocked storage cells in a master-slave flip-flop circuit and is applied to monolithic I ² L integrated circuits.

It is an object of the invention to provide a two-phase shift register suitable for monolithic I ² L integrated circuits that allows for chip area savings and high speed operation.

Next, embodiments of the present invention will be described with reference to the drawings. Figure 1 shows a monolithic I ² L according to this invention.
FIG. 2 is a circuit diagram showing the basic configuration of a two-phase shift register for integrated circuits. This shift register includes two flip-flop circuits arranged in series.
Each flip-flop circuit is
It has one main storage cell M1 or M2 and one slave storage cell S1 or S2. All storage cells in a monolithic ^I2L integrated circuit according to the invention are arranged in a pair of cross-coupled
Contains an ^I2L transistor. The cross couple is formed by connecting the base of each to the first collector of the other. Main storage cells M1, M2... The second collectors of the respective I ² L transistors are connected to the secondary storage cells S1, S2...
...connected to the base of each I ² L transistor. These main storage cells and corresponding slave storage cells constitute the same flip-flop circuit. Said slave storage cells S1, S2... 2 forming each of them
The second collectors of the two transistors are further connected to the base end or output end A of the main storage cell in the next stage. The input signal is applied to terminal E, that is, to both base terminals of the two I ² L transistors constituting the first main storage cell M1.

In FIG. 1 and the subsequent figures, the portion surrounded by broken lines indicates the injection device I _n or I _s . The description of this injection device is given using the simplest example for ease of understanding. The injector is based on the well-known I ² L design method, and the same is true for parallel-connected injectors. Furthermore, the two injection devices I _s and I _n are independent of each other. This is indicated by the two non-overlapping dashed areas. This means that the implanter I _n is not influenced in any way by the transistors that constitute the implanter I _s .
Furthermore, the injection device I _s is not affected by the injection device I _n . This is accomplished by electrically isolating multiple implanters using topologically compatible designs or isolation regions. The former is achieved, for example, by selecting the distance between circuit elements, and the latter by providing an insulating region or a dielectric intermediate layer.

The gist of the invention is that one of the clock signals is in principle out of phase with the others, and this clock signal is guided to each injection device. In this injection device, one or more injectors of each clock device are connected to one clock pulse line.

The two clock signals T _n and T _s for the two injection devices I _n and I _s are preferably generated using differential amplifiers. FIG. 3 shows the basic circuit configuration of this differential amplifier. As shown in Figure 3, 2
Each of the two injection devices I _n and I _s is connected to transistors T3 and T4 of the differential amplifier. The emitters of these transistors are connected to a current source I. Two clock signals P _n and P _s having opposite phases to each other are connected to the transistor T.
3 and T4 base.

The differential amplifier shown in FIG. 3 may be configured as an oscillator. That is, the amplifier may be configured to receive two clock signals P _n and P _s from the other side of the circuit. This preferably utilizes a flip-flop implemented in I ² L technology, as shown in FIGS. 5 and 6.

5 and 6 show two transistors T
7 and T8 flip-flops. This flip-flop may be formed directly as a component of the counter circuit chain that precedes it. In order to prevent the two PNP transistors T3 and T4 constituting the differential amplifier from being saturated, the transistors T3 and T4 are
and the collectors of transistors T7 and T8 constituting the flip-flop,
A respective forward biased diode is provided.

This forward biased diode is the fifth
In the figure, it is formed by a PN junction diode D1 or D2. These diodes are
It can be formed within the isolation region of PNP transistors T3 and T4. Alternatively, these diodes can be replaced by control transistors T5 and T6, as shown in FIG. The input signals to the differential amplifier are symmetrical rather than asymmetrical. This differential amplifier constitutes a part of the oscillator. The frequency of this oscillator is
reduced by the I ² L drive stage. The current versus time curves of the two injection currents I _n and I _s are as shown in FIG.

The most preferred division ratios and clock signal frequencies available using differential amplifiers are obtained using the monolithic I ² L integrated circuit of the present invention as shown in FIG. Here, it is used as a so-called Johnson divider (dividing ratio 1:4) and is connected as shown in the block diagram of FIG. This 1:4 split ratio results in very favorable circuit element savings. That is,
The required space within the semiconductor chip can be saved. This is because only one clock pulse frequency is required.

According to the monolithic I ² L integrated circuit according to the present invention, as shown in the block diagram of FIG.
A counter can be configured. The variable synchronous divider with two-phase shift register shown in FIG. 7 includes a reserve and/or management network N clocked by the outputs of these particular storage cells. That is, in this case,
The protection/management network _N is controlled by slave storage cells S1, S2, S3 and S4 which are controlled by the same clock signal Is. This process is necessary. The gate of the network N that is set based on the program is:
This is because accurate timing is required for forming the output signal of the network N that is applied to the input, ie, the main storage cell M1.

Typically, a drawback with clocked shift registers is that only one set of output signals is useful in the clocked configuration. This can be improved by providing a static intermediate memory. However, providing such an intermediate memory is extremely costly from a circuit design standpoint. A highly advantageous space saving possibility will be explained with reference to the circuit diagram shown in FIG. FIG. 8 shows another embodiment of the present invention which can simultaneously solve the above-mentioned problems.

The monolithic I ² L integrated circuit of FIG. 8 shows the final stage of a two-phase shift register in which the signals are output as a set. In this final stage, the second I ² L transistor T2 _so of the slave storage cell and the first I ² L transistor T1 _no of the main storage cell each have a third collector. These two third collectors 3 are connected to each other and the output signal occurring here is led to the input of an unclocked amplifier V. This input is indicated by the base of the input transistor _Tv . The amplifier V is, of course,
Preferably formed by ^I2L technology,
It does not include clocked injectors or clocked injection devices. In this manner, the pair of output circuits that transmit the clocked logic to the static logic is greatly simplified.

The signals of the two clock pulse devices are coupled together at the input of the amplifier V. This allows the output signal to be used during both clock half cycles to directly control static gates and other circuits used in combination. Two clock signals are generated by using the differential amplifiers of FIGS. 3-6. The circuit disclosed herein has the advantage that no transient signal peaks occur when switching from one clock signal to another. For example, the segment display static decoder can be directly controlled by a clocked counter.

The pair of output circuits shown in FIG. 8 can also be used effectively when controlling storage inputs.

Because the principles of the invention have been described in connection with specific circuit arrangements, what is disclosed herein is intended to be illustrative only and is intended to limit the scope of the invention as indicated by the scope and claims. It will be clearly understood that this is not the case.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the basic configuration of a two-phase shift register according to the present invention, Fig. 2 is a block diagram showing a Johnson divider as an applied example of the invention, and Fig. 3 shows two clock devices. FIG. 4 is a diagram showing the operation of the circuit shown in FIG. 3, and FIGS.
7 shows a block diagram of a programmable divider to which the present invention is applied, and FIG. 8 shows a preferred output circuit according to the present invention. FIG. 2 is a circuit diagram showing the final stage of a two-phase shift register. I _n ...First injection device; _Tn ...First clock signal; M1-M4...Main storage cell; _Is ...Second injection device; _Ts ...Second clock signal; S1-S4
...Substorage cell; E...Input signal end; T1 _n 1,
T2 _n 1, T1 _n 2, T2 _n 2... I ² L for main storage cell
Transistor; T1 _s 1, T2 _s 1, T1 _s 2, T
2 _s 2... I ² L transistor for secondary storage cell; A...
Output signal terminal; T3...first transistor for differential amplifier; T4...second transistor for differential amplifier;
T1 _no ... ^I2L transistor with third collector for main storage cell; T2 _so ... ^I2L transistor with third collector for secondary storage cell; V...unclocked amplifier; _Tv ...input transistor; N... …spare/
Management network (clocked network).

Claims (1)

Claims: 1. A main storage cell controlled by a first clock signal via a first injection device, and a slave storage cell controlled by a second clock signal via a second injection device, An input signal is applied to the base terminals of the two I ² L transistors constituting the main storage cell, and an output signal is taken out from the second collector of the I ² L transistor constituting the secondary storage cell. a pair of I 2 L transistors with first collectors of the transistors each connected to a second collector of a transistor of the main storage cell, and each of the main and slave storage cells being cross-coupled to a base end thereof through the ^first collector; In a monolithically integrated series-arranged I ² L flip-flop circuit, the first clock signal is taken out from the collector of the first transistor of two transistors constituting the differential amplifier; 1. A two-phase shift register, wherein said second clock signal is taken out from a collector of a second transistor of said differential amplifier and applied to said second injection device. 2. One of the I ² L transistors of the main storage cell and one of the I ² L transistors of the secondary storage cell both have a third collector, and a second of the transistors of the main storage cell with this third collector A collector is connected to a first collector of a transistor of the secondary storage cell having a third collector, and the third collectors of the transistors of the primary and secondary storage cells are both connected to an input of an unclocked amplifier. Characteristic claim 1
Two-phase shift register as described in Section. 3. The two-phase shift register according to claim 1 or 2, wherein the differential amplifier forms an oscillation circuit by being coupled with the cross-coupled pair of transistors. 4. Claims 1 to 4, wherein the first or second clock signal is applied to the base or collector of at least one of the pair of cross-coupled I ² L transistors. The two-phase shift register according to any one of Item 3. 5. According to any one of claims 1 to 4, wherein a plurality of the primary and secondary storage cells are clocked by a common clock signal, and the storage cells form a clocked network. Two-phase shift register as described.