JPS623515B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage clamp circuit, and particularly to a voltage clamp circuit that limits the precharge voltage of a vertical ROM (read-only memory) constructed of insulated gate field effect transistors (hereinafter simply referred to as FETs). Regarding voltage clamp circuits.

There is a conventionally known vertical ROM (read only memory) as shown in FIG. The figure shows a part of the matrix ROM, which is used for pre-charge to which clock pulse _φ
FETT _P and n to which address signals A ₁ ~ An are applied
_FETT1 to _T0 , and the output _Vput is taken out from the connection point of both FETs. In addition,
Capacity C is used for data storage. A ROM with such a configuration turns on FETT _P with a clock pulse _φ
Precharge the capacity of FETT ₁ to T _o . For example, this precharge charge is discharged when all of FETT ₁ to T _o are turned on, so that a GND (ground) potential can be read from _Vput . Regarding vertical ROM, for example,
It is described in relatively detail in Publication No. 30388.

By the way, with the above configuration, the precharge voltage is maintained close to the power supply voltage, so the drive
As the number of FETT ₁ to _{T o} increases, the pre-charge time becomes longer, and the de-charge time also becomes longer, causing a delay in the operating speed.

Therefore, an object of the present invention is to provide a circuit that can limit the precharge voltage regardless of the voltage value of the power supply used, and can be expected to speed up the operation of a vertical ROM. The object is to provide a circuit that can automatically set the potential of the precharge voltage.

The gist of the present invention is to provide a precharge means provided between the first power terminal of a pair of power terminals consisting of first and second power terminals and a first connection point; and the second power supply terminal, and a plurality of capacitors connected in series between the first connection point and the second power supply terminal.
a voltage clamp circuit in a vertical ROM including a FET, a switching means connected in series to the precharge means between the first power supply terminal and the first connection point; by controlling the switching means by the output of the inverting means, the precharge voltage level to the capacitance is changed between the first power supply terminal and the second power supply terminal. A voltage clamp circuit is characterized in that the voltage is limited to a value smaller than the voltage between.

The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 2 is a circuit diagram of a voltage clamp circuit,
FIG. 3 is a voltage waveform diagram for explaining the operation.

The circuit in Figure 2 consists of a precharge FETT _P connected to the power supply voltage _{V DD} side and driven by the clock pulse _{φ D} and above
Switching FETT _C inserted and connected between FETs
and an inverter _G1 whose input is the voltage _V2 at the connection point of the switching FETT _C and _the driving FETT _D. control. Note that capacitance C is a storage capacitance to which the above clock pulse _φX is applied.
FETT _P is precharge means, V _io is applied
FETT _D is the discharge means. here,
It is necessary to set the logic threshold voltage of inverter G ₁ to a value much lower than the power supply voltage V _DD (the threshold of an inverter using a normal FET is 4 V or less, so there is no need for special design. (That's enough.) Further, the power supply used in the above circuit is a negative power supply _-VDD , and all FETs are p-channel FETs.

According to the circuit configured above, as shown in the voltage waveform diagram of FIG. 3, the clock pulse _φ
DD ) level, FETT _P for pre-charge is turned on. At this time, the charging voltage is inverter G ₁
, the output _Vput of the inverter _G1 is at the "1" ( _-VDD ) level, and the switching FETT _C is turned on. Therefore, FETT _P for pre-charge is turned on.
The capacitor C is charged via the switching FETT _C and the switching FETT C (time t ₁ ). Then, the charging voltage V ₂ of the capacitor C is the threshold voltage V _LT of the inverter G ₁
When the value exceeds 1, the output V _put of this inverter G ₁ becomes "0" (GND) level (time t ₂ ). Switching FETT _C due to the “0” level of this output V _put
Since the capacitor C is turned off, charging to the capacitor C is cut off.
At this stage, the input V _io becomes "1" (-V _DD ) level, and when FETT _D is turned on, the capacitance C
A death charge will be carried out. In this case, since the voltage V ₂ of the capacitor C is almost the threshold voltage V _LT of the inverter G ₁ , its level immediately becomes smaller than the threshold voltage V _LT , and the output of the inverter G ₁ is inverted (“1”). ”)
I will let you do it. In other words, V _put is “1”
is read out (time t ₃ ). As a result of such an operation, the pre-charge and de-charge times can be shortened and the operation speed can be increased. Furthermore, by setting the threshold voltage _VLT of inverter _G1 , the precharge potential can be set, so even if the power supply voltage used changes, it is possible to automatically set the precharge potential to the best point. .

FIG. 4 is a circuit diagram of a vertical ratioless ROM showing an embodiment of the present invention, and FIG. 5 is a voltage waveform diagram for explaining its operation.

In FIG. 4, X lines (X ₁ to X ₅ ) and Y lines (YC ₁ to YC ₆ , Y ₁ to Yn) are formed in an intersecting manner, and appropriate points of intersection between the X lines and Y lines are Portion 1 in which FETs are formed vertically (for example, the portion shown by B in FIG. 4A is becoming as shown in FIG. 4B) is the matrix ROM portion, and the Line power supply -V
The portion consisting of the precharge FETT _P , the switching FETT _C , and the inverter _G1 provided between _{the DDs} is the voltage clamp circuit of the present invention. inverter
G ₂₁ ~ _{G 23} , G ₃₁ ~ _{G 32} , FETT for selection _A1 ~ T _A4 ,
Part 2 consisting of TY ₁ to TYn, etc. is an address decoder ROM part. In the matrix ROM section 1, each Y line constitutes an address line and is coupled to the output of the address decoder ROM section 2. FETTY ₁ -TYn are switch-controlled by clock pulse _φY .

In a circuit with such a configuration, as shown in FIG.
The multi-bit selection signal V _A for the address line of the matrix ROM section 1 is changed (time
_t1 ). Y lines YC ₁ to YC ₆ are connected to 3-bit signals of the selection signal V _A (inverters G ₂₁ to
_G23 input signal) determines its level, which selects one of the X lines _X1 to _X5 . When the clock pulse φ _Y becomes "1" level (-V _DD ) after the selection signal V _A changes, FETY ₁ to TYn turn on in response, and all address decoder outputs Y ₁ to Yn become "1". stand up. That is, the outputs Y ₁ to Yn of the address decoder are set to the precharge level. FETTY ₁ to TYn are then turned off by setting φ _Y to the “0” level. output
The FET installed between Y ₁ ~ Yn and the ground terminal is
The state of each switch is controlled by a selection signal V _A to form a current path between one of the outputs Y ₁ -Yn and the ground terminal. Therefore,
When FETTY ₁ -TYn are turned off, one line among the precharged outputs Y ₁ -Yn becomes "0" and is selected. matrix
The output point of the ROM section 1 is precharged via FETT _P and FETT _C when FETT _P is turned on by the clock pulse _φX becoming "1". This allows the matrix ROM
The potential V at the output point 1 is charged to the threshold voltage V _Lt of the inverter G ₁ . As a result, the output _Vput becomes "0" and FETT ₀ is turned off (period _t3 to _t4 ). If all of the series-connected FETs in a selected X line (any of X ₁ to _{X 5} ) are on, then the matrix
Since the potential V at the output point of the ROM falls and inverts the state of the inverter _G1 , a "1" level is obtained at _Vput (time _t5 ). Thereafter, the output _Vput is accessed, that is, the output _Vput is used in a circuit not shown. This makes it possible to shorten access time.

As described above, according to the present invention, the precharge voltage of the vertical ROM is limited to speed up the discharge, thereby speeding up the operation of the vertical ROM, and the precharge voltage can be increased regardless of the value of the power supply voltage used. The best point can be automatically set.

The present invention is not limited to the above embodiments, but can be modified in various ways. For example, in the embodiment described above, the switching means is configured by an FET, but other switching elements may be used. Moreover, an inverter having any configuration may be used as the inverting means. Furthermore, the polarity of the power supply used and the FET
The conductivity type may be completely reversed.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional vertical ROM, Figure 2 is a circuit diagram of a voltage clamp circuit, Figure 3 is a voltage waveform diagram for explaining its operation, and Figure 4A is an example of the present invention. FIG. 4B is a partial circuit diagram for explaining the configuration of section B in FIG. 4A, and FIG. 5 is a voltage waveform diagram for explaining its operation. 1...Matrix ROM, 2...Decoder
ROM, G ₁ to G ₅ ... Inverter, T _P , T _C , T
_D , T ₁ ~Tn, TY ₃ , TY ₄ , T _A1 ~ T _A4 ...FET,
C...Capacity.

Claims (1)

[Claims] 1 a precharge means provided between the first power terminal of a pair of power terminals consisting of first and second power terminals and a first connection point;
A vertical type including a capacitor coupled between the connection point and the second power supply terminal, and a plurality of FETs connected in series between the first connection point and the second power supply terminal.
A voltage clamp circuit in a ROM, comprising switching means connected in series to the precharging means between the first power supply terminal and the first connection point, and an inverting means receiving the voltage at the first connection point as input. and by controlling the switching means by the output of the inverting means, the precharge voltage level to the capacitor is set to be higher than the voltage between the first power supply terminal and the second power supply terminal. A voltage clamp circuit characterized in that the voltage is limited to a small value.