JPS6232877B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A beam-indexed color television receiver has a single electron beam as a picture tube, with red, green and blue color phosphor stripes arranged horizontally. An index that has a fluorescent surface and index phosphor stripes arranged horizontally on the inner surface of the phosphor surface is used, and is obtained by scanning the index phosphor stripes with an electron beam. Color switching is performed based on the signal, and when the electron beam scans the red color phosphor stripe, the red primary color signal is used.
When scanning a green phosphor stripe, a green primary color signal is used, and when a blue phosphor stripe is scanned, a blue primary color signal is used for density modulation.

The present invention provides such a beam index type color television receiver in which the focus is automatically adjusted to always be optimal.

In a beam index type color television receiver, the amplitude of the index signal changes depending on the focus state of the picture tube.

That is, when the electron gun of the picture tube is a unipotential type, as shown in FIGS. 1 to 3, the electron beam is emitted from the cathode 16 and passes through the first grid 11, second grid 12, third grid 13, A high voltage KV is applied to the third grid 13 and the fifth grid 15, and a focus voltage FV is applied to the fourth grid 14. ,
If the voltage difference ΔV between the high voltage HV and the focus voltage FV is large, overfocus will occur as shown in Figure 1, and when the difference voltage ΔV is an appropriate size, just focus will occur as shown in Figure 2. Voltage ΔV
If is small, underfocus will occur as shown in Figure 3. When in just focus, the diameter of the spot of the electron beam is at its minimum, so the amplitude of the index signal is at its maximum.On the other hand, at overfocus or underfocus, the diameter of the spot is large, so the amplitude of the index signal is at its maximum. becomes relatively small. Therefore, the amplitude of the index signal is the voltage ΔV of the difference between the high voltage HV and the focus voltage FV, as shown by curve 1 in FIG.
exhibits unimodal characteristics.

Here, when a superimposed AC signal with a certain period on the DC focus voltage FV is applied to the focus electrode 14, the index signal undergoes amplitude modulation at that period. The mode of amplitude modulation changes depending on the focus state.

In other words, as shown in Fig. 4, when in just focus, the index signal does not undergo amplitude modulation even if an AC signal is superimposed, but when in overfocus, it undergoes amplitude modulation in the same phase as the superimposed AC signal, and when it is in underfocus, it undergoes amplitude modulation. When in focus, it receives amplitude modulation that is opposite in phase to the reversely superimposed alternating current signal.

Therefore, in this case, when the amplitude detection signal of the index signal and the superimposed AC signal are phase-compared, the phase comparison output will be at the point of just focus with respect to the focus voltage FV, as shown by curve 2 in the figure. It exhibits S-shaped characteristics centered on .

This invention focuses on this point, and the DC voltage FV
A superimposed AC signal with a certain period is applied to the focus electrode, and the phase of the amplitude detection signal and the superimposed AC signal when the electron beam of the index signal has a constant beam amount is compared, and the phase comparison output is Controls the level of DC voltage FV and automatically adjusts the focus to always be optimal.

FIG. 5 shows an example of a beam index type color television receiver according to the present invention, and 10 is a beam index type color picture tube, for example, as shown in FIG. Effective screen portion 17 where body stripes R, G and B are formed
An index phosphor stripe I is formed at a pitch of 2/3 of a set of color phosphor stripes R, G, and B over the horizontal scanning start section 17B on the left side of the index A, and an index phosphor stripe I is formed on the outside of the funnel section. A photodetector 21 is provided.

and horizontal and vertical blanking pulses P
_B is supplied to the switch 28, the switch 28 is turned off during the "0" period of the pulse P _B , that is, the horizontal and vertical retrace periods, and the picture tube 10 is cut off, and the picture tube 10 is cut off during the "1" period of the pulse P _B. That is, the switch 28 is turned on during the horizontal scanning period within the vertical scanning period.

Then, at the trailing edge of the blanking pulse P _B , the RS flip-flop 41 is set and its output signal P _W becomes "1", and this output signal P _W is supplied to the switch 26 and during the "1" period. The switch 26 is switched to the terminal W side, a DC voltage from the voltage source 27 is supplied to the first grid 11 of the picture tube 10, and the electron beam scans the horizontal scanning start part 17B with a relatively large constant beam amount. Photodetector 2
At 1, light from the index phosphor stripe I of the horizontal scanning start section 17B is detected.

The output signal of this photodetector 21 is passed through a bandpass filter 22 and a phase shifter 23 for phase adjustment, so that the index phosphor stripe I
An index signal S _I with a frequency f _I determined by the pitch of the PLL and the scanning speed of the electron beam is obtained.
30.

In the PLL 30, the index signal S _I is supplied to the phase comparator 31, and the output signal S _O of the voltage controlled oscillator 32 is supplied to the frequency divider 33, where the frequency is divided by 1/2 in the case of FIG. The frequency signal P _N is supplied to a phase comparator 31 , and the output voltage of the phase comparator 31 is supplied to an oscillator 32 through a low-pass filter 34 .

On the other hand, another RS at the trailing edge of blanking pulse P _B
The flip-flop 42 is set and its output signal P _S becomes "1", and the index signal S _I
is supplied to the pulse shaping circuit 43 to obtain an index pulse P _I , and this index pulse P _I
At the first rising edge of , the flip-flop 42 is reset and its output signal P _S becomes "0".

Then, the output signal P _S of the flip-flop 42 is supplied to the oscillator 32 of the PLL 30, and the oscillation phase of the oscillator 32 is regulated. That is, as shown in FIG. 6, during the period of "1" of the signal P _S from the trailing edge of the blanking pulse P _B to the first rise of the index pulse P _I , the oscillator 32 stops oscillating. When the output signal S _O maintains the state of "0" and the signal P _S becomes "0" at the first rising edge of the index pulse P _I , the oscillator 32
starts oscillating, and its output signal S _O begins to alternate between "0" and "1" states, so that the phase of the output signal S _O with respect to the index pulse P _I changes as shown in the figure. It is determined as follows.

Furthermore, the output signal P _S of the flip-flop 42
is also supplied to the frequency divider 33 of the PLL 30, and at the same time, the state of the frequency divider 33 is regulated. That is, the picture tube 10 is configured as shown in FIG. 6, and the frequency divider 33 is 1/2.
When used as a frequency divider, the frequency divider 33 is composed of one flip-flop, but in this case, this flip-flop is triggered at the rising edge of the output signal S _O of the oscillator 32, and the flip-flop is triggered at the rising edge of the output signal _{S O} of the oscillator 32, and During the "1" period, this flip-flop is cleared and its output signal P _N is set to "0".

In this way, the output signal P _S of the flip-flop 42 determines the phase of the output signal S _O of the oscillator 32 with respect to the index signal S _I , and the state of the frequency divider 33 is regulated, so that the index pulse P _I At the first rising edge of , the frequency-divided signal P _N from the frequency divider 33 becomes exactly 90 degrees behind the index signal S _I as shown in the figure, so that the PLL 30 immediately locks. Become.

When the PLL 30 locks, the output signal S _O of its oscillator 32 becomes the index signal S _I as shown.
frequency 3, which is twice the so-called triplet frequency determined by the pitch of the set of color phosphor stripes R, G, and B and the scanning speed of the electron beam.
At _T , each color phosphor stripe rises R, G
and B (assuming that it is formed extending from the effective screen area 17A, although it is not in the horizontal scanning start area 17B), the phase will be at an intermediate position.

The output signal S _O of this PLL 30 is supplied to a gate signal generator 24 to obtain three-phase gate signals S _R , S _G and S _B for gating the red, green and blue primary color signals, and in this case, flipflop 42
The output signal P _S is further supplied to this gate signal generator 24 as a mode set pulse to generate the signal P
The gate signals S _R , S _G and S _B are aligned in phase by _S.

That is, the gate signal generator 24 has, for example, 3
It consists of a ring counter having JK flip-flops in stages, and the Q outputs of the first, second and third stage flip-flops are gate signals S _R , S _G
and S _B , but during the period when the output signal P _S of the flip-flop 42 is "1", the first stage flip-flop is preset and the gate signal S _R is set to "1", and the second and third stage flip-flops are preset. The flip-flop of is cleared and the gate signals S _G and S _B are set to "0", and when the signal P _S becomes "0" at the first rising edge of the index pulse P _I , each output is shifted every time the signal S _O rises. Gate signals S _R , S _G and S _B are applied to red, green and blue color phosphor stripes R, G and B (not in the horizontal scanning start part 17B but extending from the effective screen part 17A), respectively. It becomes "1" at the position ).

On the other hand, the counter 44 is cleared during the "1" period of the output signal P _S of the flip-flop 42, and the signal P _S is cleared at the first rising edge of the index pulse P _I.
When becomes "0", the falling edge of the divided signal P _N from the frequency divider 33 of the PLL 30 is counted by the counter 44, and at the end of the horizontal scanning start section 17B, the falling edge of the divided signal P _N from the frequency divider 33 of the PLL 30 is counted by the predetermined number indicated by the arrow. When the falling edge of the flip-flop 41 is counted, the flip-flop 41 is reset, its output signal P _W becomes "0", and the switch 26 is switched to the terminal V side.

When the switch 26 is switched to the terminal V side,
Therefore, in the effective screen area 17A, the gate signals S _R , S _G and S _B from the gate signal generator 24
Switch 25R, 25G at the positions of the red, green and blue color phosphor stripes R, G and B where the value becomes "1"
and 25B are turned on, red, green and blue primary color signals E _R , E _G and E _B are taken out, and the switched primary color signals are sent to the first grid 11 of the picture tube 10 .
is supplied to

In the present invention, for example, the vertical pulse P _V is supplied to the flip-flop 45 and is inverted every vertical period as shown in FIG.
_X and S _Y are obtained, and one of the signals _S
is supplied as a control voltage. On the other hand, high voltage HV obtained from the high voltage generating circuit 61 is applied to the anode button 18 of the picture tube 10, but bleeder resistors 62, 63 are connected between the output side of the high voltage generating circuit 61 and the output side of the DC-DC converter 50. and 64 are connected, and the voltage obtained at the regulator of the intermediate resistor 63 is applied to the focus electrode 14 of the picture tube 10.

The DC-DC converter 50 is a circuit similar to the high voltage generation circuit 61 that uses horizontal pulses P _H , but the output voltage is converted to a negative voltage and taken out, and when the control voltage increases, the output voltage decreases. ing. Therefore, by supplying the signal S _X as a control voltage, the output voltage changes every vertical period based on the negative DC potential MV as shown in FIG. 7, and is thereby applied to the focus electrode 14. As shown in the figure, the voltage also changes every vertical period based on the DC voltage FV. That is, the focus electrode 14 is given a superimposed AC signal that is inverted every vertical period and has an opposite phase to the signal S _X on the DC voltage FV. Therefore, as explained in FIG. 4, the index signal S _I is subjected to amplitude modulation in a manner depending on the focus state.

This index signal S _I is then supplied to an amplitude detector 65 for double wave detection as shown in FIG. 8, for example, and the detected signal S _D is supplied to a sampling and hold circuit 70. On the other hand, the output signal P _W of the flip-flop 41 is input to the AND gate 66
At the same time, the output signal P _S of the flip-flop 42 is inverted by an inverter 67 and supplied to an AND gate 66, which converts the signal P _S from the falling edge of the signal P S to the rising edge of the signal P _W as shown in FIG. A sampling pulse P _D having a pulse width between 1 and 2 is obtained, and this sampling pulse P _D is passed to the sampling hold circuit 70.
The switch 71 is turned on during the period of the pulse width, and the portion of the detection signal S _D when the electron beam at the beginning of each horizontal scanning period has a constant beam amount is sampled and held. Ru. And its sampling hold voltage
EH is supplied to a phase comparator 80.

The phase comparator 80 obtains the voltage difference between the value of the sampling and holding voltage EH from the sampling and holding circuit 70 in the vertical period when the output signal _S It is becoming more and more popular.
That is, the output signal S _X of the flip-flop 45
is supplied to the switch 81 and the output signal S
During the vertical period when _Y is supplied to the switch 82 and the signal _S During the vertical period in which the signal S _Y goes high as the signal S _X goes low, the switch 82 turns on and the sampling hold voltage increases.
EH in that vertical period is further sampled and held and is applied to the negative input of the differential amplifier 83. Then, the phase comparison output of this phase comparator 80, that is, the differential amplifier 83
The output voltage is smoothed by a low-pass filter 68 and supplied to the DC-DC converter 50 as a control voltage through the matrix circuit 46.

The focus electrode 14 is supplied with a DC voltage as described above.
Since the FV is given a superimposed AC signal of opposite phase to the signal _S
During overfocus, the amplitude of the index signal S _I is small during the vertical period when the signal S _X is at a high level, and becomes large during the vertical period when the signal S _X is at a low level. Therefore, at this time, the sampling hold voltage EH is small during the vertical period when the signal S _X is at a high level, and becomes large during the vertical period when the signal S _X is at a low level. Therefore, the voltage at the negative input of the differential amplifier 83 becomes higher than the voltage at the positive input, the output voltage of the differential amplifier 83 becomes lower, and the DC voltage of the output voltage of the DC-DC converter 50 decreases. MV is raised (close to ground potential), and the DC voltage FV applied to the focus electrode 14 is raised to achieve just focus, as is clear from FIG. 4.

At the time of underfocus, contrary to FIG. 7, the amplitude of the index signal S _I is large in the vertical period when the signal S _X is at a high level and becomes small in the vertical period when the signal S _X is at a low level. Therefore,
At this time, the sampling hold voltage E _H becomes _large during the vertical period when the signal _S
It becomes smaller during the vertical period when the signal becomes low level. Therefore, the voltage at the positive input of the differential amplifier 83 becomes higher than the voltage at the negative input, the output voltage of the differential amplifier 83 increases, and the DC potential of the output voltage of the DC-DC converter 50 increases. MV is lowered (moved further from the ground potential) and the DC voltage FV applied to the focus electrode 14 is lowered to achieve just focus as is clear from FIG.

In this way, the level of the focus DC voltage FV is controlled by the phase comparison output of the phase comparator 80 that detects the focus state, so that the focus is automatically adjusted to always be optimal.

In the example shown in the figure, the parabolic voltage EP with a vertical period is actually supplied to the matrix circuit 46, and as shown in FIG. ₉ , the sum of the signal S In this case, the same operation as described above is still performed.

By applying to the focus electrode 14 a superimposed AC signal that is inverted every horizontal period and has a period of two horizontal periods with respect to the DC voltage FV, the amplitude of the index signal S _I is increased to 1. It may be made to change every horizontal period.
Of course, in that case, a signal that is inverted every horizontal period is supplied to the phase comparator 80.

Further, for example, the electron beam is configured to scan the index phosphor stripe I with a constant beam amount in one or more horizontal periods at the top of the screen, and the amplitude detection signal and the DC voltage FV of the index signal at this time are superimposed. Alternatively, the phases of the alternating current signals may be compared.

Note that a DC amplifier using a transistor may be used instead of the DC-DC converter 50, and the AC signal may be directly applied to the focus electrode 14 through capacitive coupling.

According to this invention, in a beam index type color television receiver, the focus can be automatically adjusted to always be optimal. Furthermore, since the focus is always optimal and the amplitude of the index signal is always maximized, color switching is also effected stably.

[Brief explanation of the drawing]

1 to 4 are diagrams for explaining the relationship between the focus state and the amplitude of the index signal in a beam index color television receiver, and FIG. A system diagram of an example of the machine, FIGS. 6 to 9, are waveform diagrams for explaining its operation. 10 is a picture tube, 14 is its focus electrode, 2
1 is a photodetector, 22 is a bandpass filter, 65
70 is a sampling and holding circuit, 80 is a phase comparator, and 50 is a DC-DC converter.

Claims (1)

[Claims] 1. A variable voltage source for supplying a DC voltage to the focus electrode of the index picture tube, a matrix circuit for superimposing an alternating current signal of a constant period on the focus electrode, and an index signal from the picture tube when the electron beam is constant. a detection circuit that detects the amplitude of the signal, a phase comparison circuit that compares the phase of the output of the detection circuit and the AC signal, and a phase comparison output of the phase comparison circuit that is supplied to the control terminal of the variable voltage source to receive the image. A beam index type color television receiver characterized in that each control loop is provided to control the focus state of the tube so as to always keep it optimal.