JPS6232427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alarm sound generating device for a watch that can generate a pseudo sound such as a bird's voice.

Conventionally, various notification sounds have been proposed for use as alarm sounds for clocks. The conditions for the notification sound used as the alarm sound are, first of all, to be able to reliably notify the user that the set time has arrived. This first condition can be solved by increasing the volume, etc., but no matter how reliable it is to notify the user that the set time has arrived, it may cause discomfort to the user. Notification sounds that disturb others are not suitable as alarm sounds. The second alarm sound is something that is pleasant to hear.
It becomes a condition of

In recent years, natural sounds, especially bird voices, have been attracting attention as notification sounds that satisfy these first and second conditions.

However, when we analyzed the sounds of birds, we found that the changes were quite complex, with the frequency rapidly changing continuously at short intervals, or irregularly intermittent. Therefore, if one were to create this pseudo-sound of bird calls in an analog manner using resistors, transistors, etc., the circuit configuration would have to be enormous. Particularly in recent years, the integration of clock circuits has been promoted, and such a huge circuit configuration has become a major problem in practical application not only in terms of cost but also in terms of integration.

The purpose of the present invention is to provide a relatively simple circuit configuration.
An object of the present invention is to provide a clock notification sound generating device capable of generating pseudo-sounds such as bird voices.

In order to achieve the above object, the present invention continuously changes the frequency division ratio of a frequency dividing circuit that divides a reference frequency signal to form a frequency signal for notification sound at short intervals, and By the signal of the storage means in which the fundamental pitch frequency signal and the rest period are stored,
It is characterized by generating pseudo-sounds such as bird calls by varying the fundamental pitch frequency and by providing rest periods.

The present invention will be explained below based on the drawings. FIG. 1 is a block circuit diagram illustrating the present invention. Reference numeral 2 denotes a reference signal generation circuit, which is composed of an oscillation circuit 4 and a frequency division circuit 6 that appropriately divides the frequency of the reference frequency signal f ₀ from the oscillation circuit 4 and outputs reference frequency signals f ₁ and f ₂ . The magnitude of the reference frequency signals f ₀ , f ₁ , f ₂ is f ₀ >
The relationship is f ₁ > f ₂ . Reference numeral 8 denotes a variable frequency dividing circuit that divides the reference frequency signal f ₀ to generate a frequency signal for notification sound. The notification sound frequency signal from the variable frequency dividing circuit 8 is passed through an AND gate 10 as a gate means.
The signal is applied to a sound generation circuit 16 comprising an amplifier circuit 12 and a speaker 14 through the amplifier circuit 12 and the speaker 14.

The reference frequency signal f ₂ from the frequency divider circuit 6 is applied to the clock input C of the address counter 18. Output Q ₁ , Q ₂ ... of address counter 18,
Q _o is the input A ₁ of the ROM 20 as a storage means,
It is applied to A ₂ , ..., A _o . The ROM 20 stores data that determines the pause period of the notification sound, the basic pitch frequency of the notification sound, and the repetition period of the notification sound. The address counter 18 counts the reference frequency signal f ₂ , specifies an address in the ROM 20 based on the count value, and transfers the data stored there to the outputs B ₀ , B ₁ , B ₂ ,
It is configured to output from B ₃ , B ₄ , ..., _Bo . Among the plurality of outputs of the ROM 20, data for determining the repetition period of the notification sound is outputted from the output _B0 , and this data is applied to the reset input R of the address counter 18 via the OR gate 22. Data for determining the pause period of the notification sound is output from the output B ₁ , and this data is applied to the other input of the AND gate 10 . As a result, the AND gate 10 is controlled to open and close.
Further, data for setting the notification sound frequency signal to the fundamental pitch frequency is outputted from the output _B2 , and this data is applied to the reset input R of the modulation counter 24. The modulation counter 24 counts the reference frequency signal f ₁ from the middle of the frequency dividing stage of the frequency dividing circuit 6, and outputs the count value to one of the arithmetic circuits 26 via outputs Q ₁ , Q ₂ , ..., Q _o . Input C ₁ , C ₂ ,…
..., applied to _Co. The other inputs D ₁ , D ₂ , ..., Do of the arithmetic circuit 26 are the outputs B ₃ , D _o of the ROM 20 .
B ₄ , . . . , B _o signals are applied via a decoder 28. The outputs B ₃ , B ₄ , . . . , B _o output data for determining the basic pitch frequency signal of the notification sound. The arithmetic circuit 26 receives input C ₁ ,
Calculate the data applied to C ₂ , ..., _Co and the inputs D ₁ , D ₂ , ..., _Do , and output the outputs E ₁ , E ₂ , ..., E
_{The inputs F 1 , F 2} ,
..., F _o , F _o+1 . Variable frequency divider circuit 8
The frequency division ratio is set by the data applied to the inputs F ₁ , F ₂ , . . . , F _o , F _o +1.

On the other hand, numeral 30 is a reference for the clock section 32, which outputs a signal to the control circuit 34 when the set time arrives. The control circuit 34 is configured to cancel the reset of the address counter 18 via the OR gate 22 when the signal from the reference 30 is applied, and further apply an operating signal to the oscillation circuit 4.

FIG. 2 shows a detailed circuit diagram of the arithmetic circuit 26 in FIG. 1. In this embodiment, the arithmetic circuit 26 is composed of an adder circuit. In FIG. 2, the arithmetic circuit 26 includes one half adder 36 and n-1 full adders 38. half adder 3
6 is composed of an exclusive OR gate 40 and an AND gate 42. The signals of inputs C ₁ and D ₁ are applied to the inputs of the exclusive OR gate 40 and the AND gate 42, and the output signal of the exclusive OR gate 40 is outputted to the output E ₁ . Each full adder 38 includes exclusive OR gates 44 and 46, NAND gates 48 and 50, and an OR gate 52. Signals of inputs _{C 2 , C 3 , .} ..., the signal D _o is applied and rotates.
The output signal of exclusive OR gate 44 is applied to one input of exclusive OR gate 46 and NAND gate 48. The other input of the exclusive OR gate 46 and the NAND gate 48 is connected to the OR gate 5 of the full adder 38 for the lower digits.
The output signal of the AND gate 42 of the two or half adder 36 is applied. The output signals of the exclusive OR gate 46 are output E ₂ and
It is output to E ₃ , ..., E _o . Further, the output signals of NAND gates 48 and 50 are both applied to OR gate 52. The output signal of the OR gate 52 of the full adder 38 which outputs the output E _o is output as the output E _{o +1} .

3 shows a truth table for half adder 36 of FIG. 2, and FIG. 4 shows a truth table for full adder 38 of FIG. In FIG. 3, C and D are arithmetic circuits 26
indicates the signals input to the inputs C ₁ and D ₁ of , and E indicates the signal output from the output E ₁ . X indicates the output signal of the AND gate 42, that is, the carry output. In FIG. 4, C and D are the input C ₂ of the arithmetic circuit 26,
Signals input to C ₃ , . _{. .} , _Co and D ₂ , D _{3 , .} X indicates a carry output output from the OR gate 52, and Y indicates a carry signal output from the OR gate 52 of the lower full adder 38 or the AND gate 42 of the half adder 36.

As can be seen from the truth tables in Figures 3 and 4,
The inputs C ₁ , C ₂ , ..., C _o of the arithmetic circuit 26 are input by the half adder 36 and the n-1 full adders 38 .
The binary data applied to D ₁ , D ₂ , ..., D _o is added to each digit at the same time, and the added value is output E ₁ , E ₂ , ..., E _o , E _o+1 Output to.

Fig. 5 is a table showing the contents of data output from B ₀ , B ₁ , and B ₂ of the ROM 20, and Fig. 6 shows changes in the frequency for notification sound based on the data shown in Fig. 5. FIG.

Below, based on the table in Figure 5 and the waveform diagram in Figure 6,
The operation of the circuit shown in the figure will be explained.

When the preset time arrives, the clock section 32
The indicator 30 built in is closed, and the address counter 18 is sent from the control circuit 34 via the OR gate 22.
The signal applied to the reset input R of the
The reset signal changes from "0" to "0" and the reset is released. Further, a signal of "1" is applied from the control circuit 34 to the oscillation circuit 4, and the oscillation circuit 4 starts operating. Then, the address counter 18 counts the reference frequency signal f ₂ from the reference signal generation circuit 2, and when the count value specifies the address "1" of the ROM 20, the output B ₁ and B ₂ signals are "1", and the output B ₀ The signal becomes "0" (corresponding to T ₁ in FIG. 6). This opens the AND gate 10 and clears the count contents of the modulation counter 24. and modulation counter 2
4 starts counting the reference frequency signal f ₁ and applies the count value to the arithmetic circuit 26 . The arithmetic circuit 26 receives the count value of the modulation counter 24 and the output of the ROM 20 applied via the decoder 28.
B ₃ , B ₄ , ..., data for determining the basic pitch frequency signal of the notification sound from B _o are added, and the added value is input to the variable frequency divider circuit 8 F ₁ , F ₂ , ..., _Fo ,
Apply to F _o+1 . The variable frequency dividing circuit 8 sets a frequency dividing ratio based on the added value from the arithmetic circuit 26, and divides the reference frequency signal f ₀ from the reference signal generating circuit 2 to f _A as shown in FIG. Thereafter, the count value of the modulation counter 24 increases as time passes, and the added value applied from the arithmetic circuit 26 to the variable frequency divider circuit 8 also increases accordingly. Therefore, the frequency division ratio of the variable frequency divider circuit 8 also increases, and the frequency division ratio of the variable frequency divider circuit 8 increases.
The frequency for the notification sound output from is decreased. Then, after t ₁ hour has passed from now, the notification sound frequency will be f
_B , and the count value of the modulation counter 24 returns to "0" again. Therefore, the added value from the arithmetic circuit 26 decreases rapidly, the frequency division ratio of the variable frequency divider circuit 8 also decreases, and the notification sound frequency increases to _fA .
After this, the notification sound frequency rapidly changes from f _A to f _B and from f _B to f _A every time t ₁ time elapses.

Then, when address "5" of the ROM 20 is specified by the count value of the address counter 18,
The outputs B ₀ , B ₁ , and B ₂ of the ROM 20 all become "0" (corresponding to T ₂ in FIG. 6). As a result, the AND gate 10 closes and the notification sound stops. From this state, the address counter 18 further counts, and when the count value specifies the address "7" of the ROM 20, the output B ₀ of the ROM 20 becomes "0" and the outputs B ₁ and B ₂ become "1" (Fig. 6). corresponding to T ₃ ). As a result, AND gate 10 opens,
The modulation counter 24 is cleared and starts counting again from the beginning. Then, the count value of the modulation counter 24 and the data signals from the outputs B ₃ , B ₄ , ...B _o of the ROM 20 are added in the arithmetic circuit 26.
The added value is applied to the variable frequency divider circuit 8.
The variable frequency divider circuit 8 has a frequency division ratio set by this added value.
Since the data of the outputs B ₃ , B _{4 ,} .
Therefore, the frequency for the notification sound that is not output from the variable frequency dividing circuit 8 becomes f _C as shown in FIG.
As the count value of the modulation counter 24 increases, the notification sound frequency decreases, as before.
Each time the notification sound frequency decreases to f _D after _one hour t, the count contents of the modulation counter 24 return to the initial value, and the notification sound frequency rapidly increases to f _C .

Furthermore, when the address counter 18 counts and the address "B" of the ROM 20 is specified,
The output B ₀ of the ROM 20 becomes "1", and the outputs B ₁ and B ₂ become "0" (corresponding to T ₄ in FIG. 6). As a result, the address counter 18 is reset, the count contents of the address counter 18 are cleared, and the ROM2
Specify the address "0" for 0. This results in ROM
The outputs B ₀ , B ₁ , and B ₂ of 20 all become "0", the AND gate 10 closes, and the notification sound stops. Then, the address counter 18 counts the reference frequency signal f ₀ again and repeats the above operation.

In this way, according to this embodiment, the variable frequency divider circuit 8
Continuously vary the frequency division ratio at short intervals, and
Based on the data of the basic pitch frequency and rest period of the bird's voice, etc., stored in the ROM 20, it is possible to generate a pseudo sound of a bird by varying the basic pitch frequency and providing a rest period. Furthermore, since the circuit according to this embodiment is simple, the cost is low.
Furthermore, since it is composed of a completely digital electronic circuit, it is easy to integrate.

Note that in this embodiment, the reference signal generation circuit 2
was newly provided for the notification sound, but it is also possible to use the clock's oscillation circuit and frequency dividing circuit. Further, in this embodiment, the present invention is applied to an analog display electronic timepiece, but it is also possible to implement the present invention to a digital display electronic timepiece that does not have a guide.

As described above, according to the present invention, the frequency division ratio of the variable frequency divider circuit that forms the notification sound frequency signal is continuously changed at short intervals, and the rest period signal from the storage circuit and a plurality of basic pitches are By setting a pause period or changing the basic pitch frequency depending on the frequency signal, it is possible to produce sudden changes in frequency over a short period of time, which are characteristic of bird voices, or irregularly intermittent bird onomatopoeia. As a result, a pleasant notification sound can be obtained. Furthermore, since the circuit configuration can be realized using a simple digital circuit, integration is easy and cost increase can be suppressed.

[Brief explanation of the drawing]

Figure 1 is a block circuit diagram showing the present invention, Figure 2 is a detailed circuit diagram of the arithmetic circuit in Figure 1, and Figure 3 is a detailed circuit diagram of the arithmetic circuit in Figure 1.
The figure shows the truth table for the half adder in figure 2, and figure 4 shows the truth table for the half adder in figure 2.
FIG. 5 is a truth table of the full adder shown in the figure, FIG. 5 is a table showing the contents stored in the ROM, and FIG. 6 is a waveform diagram showing changes in the notification sound frequency based on the data shown in FIG. 5. 2... Reference signal generation circuit, 8... Variable frequency dividing circuit, 10... AND gate, 16... Sound generation circuit,
18... Address counter, 20... ROM, 2
4...Modulation counter, 26...Arithmetic circuit, 30...
...Approximately 32...Clock part.

Claims (1)

[Scope of Claims] 1. Reference signal generation means that starts operating at a preset time and generates a plurality of reference frequency signals; and variable frequency division means that variably divides the reference frequency signal of the reference signal generation means. , a sound generating means for generating a notification sound based on the output signal from the variable frequency dividing means; a storage means storing at least a signal for setting a rest period of the notification sound and a basic pitch frequency of the notification sound; and the reference. address counter means for specifying an address in the storage means by a reference frequency signal from the signal generation means and sequentially calling the contents; and address counter means for counting the reference frequency signal from the reference signal generation means and repeatedly counting at a shorter cycle than the address counter means. a modulation counter means for calculating a count value from the modulation counter means and a fundamental pitch frequency signal from the storage means,
calculation means for supplying the frequency division ratio after the calculation to the variable frequency division means; and a calculation means connected between the variable frequency division means and the sound generation means, and responsive to the rest period signal from the storage means, An alarm sound generation device for a watch, comprising: gate means for preventing the output signal from the frequency dividing means from being applied to the sound generation means.