JPS6232316Y2 - - Google Patents
Info
- Publication number
- JPS6232316Y2 JPS6232316Y2 JP18265678U JP18265678U JPS6232316Y2 JP S6232316 Y2 JPS6232316 Y2 JP S6232316Y2 JP 18265678 U JP18265678 U JP 18265678U JP 18265678 U JP18265678 U JP 18265678U JP S6232316 Y2 JPS6232316 Y2 JP S6232316Y2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- input signal
- flip
- voltage
- flop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Description
【考案の詳細な説明】
本考案は分周装置に関し特にフリツプフロツプ
回路を用いて楽音信号の重低音付加効果をなす音
響機器に好適な分周装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency dividing device, and more particularly to a frequency dividing device suitable for audio equipment that uses a flip-flop circuit to add deep bass to a musical tone signal.
音響機器においてはレコード再生音等の楽音信
号に重低音を付加して低音効果を高めることが行
われる。そのために重低音付加装置が用いられる
が、かゝる装置においては、楽音信号の最低音の
1/2の周波数信号をフリツプフロツプ等を用いて
発生させ、これをその最低音の振幅に比例した振
幅に制御して原音の楽音信号に付加する方式があ
る。この場合、フリツプフロツプの分周出力は電
源電圧が一定であれば振幅も一定となるから、当
該出力を振幅制御回路を設けてコントロールする
必要があり、そのために回路構成が多くなる欠点
がある。 2. Description of the Related Art In audio equipment, heavy bass is added to a musical sound signal such as a record playback sound to enhance the bass effect. For this purpose, a deep bass adding device is used, but in such a device, the lowest tone of the musical tone signal is
There is a method of generating a 1/2 frequency signal using a flip-flop or the like, controlling the amplitude to be proportional to the amplitude of the lowest note, and adding it to the original musical tone signal. In this case, since the frequency-divided output of the flip-flop has a constant amplitude if the power supply voltage is constant, it is necessary to provide an amplitude control circuit to control the output, which has the disadvantage of requiring a large number of circuit configurations.
本考案の目的はフリツプフロツプの如き分周出
力振幅が電源電圧に比例する分周器の出力振幅を
極めて簡単な構成によつて入力信号レベルに対応
させることが可能な分周装置を提供せんとするこ
とである。 An object of the present invention is to provide a frequency dividing device that can make the output amplitude of a frequency divider, such as a flip-flop, whose divided output amplitude is proportional to the power supply voltage correspond to the input signal level with an extremely simple configuration. That's true.
本考案の分周装置は分周すべき入力信号のレベ
ルに応じた直流電圧を発生する手段を有し、この
直流電圧を分周器の電源電圧に用いることを特徴
とするものである。 The frequency divider of the present invention is characterized in that it has means for generating a DC voltage according to the level of the input signal to be frequency divided, and that this DC voltage is used as the power supply voltage of the frequency divider.
従つて、本考案によれば単に入力信号を整流す
る整流回路を付加するだけで分周出力振幅が入力
信号レベルに対応するようになり、特に重低音付
加装置に用いて好適となる。 Therefore, according to the present invention, by simply adding a rectifier circuit for rectifying the input signal, the frequency-divided output amplitude can correspond to the input signal level, and it is particularly suitable for use in a deep bass adding device.
以下本考案について図面を用いて説明する。 The present invention will be explained below with reference to the drawings.
第１図は本考案の実施例を示す回路図であり、
分周されるべき入力信号ａは整流ダイオードD1
及び平滑コンデンサC1よりなる直流電圧発生回
路１によつて直流電圧ｂに変換される。当該電圧
ｂはエミツタフオロワトランジスタQ1のエミツ
タからフリツプフロツプ３の正電圧印加端子に加
えられる。 FIG. 1 is a circuit diagram showing an embodiment of the present invention,
The input signal a to be divided is the rectifier diode D 1
and is converted into a DC voltage b by a DC voltage generation circuit 1 comprising a smoothing capacitor C1. The voltage b is applied from the emitter of the emitter follower transistor Q1 to the positive voltage application terminal of the flip-flop 3.
入力信号ａはまたアンプ２により増幅後、直流
阻止用コンデンサC2を介してトリガダイオード
D2及びD3へ印加される。尚、抵抗R1及びR2はダ
イオードD2，D3のバイアス用である。そしてフ
リツプフロツプ３は一対のトランジスタQ2及び
Q3、抵抗R3〜R8及びコンデンサC3，C4より成る
周知の構成であり、この一対のトランジスタのベ
ースへトリガダイオードD2及びD3を介して入力
信号がトリガ入力として印加される。 Input signal a is also amplified by amplifier 2 and then sent to trigger diode via DC blocking capacitor C2 .
Applied to D 2 and D 3 . Note that the resistors R 1 and R 2 are for biasing the diodes D 2 and D 3 . Flip-flop 3 consists of a pair of transistors Q 2 and
Q 3 , resistors R 3 to R 8 and capacitors C 3 and C 4 are well-known configurations, and an input signal is applied as a trigger input to the bases of this pair of transistors via trigger diodes D 2 and D 3 . .
第２図は第１図の各部動作波形を示し上側は入
力信号ａの振幅がやや小なる場合、下側はやや大
なる場合を示している。そして両図において同等
符号は同一部分の信号波形である。 FIG. 2 shows the operation waveforms of each part of FIG. 1, and the upper side shows the case where the amplitude of the input signal a is slightly smaller, and the lower side shows the case where the amplitude is slightly larger. In both figures, the same symbols indicate the signal waveforms of the same parts.
図からも明白な如く、フリツプフロツプ３の分
周出力振幅は入力信号ａのそれに比例して変化す
ることがわかる。尚、第１図においては、フリツ
プフロツプ３の負電源印加端子には負電源Ｅが加
えられて出力振幅を所望の大きさにしている。 As is clear from the figure, the frequency-divided output amplitude of the flip-flop 3 changes in proportion to that of the input signal a. In FIG. 1, a negative power supply E is applied to the negative power supply terminal of the flip-flop 3 to adjust the output amplitude to a desired level.
このように、本考案によれば極めて簡単な構成
でフリツプフロツプの分周出力を入力信号レベル
に応じて制御することができ、よつて音響機器の
重低音付加装置の小型化が可能となる。また重低
音付加装置に限らずシンセサイザ等の信号発生器
のレベルコントロール装置に用いることもできる
ことは勿論である。 As described above, according to the present invention, the frequency-divided output of the flip-flop can be controlled in accordance with the input signal level with an extremely simple configuration, thereby making it possible to downsize the deep bass sound adding device for audio equipment. Moreover, it goes without saying that the present invention can be used not only as a deep bass adding device but also as a level control device for a signal generator such as a synthesizer.
尚、上記実施例においては、分周器としてフリ
ツプフロツプを用いたが、その分周出力振幅が印
加電圧に比例する如き分周器であれば他のものを
用いてもよいことは勿論である。 In the above embodiment, a flip-flop is used as the frequency divider, but it goes without saying that other frequency dividers may be used as long as the divided output amplitude is proportional to the applied voltage.
第１図は本考案の一実施例を示す回路図、第２
図は第１図の動作波形図である。
主要部分の符号の説明、１……直流電圧発生回
路、３……フリツプフロツプ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is an operational waveform diagram of FIG. 1. Explanation of the symbols of the main parts: 1...DC voltage generation circuit, 3...Flip-flop.
Claims (1)
幅が電源電圧に比例する分周器と、前記入力信
号のレベルに応じた直流電圧を発生する手段と
を含み、前記直流電圧を前記分周器の電源電圧
に用いることを特徴とする分周装置。 (2) 前記分周器はフリツプフロツプ回路であるこ
とを特徴とする実用新案登録請求の範囲第１項
記載の分周装置。[Claims for Utility Model Registration] (1) A frequency divider that divides an input signal frequency and whose divided output amplitude is proportional to a power supply voltage, and means for generating a DC voltage according to the level of the input signal. A frequency dividing device characterized in that the DC voltage is used as a power supply voltage of the frequency divider. (2) The frequency dividing device according to claim 1, wherein the frequency divider is a flip-flop circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18265678U JPS6232316Y2 (en) | 1978-12-29 | 1978-12-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18265678U JPS6232316Y2 (en) | 1978-12-29 | 1978-12-29 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5599582U JPS5599582U (en) | 1980-07-10 |
| JPS6232316Y2 true JPS6232316Y2 (en) | 1987-08-18 |
Family
ID=29194330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18265678U Expired JPS6232316Y2 (en) | 1978-12-29 | 1978-12-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232316Y2 (en) |
-
1978
- 1978-12-29 JP JP18265678U patent/JPS6232316Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5599582U (en) | 1980-07-10 |
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