JPS6231071A - Error detecting and correcting system - Google Patents

Abstract

PURPOSE:To effectively detect a data error which cannot be detected in an error correcting processing of a preceding stage by adding an error detecting code for detecting the data error of a pattern which cannot be corrected by an error correction to the original data before encoding the error correction. CONSTITUTION:The data DT after an error is corrected is added to a syndrome producing circuit 41 based on a square matrix A and the syndrome produced by the circuit 41 is once stored in a syndrome register 42. An output of a register 42 is added to the circuit 41 and to an error deciding circuit 43. Every time the data DT is added the syndrome S is newly calculated and successively added to the error deciding circuit 43. A control part 44 synchronizes with a timing signal TM 2 to start an operation, clears the register 42 immediately before the data DT is inputted and operates the error deciding circuit 42 synchronously with the timing in which the data DT of one sector is completed to be inputted. In this way, the error deciding circuit 43 outputs an error signal ER 2 when the value of the syndrome is other than zero.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an error detection and correction method applied to a data processing device that processes data in a fixed format.

[Prior Art] Generally, PCM (Pulse Code Modula
When recording, reproducing, and transmitting digital code data such as data modulated by tion), defects or scratches on the recording medium used to transmit data from the recording side to the reproducing side, or dust or dirt attached to the surface, etc. , due to noise or signal deterioration in the transmission path between the sending side and the receiving side, the data output from the data sending side may be input to the data receiving side in an error state. Occurs often.

For example, the following measures have been taken in the case of optical disk devices, which have recently been proposed to be used as auxiliary storage devices or external storage devices for computer systems due to their large storage capacity.

This optical disk device uses as a storage medium an optical disk in which a photoreactive recording residual amount is formed into a disk shape. On the surface of the optical disk, there are many recording tracks with a width of about 1 μm at a track pitch of about 1.5 μm. It is formed.

Then, information pits corresponding to the information to be stored are written directly onto the above-described recording track using a laser spot narrowed to a minute diameter of about 1 μm. The storage capacity of this optical disc is approximately 300I11 in diameter, and each disc has a storage capacity of 101
It is approximately 1 to 1012 bits.

On the other hand, since optical disks are capable of high-density storage, random positive errors are likely to occur in data due to defects during disk molding or dirt and dust attached after molding.

Furthermore, there is a high possibility that large burst errors will occur due to scratches or the like left after data recording.

As countermeasures against these errors, defects at the time of disc formation are inspected after the disc is formed and sectors with defects are not used, and data is reproduced immediately after data is recorded to detect errors.

Reliability of reproduced data can be improved by re-recording in other sectors.

However, the bit error rate of the disk itself is 10″″
Since the rate is as high as 4 to 10''5, it is not preferable to remove sectors with even a 1-bit error because the recording efficiency will drop markedly.

Therefore, in order to improve the reliability of data recording and reproduction, so-called error correction is performed.

FIG. 11 shows an example of a method for performing error correction in units of one sector. In fig.

The l sector consists of 7 frames, and each frame has 10 words (Wx to Wto) of data.

In this case, horizontally (i.e. word forward in the frame)
CRCC (Cyclic Rsdundancy)
Check Cods) are added, and parity words P and Q based on a b-adjacency code (b-adjac-nt code) are added in the vertical direction (that is, in the forward direction of the frame for words at the same position in the frame).

In this example, the error position in the vertical direction is detected by checking whether there is an error in each frame using CRCC, and the word at this error position can be corrected by referring to the parity words P and Q (single error). correction).

However, the b-adjacent code has the ability to correct only one word error, and in CRCC, the frame has only one word error correction capability.
Since it is only possible to determine whether there is an error of more than one bit, if a burst error occurs in three frames in one sector or a random error occurs in three different frames, the error correction function is not performed at all.

Therefore, an error correction method with double interleaving has been proposed by the same applicant as an error correction method having high correction ability for both burst errors and random errors (Japanese Patent Application No. 58-247431). (see issue).

This error correction method divides and arranges sectors of data to be recorded and reproduced sector by sector on a recording medium into frames each having an information word and two sets of parity. A first correction sequence is formed by interleaving to form a first correction sequence, and a set of parities for this first correction sequence is formed, while completing in a direction different from the first correction sequence and within a sector. By interleaving to form a second correction sequence, and adding a set of parity to this second correction sequence, random and burst errors occurring in the data are corrected.

According to this error correction method, the word error rate before correction is reduced to 1
If the value is 0''''4, the word error rate can be reduced to about 10-1 times after correction, for example, for random errors.

However, in this error correction method, although the error correction ability is large as mentioned above, the error detection ability to detect that an error has occurred in the corrected data is as low as the error correction ability of about 1710. This resulted in the disadvantage that the error rate of the contact data was relatively high.

Note that in order to resolve this inconvenience, it is possible to add CRCC to the original data as in the past, but while this CRCC has a very high ability to detect burst errors, it also suffers from random errors. The detection ability is not very high. Therefore, there is a problem in that the effectiveness of error detection is small for discs that generate many random errors, such as optical discs.

[Objective] The present invention has been made in order to eliminate the above-mentioned disadvantages of the prior art, and provides an error detection and correction system with high error detection capability.

In order to achieve this object, the present invention adds an error detection code that detects a pattern of data errors that cannot be corrected by error correction to the original data before being encoded into an error correction code. It is possible to reliably detect data errors that could not be detected by error correction processing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 illustrates a data recording format on an optical disc according to an embodiment of the present invention.

On the track TR of the optical disc, sectors SC are arranged consecutively via gaps GP, and each sector SC has a preformat part PF consisting of a preamble, a sector synchronization signal, and a sector address signal, and 256 data frames DF. It consists of a data section consisting of a set.

Further, the data frame DF includes a preamble, a frame synchronization signal, 8 data words, and 2 sets of parity words P I T Q 1t P z + 02
It is composed of 12 words of recording data (described later).

It should be noted that each word of the recording data section is composed of 8 bits long.

In this way, 256 consecutive data frames DF are recorded in sector SC, and 2048 words are recorded. In addition, in this embodiment, as shown in FIG. 2, the last 1 byte of the final frame of the 1 sector worth of data is used as a parity word R for error detection, and the parity word R is calculated by the following formula ( It is calculated by I).

R:A"-"DzΦA"-"D2Φ...eADn-t
”(I) However, n is the number of words in one sector, that is, 2o48, Di is the i-th data in one sector, and A is a square matrix calculated by the following equation (II). Also, the operator e is modulo 2 Hail the addition of.

Further, terms b1 to b7 of this square matrix A are respective coefficients (values are O or 1) of an 8th order generator polynomial 〇(X) expressed by the following equation (m).

G(X)=X"+b7X'+b6X'+bsX"+b
4X'+b3X3+bzX2+btX+1...
(m) For example, coefficients bt, bz, b3. b4. bs, b6. b
When 7 is set to 0.0, 1, 0, 1, and 0.1, respectively, the square matrix A becomes as follows.

Furthermore, in this embodiment, in order to suppress the influence of burst errors, the original recorded data (hereinafter referred to as optical data) including the parity word R7 as described above is interleaved to form the recorded data of the data frame OF. There is.

That is, first, the original data of 2048 words is divided into 256 groups of 8 words each in the order of arrangement, and parity words P and Q of b-adjacent codes are added to each group.

Then, interleaving is performed so that the data word of the 5th group in the original data is placed in the word 111k of the Nth frame. However, H is expressed by the following formula (TV).

A=L+14 X (k-1) ・・・・・・(I
V) Also, the parity words P and Q of the Lth group are:

parity word P of the (L+LL2)th frame, respectively.
2) Place it in the parity word Q2 of the (L+126)th frame.

Note that when X exceeds 256, the value obtained by subtracting 256 from k is used as the value, so that this interleaving is completed within the same sector SC. Further, when selecting the positions of parity words P and Q (P2.Q2), similar processing is performed so that the selection is completed within the same sector.

Therefore, for example, the first word of the first group becomes the word v1 of the first frame, the second word becomes the word w2 of the 15th frame, the third word becomes the word v3 of the 29th frame, and the fourth word becomes the word v3 of the 43rd frame. The 5th word is in word v4 of the frame, the 5th word is in word lll5 of the 57th frame, and the 6th word is in word v4 of the 57th frame.
The word v6 is in the 71st frame, the 7th word is v7 in the 85th frame, and the 8th word is v6 in the 99th frame.
In word w6 of the frame, parity word P is the 113th word
The parity word Q is allocated to the parity word P2 of the frame, and the parity word Q is allocated to the parity word Qz of the 127th frame.

Table 1 below shows representative interleaving of each word in other groups.

In addition, each number in the table indicates the corresponding frame number, and P(2) and Q(2) in the word column indicate the parity words P and Q for each group and the parity word P2 of each data frame. ．． It's raining Q2.

2 In this way, the original data of 2048 words is stored in one sector SC interleaved every 14 frames with parity words P and Q based on b-adjacent codes added every 8 words.

Furthermore, the data in one sector formed in this way is selected (that is, interleaved) in a direction different from the data recording direction and the original data arrangement direction to form a 01 correction sequence, and the adjacent code is Parity word P1. Add Qt. In contrast to this 01 correction sequence, hereinafter, a sequence of original data and parity words P and Q (Pz, Qz) will be referred to as a 02 correction sequence.

For example, the 01 correction sequence consists of words v1 to 8 and parity words Pz+Qz that are interleaved and selected every 11 frames, and parity words P1 . The positions of parity words Px and Qx are set 11 frames and 22 frames after parity word Q2, respectively.

Further, this 01 correction sequence is also formed by connecting the 256th frame and the first frame so that it is completed within one sector SC.

The arrangement of the 01 correction series and 02 correction series described above is shown in FIGS. 3 and 4.

As shown in the figure, two correction series (C1 correction series and C2 correction series) are set in different directions that intersect data recording.

In the above example, the 01 correction sequence is formed by interleaving every 11 frames, and the C2 correction sequence is formed by interleaving every 14 frames.

This interleaving interval is not limited to this. Further, the interleaving interval of the C1 correction sequence may be made larger than the interleaving interval of the Cz correction sequence.

Further, although the 02 correction series and the original data are arranged in the same direction, it is not necessary that the directions are the same. For example 1
The direction in which the original data is arranged may be the same as the data recording direction, and the C2 correction sequence may be used as the direction in which parity words P2 and Q2 are added.

Now, parity words P, Q (Px) by b-adjacent codes.

Ql;P2. Q2) is generated as follows.

That is, if the number of words constituting the correction series is n (n=10 for Cz correction series; n=8 for Cz correction series), then parity words P and Q are expressed by the following equations (V) and (VI
). In the following, the data word D (1≦i≦n) refers to the words forming each correction series.

P:ΣDi...(V)i
= 1 Q = ΣT" Di ... (VI) i = 1 Here, T is the word length (number of bits) (b +
1) It is a square matrix consisting of a primitive polynomial 〇(X) with elements of terms. In this example, since the l word is 8 bits, the primitive polynomial 〇(X) and the square matrix T are defined as follows.

According to this b-adjacent code, error correction of one word in a correction sequence (single-error correction) is possible, which will be explained next.

That is, when the recorded data is read out, it is assumed that the data word Di and parity words P and Q that make up the correction sequence contain errors, and if the respective error patterns are ei, 81', and eQ, then Data word Di' and parity words P', Q' are given by the following equation.

Dl'=DlΦei ......(IK)P'
=Peep ”...(X)Q' =Qeeo
-...(X[) Here, syndrome Sp, S defined by the following formula.

think of.

SP=ΣDlΦP' -------Ca
mi=0 (=ΣTn−LD, l■Q′ ・・・・・・(x
m) In other words, the syndrome Sr is based on each data word Di' and parity word P of the correction series related to the read data.
The syndrome So is the result of adding each term of each data word Di' weighted by a square matrix T and the parity word Q' all modulo 2.

Now, considering the case where the data word D1' and parity words P' and Q' in the correction sequence are all error-free, Dl''=05 P'=P, Q'=Q, so from the definition Both syndromes SP and SQ become 0.

Therefore, if the values of syndromes SP and SQ are both O, it can be determined that there is no error in this correction series.

Next, consider the case where an error ek occurs in the data word Dk' of the data word Diy.

The syndromes SP and SQ in this case are as follows.

SP:. , ・・・・・・(XIV)S
o=T"ek""(X V) By eliminating 8k from the above two equations, the position k of the error word can be found in a linear manner.

5o=T"SP... (XVI) That is, according to this formula (XVI), the syndrome Sp has a matrix Tn"
``1'' is sequentially multiplied to produce a matching matrix ``Tfi''''I
k can be known from the number of cars.

At this time, since the error pattern ek appears in the syndrome SP, the data word Dk' can be corrected using a linear equation.

Dk=Di'Φek''...(X■) Note that when errors occur in each of the parity words P'' and Ql, the following equations hold true.

That is, if one of the syndromes is O, an error has occurred in the parity word for calculating the other syndrome, and each error pattern is a value of the syndrome other than 0.

In this way, one word errors within the correction sequence can be corrected.

Therefore, considering the 01 correction series, since the data words that make up the C1 correction series are interleaved every 11 frames, it is assumed that consecutive burst errors occur within 11 frames.

However, since the error is only a one-word error from the perspective of the 01 correction series, the error can be corrected by the procedure described above.

Furthermore, since the 02 correction sequence is interleaved every 14 frames, even if consecutive burst errors occur within 14 frames, the errors can be corrected in the same manner as the 01 correction sequence.

Note that if the frame interval (interleave interval) of each word of each correction series is lengthened, the burst error correction ability can be increased proportionally, but if the interleave interval is not long, burst errors occurring at multiple locations will be The probability that two or more errors will be mixed in the same correction sequence increases, and the possibility that error correction will not be possible increases, so the interleaving interval is set taking both of these into consideration.

Now, in this way, in the C1 and C2 correction series, it is possible to correct a 1-word error that occurs within the same correction series, but if a 2-word error occurs, it means that an error has occurred. Although the error can be detected, the error cannot be corrected because the location cannot be detected.

Furthermore, even though a two-word error has occurred in the correction series, it may be assumed that a one-word error has occurred, and the word may be incorrectly corrected. Such erroneous corrections are made in the following cases, and as a matter of course, even the occurrence of an error is not detected in these cases.

(2) An error occurs in the data words Di and Dj, but since the error patterns ei and 6J are equal, the syndrome Sr becomes 0, and it is determined that an error has occurred in the parity word Q.

ei=eJ≠0 5p=eieeJ=O 3q=T"-1eiΦT"-'ej≠0■ An error occurred in the data word D + DJ, but since the syndrome So becomes O, an error occurs in the parity word P. If it is determined that the

1f-ej Sp=ehΦeJ≠0 3o=T"eiΦT"-'ej=0 ■ Both syndromes are not O, but an error has occurred in one data word Dk other than the data word Dl and DJ in which the error has occurred. If it is determined that

5P=et■eJf-O 3o=T”etΦTn-je4≠0 5o=T”ΦSp (1≦to≦n) “”(XX)
That is, there is a case in which k happens to satisfy equation (XX) in the correction sequence, and the correct data word Di
is incorrectly corrected, and the data word D containing the error, DJ, is not corrected.

Note that even if syndromes Sp and SQ both become 0 even though an error of 3 or more words has occurred, no error is detected. That is, for example, when an error occurs in the data words Di, Dj and the parity word Q.

5P=eiΦe4=0 So=T"-'eieT"-'ejΦeo=0However,
If the data word Di determined to have caused an error in the above case (■) is not in the correction sequence, that is, k=o
Or if n<k.

It can be clearly determined that an error of two words or more has occurred.

Of the cases ~■ described above, the probability of cases ■ and ■ is relatively high, so if it is possible to detect that a data error has occurred in these cases, it will be possible to prevent data from being output with an error. Ru.

Now, in the present invention, as described above, data errors that could not be detected in each correction series are detected by referring to the parity word R.

That is, for the data word Di' output after being subjected to error correction processing using each correction sequence as described above,
Consider the following syndrome SR.

5R=A'-1Dt'■A"-"Dz'■"・ΦAD+
-1'eDn''' (XXI) However, data word D0' is parity word R.

Now, assuming that there is no error in each data word Di', (the following is a blank space) 1) 1'=Dt (1≦1≦mouth) DnI:R...(XXIl) =A"-'D+ΦA", −” D2 ■・・・ΦAD
n −1 tonalnote, Collellano formula (X XI)j (X
According to The value becomes non-zero.

Now, considering the case described above as an example of a data error not detected by each of the correction sequences described above, in this case, the error patterns e i + e J occurring in the two data words DL and DJ are equal. Also, as mentioned above, one data frame in the final 02 correction series is composed of 8 data words, so if the frame number in the 02 correction series is k, then i=8 umbrellas +i, j
=8 umbrellas i(+j, therefore, syndrome SR
is of first order.

sR: An-(e-zai-ni+i)8. Φ An-(I
l*+i).

Therefore, syndrome SR can be rewritten as follows.

SR= A"-8*'(8-' Φ A-
' ) e=-(xxnr) This formula (
In order for the syndrome SR value of XXIII) to become 0, the square matrix A must be a unit matrix.

In this case, square matrix A is not a unit matrix.

As described above, it is possible to reliably detect errors when two identical error patterns occur.

In addition, as another example of a data error that is not detected by the above-mentioned correction sequence, consider the case (■) mentioned above. In this case, it is determined that an error has occurred in the parity word P, so an error has occurred. The data word is output to the next stage without its errors being removed.

At that time, an error has occurred in the data words Di, D=.

T7-iei @T7-' ej=O.

If there is a relationship, the syndrome SR at this time
becomes as follows.

SR= A"-'Zai'(A-'T'-'
(CI A-j)ei ・”””(XXIV) In order for the syndrome SR value of this formula (X Since the square matrices A and T are not equal, the syndrome SR will never become 0, and such data errors can be reliably detected.

Further, in order to detect such data errors, the square matrix A is made different from the square matrix T, and in particular, the shift direction of each bit of the data word is reversed to make the difference noticeable.

Note that, as described above, the square matrix A does not need to be equal to the square matrix T, so it is sufficient that the primitive polynomials G(X) forming the basis thereof are different, and the shift direction of each bit of the data word may be the same. Alternatively, the primitive polynomial G(X) may be the same, but the shift direction of each bit of the data word may be reversed.

As described above, most of the data errors that are not detected by error correction using the C1 and C2 correction sequences can be detected by the error detection processing using the parity word H, so that the data after error correction is It is possible to reliably prevent output from containing errors.

Furthermore, according to a computer simulation carried out by one of the inventors, when the word error rate before correction is 6m, the probability Pwd of an error included in a data word after being processed by the error detection and correction method according to the present invention is at least It was determined that the value is smaller than the value of the following formula (xxV).

Pwa = 1.4 x 1O-1X e'
”(XXV) This value is about 1/10,000 of the probability of an error contained in a data word after error correction processing using the C1 and C2 correction sequences. It can be seen that the detection effect is quite large.

FIG. 5 shows an example of a recording data encoding device according to the present invention.

In the figure, record data RD output from a data generator (path shown) is divided into 2047 word units and sequentially input to an R parity addition circuit 10, to which a parity word R based on the above-mentioned square matrix A is added. So, P2
．． It is output to the Q2 parity addition circuit 11.

P2. The Q2 parity adding circuit 11 adds a parity word P2?02 based on the above-mentioned square matrix T to every eight successive words of the received data words, and sequentially outputs them to the interleave memory 12 for storage.

The data words stored in the interleave memory 12 in this way are the words of the C1 correction series Pl,
Input to the OL parity addition circuit 13, Pt, (h)
<The parity adding circuit 13 adds the parity words Pi, Q to each successive 10 received data words.
1 is added, and sequentially output to and stored in the interleave memory 14.

In this way, the recorded data is finally stored in the interleave memory 14, and is sequentially outputted to the optical disk drive device 15 for each data frame, and is sent to the optical disk (path shown).
is memorized.

An example of the R parity addition circuit 10 will be described next.

In the figure, recording data RD is applied to one input terminal of a selector 21 and an R parity generation circuit 22.

The R parity generation circuit 22 generates a parity word R based on the input recording data RD of 2047 words, and its output is applied to the other input terminal of the selector 21.

The control unit 23 operates in synchronization with a timing signal TMI output from a controller (not shown), and clears the R parity generation circuit 22 to the initial state immediately before the transfer of the recording data RD for sectors is started. While the 2047 words of recording data RD are being added, the selector 22
The R parity generation circuit 22 selects the recording data RD and synchronizes with the output timing of the 2048th word.
select the output data.

In this way, the parity word R is output following the 2047 words of recording data RD.

As mentioned above, the parity word R is generated by a square matrix A. This square matrix A is defined as data word D=[a
t, az, a3. a4. as, as, a7. Considering the case where it is applied to ael, the data word D"=[bx, bz, b3.b4.bs, bs,
bt and bel are as follows.

Therefore, the configuration of the R parity generation circuit 22 is as shown in FIG.

In the figure, each bit of recording data RD is modulo 2
Exclusive OR circuits 101 to 1 forming the adder circuit of
Each is applied to one input terminal of 0g.

Note that the first bit of the recording data RD is assumed to be LSB, and the eighth bit is assumed to be MSB.

The outputs of the exclusive OR circuits 101-108 are temporarily stored in the parity register 109.
As for the output of 09, the 1st bit data (LSB) is added to one input terminal of exclusive OR circuits 110, 111, and 112, and the 2nd bit, 4th bit, and 6th bit data are respectively exclusive. It is added to the other input terminals of OR circuits 110, 111, and 112.

Also, the 1st bit data of the parity register 109 (
LSB) is the 8th bit data (M
SB) is output to the next stage and is added to the other input terminal of the exclusive OR circuit 108, and the exclusive OR circuit 11
The output of 0 is the 1st bit data (L
SB) to the next stage and is also output to the exclusive circuit 10.
1, and the third bit data of the parity register 109 is output to the next stage as the second bit data of the parity word R, and is also added to the exclusive OR circuit 102, and the output of the exclusive OR circuit 111. is output as the third bit of parity word H to the next stage and is added to the other input terminal of exclusive OR circuit 103, and the fifth bit of parity register 109 is output as the fourth bit of parity word R. The output of the exclusive OR circuit 104 is outputted as data to the next stage and added to the exclusive OR circuit 104, and the output of the exclusive OR circuit 112 is output to the next stage as data of the 5th bit of the parity word R and is added to the exclusive OR circuit 105. It is added to the other input terminal, and the parity register 109
The 7th bit data of parity word R is outputted to the next stage as the 6th bit data of parity word R, and is also added to the other input terminal of exclusive OR circuit 106, and is input to parity register 1.
The 8th bit data of 09 is output to the next stage as the 7th bit data of the parity word R, and is also applied to the other input terminal of the exclusive OR circuit 107.

In this way, exclusive OR circuits 110, 111, 112
By rearranging the digits of each bit of the parity register 109, the function of the square matrix A is realized.

Note that the stored contents of the parity register 109 are cleared by a clear signal CL output from the control section 23.

Further, when generating the parity word R, a square matrix A' whose shift direction is opposite to the square matrix A described above can be used. This square matrix A' can be expressed, for example, as follows.

Now, define this square matrix A' as data word D=[at.

a2. a3. a4. as, as, at, ae], the data word D''jl=[bl.

bz, b+, b4. bs, b6. bt, bs] is as follows.

An example of the R parity generation circuit in this case is shown in FIG.

In this figure, the same parts and corresponding parts as in FIG. 7 are designated by the same reference numerals, and the explanation thereof will be omitted.

In this R parity generation circuit, the parity register 109
As for the output of It is added to the other input terminals of sum circuits 110, 111, and 112.

Also, the 8th bit data of the parity register 109 (
The MSB) is output as the LSB of the parity word R to the next stage and is added to the other input terminal of the exclusive OR circuit 101, and the 1st bit data (LSB) of the parity register 109 is the 2nd bit of the parity word R. is output as data to the next stage and also to the exclusive OR circuit 102.
The 2nd bit data of the parity register 109 is applied to the other input terminal, and is output to the next stage as the 3rd bit data of the parity word R.
The output of the exclusive OR circuit 110 is output to the next stage as the 4th bit data of the parity word R, and is also applied to the other input terminal of the exclusive OR circuit 104. The 4th bit data of the register 109 is output to the next stage as the 5th bit data of the parity word R and is also added to the other input terminal of the exclusive OR circuit 105, and the output of the exclusive OR circuit 111 is the parity word R. The data of the 6th bit of the parity register 109 is outputted to the next stage as the data of the 6th bit of the parity word R, and is added to the other input terminal of the exclusive OR circuit 106. It is output to the next stage and added to the other input terminal of the exclusive OR circuit 107, and the output of the exclusive OR circuit 112 is output to the next stage as the 8th bit data (MSB) of the parity word R. It is added to the other input terminal of the exclusive OR circuit 108.

Next, an error detection and correction device that detects and corrects data errors contained in data reproduced from an optical disc will be described.

FIG. 9 shows an example of an error detection and correction device.

In the figure, reproduced data reproduced from an optical disk (not shown) by an optical disk drive device 31 is stored in a dinterleave memory 32 in the order of CI correction series.

The data stored in the dinterleave memory 32 is sequentially read out by the decoder 33 and subjected to the above-described error correction process using the CI correction series, and the data after the error correction process is stored in the dinterleave memory 34. The data are stored in the order of 02 correction series.

The data stored in the dinterleave memory 34 in this way is sequentially read out by the decoder 35 and subjected to the above-described error correction processing using the 02 correction series, and the data DT after the error correction is used for the next stage of signal processing. The data are sequentially output to a device (eg, a host computer device, etc.) and an error detection circuit 36.

Furthermore, when the decoder 35 detects an uncorrectable data error, it outputs an error signal ERI.

This error signal ERI is applied to one input terminal of the OR circuit 37.

The error detection circuit 36 detects a data error using the parity word R described above, and outputs an error signal ER2 to the OR circuit 37 when a data error is detected.

The output of this OR circuit 37 is sent to the above-mentioned signal processing device.
A data error signal is added to indicate that an error has occurred in the sector data being read.
As a result, the signal processing device discards or re-inputs the input data.

In this way, one sector worth of reproduced data is error-corrected, and data errors that were not detected by the error correction are detected.

The detection result is output.

FIG. 10 shows an example of the error detection circuit 36.

In the figure, the error-corrected data DT output from the decoder 35 is applied to a syndrome generation circuit 41 that generates the syndrome SR described above based on the square matrix A. The SR is temporarily stored in the syndrome register 42.

The output of the syndrome register 42 is applied to the syndrome generation circuit 41 and also to the error determination circuit 43. Therefore, every time the data DT is added, the syndrome SR is newly calculated and sequentially added to the error determination circuit 43.

The control unit 44 starts its operation in synchronization with a timing signal TM2 applied from a controller (not shown), clears the syndrome register 42 immediately before inputting the data DT, and completes input of one sector worth of data DT. The error determination circuit 43 is made operational in synchronization with the timing.

As a result, with the final syndrome SR calculated and added to the error determination circuit 43, the error determination circuit 43 determines whether the value of the syndrome SR is O or not, and if it is other than 0, the error determination circuit 43 determines whether the value of the syndrome SR is O or not. It is determined that an error has occurred in the sector data, and an error signal ER2 is output.

In this way, it is determined whether or not an error has occurred in one sector's worth of error-corrected data.

The determination result is output.

By the way, in the embodiment described above, one data frame DF is divided into one set of recording data (that is, 8 words of data Wt-We and parity words Pi, Ql, P2゜Q).
z), but the present invention is not limited to this, and one data frame DF may include multiple sets of recording data.

Further, the number of bits of a data word, the number of words per sector, the number of words of a data frame, etc. are not limited to those described above, and the recording format of a recording track is not limited to those described above.

Furthermore, the configuration of the square matrix A for generating the parity word R is not limited to that described above.

Furthermore, although two sets of error correction sequences are set in the above embodiment, it is also possible to set three or more sets of error correction sequences.

Furthermore, the present invention can be applied even when a similar error correction code other than the b-adjacent code is used.

Note that the present invention is not limited to optical disk storage devices, but can similarly apply to devices that handle data as a single unit, such as magnetic disk storage devices, magneto-optical disk storage devices, or digital transmission devices. Applicable.

[Effects] As explained above, according to the present invention, an error detection code that detects a pattern of data errors that cannot be corrected by an error correction code is added to the original data before being encoded into an error correction code. Even if the error detection code is at most one word, the error detection capability can be greatly increased, and as a result, there is an advantage that outputting data containing errors can be reliably prevented.

[Brief explanation of the drawing]

Fig. 1 is a signal arrangement diagram showing an example of a data recording format, Fig. 2 is a signal arrangement diagram illustrating the structure of data for one sector, and Fig. 3 is a signal arrangement diagram illustrating the arrangement of each correction sequence. FIG. 4 is a schematic diagram illustrating the interleaving direction,
FIG. 5 is a block diagram illustrating a recorded data encoding device according to the present invention, FIG. 6 is a block diagram illustrating an example of an R parity addition circuit, and FIG. 7 is a block diagram illustrating an example of an R parity generation circuit. , FIG. 8 is a block diagram showing another example of an R parity generation circuit, FIG. 9 is a block diagram showing an example of an error detection and correction device according to the present invention, and FIG. 10 is a block diagram showing an example of an error detection circuit. FIG. 11 is a signal arrangement diagram for explaining a conventional example of an error detection and correction system. 10...R parity addition circuit, 11...P2. Q2
Parity addition circuit, 12. 14... Interleave memory, 13... Pl, Qt parity addition circuit, 21.
...Selector, 22...R parity generation circuit, 32.
34...Dinterleave memory, 33.35...
Decoder, 36...Error detection circuit, 37...OR circuit, 41...Syndrome generation circuit, 42...Syndrome register, 43...Error determination circuit, 101-
112... Exclusive OR circuit, 109... Parity register. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 n) Fig. 10 Fig. 11

Claims (2)

[Claims] (1) In an error detection and correction method for a data processing device that processes data in formatted sector units, each word data for one sector is multiplied by the first square matrix of the power corresponding to its position, and each The first term formed by summing the terms
The parity word of the sector is placed in the final word data of the sector, interleaved in different directions intersecting the data order to form two or more correction sequences that are completed within one sector, and further, for each of these correction sequences, , a set of second parity words according to a second square matrix is added, and each of the correction series is calculated based on the syndrome calculated from the data word of each correction series, the second parity word, and the second square matrix. In addition to correcting data errors in the sector, data errors occurring in the sector are detected based on the syndrome calculated from the error-corrected data, the first parity word, and the first square matrix. Features an error detection and correction method. (2) Error detection according to claim 1, wherein the first square matrix and the second square matrix are opposite in direction in which each element of the data word is shifted. Correction method.