JPS6230468B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a card data reading control system, and particularly to a control system for reading different types of cards by the same card reader.

Conventionally, the card widely used in computer systems is the 80-column card that records 80 characters of information, but other cards such as token cards (50 columns) are also used for special purposes. .

The 80-column card has 80 vertical columns, and each column has 12 perforation positions, which are named R, X, 0, 1, ...9, and the card code is determined by the hole position. represents.

The card reading device reads the code based on the presence or absence of holes punched in the card and the combination thereof, and transfers the data to the main memory of the computer via the control section.

A card reading device normally feeds a card in the longitudinal direction (direction A) as shown in Fig. 1, and passes the card through a reading mechanism column by column.
Read the code using column method.

The reading mechanism includes a photo cell that detects the position of the card in the reading station and generates strobe pulses to synchronize the column being read.
An SPC and a read photo cell RPC are provided for reading the code of each column of the card.
As shown in Figure 1, the strobe photo cell
The SPCs are arranged in a number equivalent to 80 columns on the card, and each time the card is read one column at the front, a strobe photo cell SPC appears from the rear, which detects the light source and generates a strobe pulse. occurs. As shown in FIG. 2, this strobe pulse is used as a synchronizing signal when the read information is sent from the card reading device CR to the control unit CONT on 12 data lines DT. To read the information on one card, 80 strobe pulses are sent, and the reading ends at the 80th strobe pulse.

The read photo cell RPC is then perpendicular to the strobe photo cell SPC for a number of rows (12
When the perforated position of the card passes, the light source is detected and the light source is turned on. The data read by the read photo cell RPC is transferred to the data line.
The data is sent to the control unit CONT via DT, and then converted into the computer's internal code and sent to the CPU.

As shown in Figure 2, the control unit CONT is located between the card reader CR and the CPU, decodes the card reading command RD sent from the CPU, gives an execution instruction to the card reader CR, and reads the card from the card. The read 12-line data DT is code converted and errors and errors are detected.
After checking, the timing TM is taken and the CPU
transfer to the main storage of the other side. In addition, the control unit CONT
displays the device status STI, e.g., hot/empty, stack/full, power on/off, etc.
Notify.

In the card reading device CR, the card is transported from the hopper HP to the reading station RS via the wait station WS, and after the code is read,
Sent to Statska STK via Kitsuku Station KS. Card feed command from control unit CONT
FD, Reject stack command RJ, Error command
ER is given to the card reader CR, while data is sent from the card reader CR to the control unit CONT.
DT, column signal CL, final column signal CE, and device status ST are transferred. The control unit CONT creates a card data read control signal using the transferred column signal CL, final column signal CE, etc., uses this as a synchronization signal, and reads the data.
Furthermore, it is necessary to create a control signal for error checking, perform detection in the card data area, check the card length, and transfer data DT and device status interrupt signal STI to the CPU.

Conventionally, in order to create control signals for data reading and error checking, a control unit receives strobe pulses (column signal CL) generated by following the movement of a card and counts them using a counter. , and its output is directly input to a decoder using gate wired logic.

However, when reading card data under different conditions using the same control unit CONT, it is necessary to create different control signals for card data reading and error checking depending on the type of card used. In the conventional method, a decoder must be provided for each type of card used, which makes the decoder complicated. Furthermore, if the specifications of the device are changed, the decoder must be changed, making the change extremely troublesome.
As described above, the conventional method has various drawbacks due to lack of flexibility in the circuit.

SUMMARY OF THE INVENTION In order to eliminate such conventional drawbacks, an object of the present invention is to provide a card data reading control unit that simplifies the circuit and has flexibility in the circuit in a card reading control unit that reads different types of card data. The purpose is to provide a method.

The card/data reading control system of the present invention is a card/data reading control system that runs a card medium and controls reading of data on the card medium. A suitable read-only memory is selected according to the type of card, and when the card medium runs, a timing signal generated in synchronization with the movement of the column on the card medium is input to the control means. The counter counts the timing signals, supplies the count output to a selected read-only memory as an input address, and extracts a card data read synchronization control signal and an error check control signal from the memory. be.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of the card data reading control system of the present invention.

In FIG. 3, excluding the card reader mechanism section 1, there is a read start control section 6, a timing counter 2, a ROM select control section 7, a card status detection section 8, a read head amplification section 9, a data
The read zone detection section 10, card data latch 11, and ROMs 3, 4, and 5 are control sections.
Provided in CONT.

Conventionally, a decoder is provided for each type of card, but in the present invention, a ROM for control and timing is provided according to the type of card, and a ROM select control section is provided for selecting the necessary ROM from among these. It will be done. That is, in order to simplify the hardware, the circuit for decoding the control signals is simplified, ROMs are provided in place of gate wired logic, and control signal generation patterns are stored in these ROMs. Control signals that can be shared are stored in the same ROM, but patterns of control signals that cannot be shared depending on the card type are stored in separate ROMs. These ROMs count timing signals (column signals) generated by card running with a counter 2, read out the ROM using the counted number as an input address, and create control signals from the read data. ROMs that are not selected are used in a high impedance state under the control of the memory chip select signal, so each
The ROM can be output by wired OR, thus simplifying the hardware.

If the card used is changed, the control signal generation pattern will be reprogrammed.
It can be easily changed by replacing it with ROM, giving flexibility to the circuit.

In FIG. 3, when the card reader mechanism section 1 detects a card set and the read operation is activated by the read activation control section 6, the card reader mechanism section 1 performs column-by-column reading. Begins. At the same time, a timing signal (column signal CL) is generated and sent to the control unit CONT as a synchronization signal together with the read data DT.
In the control unit CONT, a timing counter 2 counts the received timing signals.

On the other hand, the order of the cards to be read is set by software, and the ROM selection control section 7 is activated by a signal from the reading activation control section 6 to select the ROM corresponding to the card.

In Figure 3, an 80 column card and a token card (50 columns) are used. For example, when reading an 80 column card, 80 column card control ROM 3 and data reading timing ROM 5 are selected, and when reading a token card, ROM 3 for controlling the 80 column card and data reading timing ROM 5 are selected. , the token card control ROM 4 and the data read timing ROM 5 are selected.

The ROMs 3 and 4 store error check control signal generation patterns for each card, and these control signals are used to detect the end of card data, card end, check card length, etc.

Further, the ROM 5 stores a generation pattern of a data read control signal for each card, and data is read using this control signal as a synchronization signal and stored in the latch 11.

The selected ROM is held continuously during the card data reading period, and the timing counter 2
Since the count output of is sequentially accessed as the input address of the ROM, the generated pattern is read out at each count timing. Of the generated patterns read out, only meaningful patterns (bit patterns indicating the beginning and end of read data) are stored, for example, by a flip-flop on the output side.

ROMs 3 and 4 must store control bits with different conditions for each card.
If various control bits are mixed in the same ROM, it may cause malfunction, and it is uneconomical to replace the ROM every time the type of card used is changed, so an independent ROM is provided for each card used. ing.

On the other hand, control bits indicating the length of each card are stored in the ROM 5. For example, as shown in Figure 3, in the case of an 80-column card and a token card, the difference in the number of columns between 80 and 50 is recorded. Since different control bit patterns are read out from the ROM 5 by the input addresses 50 and 80 and can be identified, it is only necessary to provide one common ROM.

By setting the output pattern of the ROM 5 in the data read zone detection section 10, the data read zone detection section 10 creates each card data read strobe signal. The data transferred from the card reader CR is read through the read head amplifier section 9 and set in the card data latch 11 in synchronization with the strobe signal from the data read zone detection section 10.

On the other hand, change the output pattern of ROM3 and 4 to the card
By setting the status detection section 8, the card status detection section 8 performs error detection and read completion check on the data read through the read head amplification section 9.

Figure 4 is a diagram showing an example of the pattern programmed into the ROM in Figure 3, and Figure 5 is a diagram showing an example of the pattern programmed in the ROM in Figure 4.
This is a time chart of the ROM output signal.

Normally, four states can be expressed with two bits, so a two-bit combination pattern is stored in ROMs ³ and 4, and in ^FIG . When (2 ⁰ , 2 ¹ )=“10”, each bit pattern at the end point of data is shown.
2 when the count of timing counter 2 is 5
“01” is output to the read line of the book and the count is 11
In this case, “10” will be output. ROM5
A 2-bit combination pattern is also stored in
At address 50, "01" indicates the card length of the token card, and at address 80, "10" indicates the card length of the 80-column card, respectively.

When the bit pattern of FIG. 4 is read out, signals as shown in FIG. 5 are generated on read lines 2 ⁰ and 2 ¹ .

Comparing the present invention and the conventional method, in terms of simplifying the amount of hardware, the present invention, which incorporates a part of the decoder as a generation pattern in the read-only memory, is better than the conventional method using gate wired logic. Compared to the decoding circuit method, the number of integrated circuit chips is reduced by 3 to 4, and the implementation can be simplified.

In addition, in terms of circuit flexibility, by adopting read-only memory, even if the timing of the data read control signal changes, it can be handled by replacing the memory, greatly increasing the flexibility of the circuit. can be improved.

Furthermore, in terms of economy, for example, if three 1-byte fuse-type ROMs are used as memory, the cost of the memory will be higher than that of wired logic, so it is economical in terms of component prices. However, if there is hope for the future and workability during patterning is considered, the present invention is superior.

As described above, according to the present invention, since the control signal is created using a read-only memory, the amount of hardware of the card reading control section can be simplified and flexibility can be provided to the circuit.

[Brief explanation of the drawing]

Fig. 1 is a layout diagram of the photo cell of the 80 column card reading section, Fig. 2 is an explanatory diagram of the interface of the card reading control section, and Fig. 3 is a block diagram of the card data reading control system showing an embodiment of the present invention. 4 is a diagram showing an example of a pattern programmed into the ROM of FIG. 3, and FIG. 5 is an output signal time chart of the ROM of FIG. 4. 1: Card reader mechanism, 2: Timing
Counter, 3: 80 column card control ROM, 4: Token card control ROM, 5: Data reading timing ROM, 6: Reading start control section, 7:
ROM select control section, 8: card status detection section, 9: read head amplification section, 10: data read zone detection section, 11: card data latch.

Claims (1)

[Claims] 1. In a card data reading control system that runs a card medium and controls the reading of data on the card medium, a control means that includes a plurality of read-only memories and a counter that generates the address of the memory is provided, An appropriate read-only memory is selected according to the type of the card medium, and when the card medium runs, a timing signal generated in synchronization with the movement of the column on the card medium is input to the control means, thereby controlling the timing signal. The card is characterized in that the counter counts, supplies the count output to a selected read-only memory as an input address, and extracts a card data read synchronization control signal and an error check control signal from the memory. Data reading control method.