JPS6230467Y2 - - Google Patents

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Publication number
JPS6230467Y2
JPS6230467Y2 JP16505179U JP16505179U JPS6230467Y2 JP S6230467 Y2 JPS6230467 Y2 JP S6230467Y2 JP 16505179 U JP16505179 U JP 16505179U JP 16505179 U JP16505179 U JP 16505179U JP S6230467 Y2 JPS6230467 Y2 JP S6230467Y2
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JP
Japan
Prior art keywords
diode
transistors
transformer
winding
primary side
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JP16505179U
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Japanese (ja)
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JPS5683995U (en
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Description

【考案の詳細な説明】 本考案は例えばリンギングチヨークコンバータ
などの電力変換器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power converter such as a ringing chain converter.

第1図は従来の電力変換器の基本回路、第2図
は第1図の動作のタイミングチヤートを示し、a
はトランジスタQ1のコレクタ・エミツタ間電
圧、bは変圧器T2の巻線NPの電圧、cは変圧器
T2の巻線NPを流れるトランジスタQ1のコレクタ
電流Ic、dは変圧器T2の巻線NSにあらわれる
電圧、eは変圧器T2の巻線NSを流れる電流、f
は変圧器T2の巻線NBにあらわれる電圧、gは変
圧器T1の磁束Φとアンペア回線NIとの関係を示
す。
Figure 1 shows the basic circuit of a conventional power converter, and Figure 2 shows a timing chart of the operation of Figure 1.
is the collector-emitter voltage of transistor Q1 , b is the voltage of winding N P of transformer T2 , and c is the transformer
The collector current I c of the transistor Q 1 flowing through the winding N P of T 2 , d is the voltage appearing at the winding N S of the transformer T 2 , e is the current flowing through the winding N S of the transformer T 2 , f
is the voltage appearing at the winding N B of the transformer T 2 , and g is the relationship between the magnetic flux Φ of the transformer T 1 and the ampere line NI.

第1図の回路において入力電源Vioが印加され
ると起動抵抗RSを介して電流が流れトランジス
タQ2のベースを正バイアスし導通状態とする。
トランジスタQ2が導通するとトランジスタQ1
導通する。(第2図a)トランジスタQ1が少しで
も導通すると変成器T2の1次巻線NPに電圧が印
加されて(第2図b)その結果変圧器T2のベー
ス巻線NBに電圧が発生してトランジスタQ2のベ
ースを正バイアスしトランジスタQ1,Q2を飽和
状態に導く。(第2図aのTpoの期間)変圧器T2
の巻線NPの電流およびトランジスタQ1のコレク
タ電流は変圧器T2の巻線NPのインダクタンスに
より直線的に増加する。(第2図c)またこのと
き変圧器T2の2次側出力巻線NSに発生した電圧
は整流用ダイオードDRECにより阻止されてい
る。変圧器T2の巻線NPに発生した電圧(第3図
d)はまた可飽和変圧器T1の1次巻線NC1に印
加される。この電圧により可飽和変圧器T1の磁
束は直線的に増加し最後の飽和磁束ΦSに達す
る。即ち第2図gに示す如く、トランジスタQ1
のONにより変成器T2の磁束Φは飽和磁束ΦS
達する。この時可飽和変成器T1の2次側巻線NC
はダイオードD3により開放になつている。変圧
器T1の磁束がΦSに達すると変圧器T1の巻器NC1
に発生している電圧は抵抗RCに印加される。そ
して抵抗R1、ダイオードD2を介してトランジス
タQ3を導通状態に導く。トランジスタQ3が導通
するといままでトランジスタQ2のベースに流れ
ていた電流はトランジスタQ3のコレタに流れト
ランジスタQ1,Q2は急激に阻止状態となる。(第
2図aTpffの状態)このとき変圧器T2の各巻線に
は逆電圧が発生し(第2図b,d,f)巻線NS
に発生した電圧はダイオードDRECを介して負荷
Rおよび平滑用コンデンサC2に電流を供給す
る。またこのとき巻線NSに発生する電圧の値は
出力電圧Vputにクランプされる。但しこのとき
ダイオードDRECの順方向の電圧降下は無視する
ものとする。
In the circuit of FIG. 1, when the input power supply V io is applied, a current flows through the starting resistor R S to positively bias the base of the transistor Q 2 and make it conductive.
When transistor Q 2 becomes conductive, transistor Q 1 also becomes conductive. (Fig. 2a) If the transistor Q 1 becomes conductive at all, a voltage is applied to the primary winding N P of the transformer T 2 (Fig. 2 b), so that the base winding N B of the transformer T 2 is energized (Fig. 2 b). A voltage is generated that positively biases the base of transistor Q 2 and brings transistors Q 1 and Q 2 into saturation. (Period of T po in Figure 2 a) Transformer T 2
The current in the winding N P of and the collector current of the transistor Q 1 increases linearly due to the inductance of the winding N P of the transformer T 2 . (Fig. 2c) At this time, the voltage generated in the secondary output winding N S of the transformer T 2 is blocked by the rectifier diode D REC . The voltage developed in the winding N P of the transformer T 2 (FIG. 3d) is also applied to the primary winding N C1 of the saturable transformer T 1 . Due to this voltage, the magnetic flux of the saturable transformer T 1 increases linearly and reaches the final saturation magnetic flux Φ S. That is, as shown in FIG. 2g, the transistor Q 1
By turning ON, the magnetic flux Φ of the transformer T 2 reaches the saturation magnetic flux Φ S. At this time, the secondary winding N C of the saturable transformer T 1
2 is made open by diode D3 . When the magnetic flux of transformer T 1 reaches Φ S , winding N C1 of transformer T 1
The voltage generated at is applied to the resistor R C. Then, transistor Q 3 is brought into conduction via resistor R 1 and diode D 2 . When transistor Q 3 becomes conductive, the current that has been flowing to the base of transistor Q 2 flows to the collector of transistor Q 3 and transistors Q 1 and Q 2 suddenly become blocked. (Situation shown in Fig. 2 aT pff ) At this time, a reverse voltage is generated in each winding of the transformer T 2 (Fig. 2 b, d, f) .
The generated voltage supplies current to the load R and the smoothing capacitor C2 via the diode DREC . Further, at this time, the value of the voltage generated in the winding N S is clamped to the output voltage V put . However, at this time, the voltage drop in the forward direction of the diode DREC is ignored.

このとき変圧器T2の巻線NPにはNP/NS・V
putまた巻線NBにはNB/NS・Vputなる逆電圧が
発生する。変圧器T2の巻線NBに発生した逆電圧
は変圧器T1の巻線NC1に抵抗RCの電圧降下を除
いた値が印加される。このとき変圧器T1の巻線
C2にはダイオードD3を介してトランジスタQ4
の導通状態で決定される電流iC1が流れる。この
電流の値は基準電圧Erefと出力電圧Vputの値に
より制御される。またこの電流は変圧器T1の巻
線NC1にNC1・iC1/NC2の関係で変換されるiC
となる。変圧器T1の巻線NC1に印加される電圧
は変圧器T2の巻線NBに発生した電圧と電圧降下
C・iC2の差であつてこの電圧により変圧器T1
の磁束はΦSよりある値Φまで変化する。即ち、
トランジスタQ1,Q2の阻止状態により、変成器
T2の巻線NBに逆電圧が発生しこの逆電圧が変成
器T1の巻線NC1に印加され逆励磁され、第2図
gに示すように、磁束の値はΦSからΦまで変化
する。この磁束の変化量がトランジスタQ1,Q2
の導通時間を決定する。即ち、電圧降下RC・iC
の値を大きくすることにより第2図gに示す磁
束Φの戻り量は小さくなり第2図aに示すトラン
ジスタQ1のON,OFF時間は短かくなる。逆にR
C・iC2の値を小さくすることにより第2図gに
示す磁束Φの戻り量は大きくなり、第2図aに示
すトランジスタQ1のON,OFF時間は長くなる。
トランジスタQ1,Q2が導通しているとき変圧器
T2の巻線NPのインダクタンスに蓄積されたエネ
ルギーが完全に2次側への放電が終ると最初の動
作が初まりトランジスタQ1,Q2が導通し上述の
動作を繰返す。
At this time, the winding N P of transformer T 2 has N P /N S・V
put Also, a reverse voltage of N B /N S ·V put is generated in the winding N B. The reverse voltage generated in the winding N B of the transformer T 2 is applied to the winding N C1 of the transformer T 1 excluding the voltage drop across the resistor R C . At this time, a transistor Q 4 is connected to the winding N C2 of the transformer T 1 via a diode D 3 .
A current i C1 determined by the conduction state of flows. The value of this current is controlled by the values of the reference voltage E ref and the output voltage V put . Also, this current is converted into the winding N C1 of the transformer T 1 by the relationship N C1・i C1 /N C2
It becomes 2 . The voltage applied to the winding N C1 of the transformer T 1 is the difference between the voltage generated in the winding N B of the transformer T 2 and the voltage drop R C・i C2 .
The magnetic flux changes from Φ S up to a certain value Φ. That is,
Depending on the blocking state of transistors Q 1 and Q 2 , the transformer
A reverse voltage is generated in the winding N B of the transformer T 2 , and this reverse voltage is applied to the winding N C1 of the transformer T 1 , which causes it to be reverse excited, and the value of the magnetic flux changes from Φ S to Φ, as shown in Figure 2g. changes up to. The amount of change in this magnetic flux is the amount of change in transistors Q 1 and Q 2
Determine the conduction time. That is, the voltage drop R C・i C
By increasing the value of 2 , the return amount of the magnetic flux Φ shown in FIG. 2g becomes smaller, and the ON/OFF time of the transistor Q1 shown in FIG. 2a becomes shorter. On the contrary, R
By decreasing the value of C ·i C2 , the return amount of the magnetic flux Φ shown in FIG. 2g increases, and the ON/OFF time of the transistor Q1 shown in FIG. 2a becomes longer.
When transistors Q 1 and Q 2 are conducting, the transformer
When the energy stored in the inductance of the winding N P of T 2 is completely discharged to the secondary side, the first operation begins and the transistors Q 1 and Q 2 conduct and repeat the above operation.

以上のように第1図の回路においては出力電圧
(出力電流)を一定に制御するためにトランジス
タQ1,Q2が阻止状態のとき変圧器T1の磁束の変
化量(ΦSからΦまでの)を制御してトランジス
タQ1,Q2の導通時間を制御している。
As described above, in the circuit shown in Figure 1, in order to control the output voltage (output current) constant, when the transistors Q 1 and Q 2 are in the blocking state, the amount of change in the magnetic flux of the transformer T 1 (from Φ S to Φ ) to control the conduction time of transistors Q 1 and Q 2 .

磁束の変化量を定めるのは、変成器T1の巻線
C1に流れる励磁電流である。従つて、この励磁
電流を小さくすることによつて、変成器T1が磁
気飽和に達する時間が短かくできる。さらに、励
磁電流iC2はiC1の値と抵抗RCの値により決ま
るが、iC1の値を大きくしようとするとEref及び
putの値を大きくする必要があつて、発振する
可能性が大きく安定な出力は得られない。さらに
励磁電流にはバラツキが大きく、誤動作を防止す
るためにもこれを小さくする必要がある。
The amount of change in magnetic flux is determined by the excitation current flowing through the winding N C1 of the transformer T 1 . Therefore, by reducing this excitation current, the time required for transformer T1 to reach magnetic saturation can be shortened. Furthermore, the excitation current i C2 is determined by the value of i C1 and the value of the resistor R C , but if you try to increase the value of i C1 , you will need to increase the values of E ref and U put , which may cause oscillation. Large and stable output cannot be obtained. Furthermore, the excitation current has large variations, and it is necessary to reduce this in order to prevent malfunctions.

従つて励磁電流を小さくするため、従来では抵
抗RCの値を大きくとり、励磁電流を小さくして
いる。しかしながら、抵抗RCを大きくすること
により、この抵抗RCによる電圧降下が大きくな
り、ダイオードD2を介してトランジスタQ3が誤
まつて導通する恐れがあり外乱によつても導通す
る恐れもあり安定したスイツチング動作を得るこ
とは困難であつた。
Therefore, in order to reduce the excitation current, conventionally the value of the resistor R C is increased to reduce the excitation current. However, by increasing the resistor R C , the voltage drop due to this resistor R C increases, and there is a risk that the transistor Q 3 will be erroneously turned on via the diode D 2 and may also be turned on due to disturbances. It has been difficult to obtain stable switching operation.

本考案の目的は上記従来の欠点を解消すること
にあり、その目的は電源をオン・オフするトラン
ジスタQ1,Q2と、該トランジスタQ1,Q2のコレ
クタに接続された変圧器T2に含まれる巻線NP
と、該巻線と変圧器T2で結合される巻線NBと、
該巻線NBに接続される可飽和変圧器T1の一次側
と、該可飽和変圧器T1の一次側に直列に接続さ
れる抵抗、ダイオードの回路網と、前記回路網と
前記トランジスタQ1,Q2のエミツタに接続さ
れ、前記トランジスタQ1,Q2をオフする制御用
トランジスタQ3よりなる電力変換器において、
前記回路網はダイオードD11、低抵抗R11と高抵抗
R12により構成され、前記トランジスタQ1,Q2
オン時には前記低抵抗R11を介して該可飽和変圧
器の1次側に励磁電流を供給し、オフ時には前記
高抵抗R12を介して、該可飽和変圧器の1次側に
逆励磁電流を供給することによつて該可飽和変圧
器を励磁し、前記制御用トランジスタQ3を制御
することにより達成される。
The purpose of the present invention is to eliminate the above-mentioned conventional drawbacks, and the purpose is to provide transistors Q 1 and Q 2 that turn on and off the power supply, and a transformer T 2 connected to the collectors of the transistors Q 1 and Q 2 . Winding N P included in
and a winding N B coupled to the winding by a transformer T2 ,
a primary side of the saturable transformer T 1 connected to the winding N B ; a network of resistors and diodes connected in series to the primary side of the saturable transformer T 1 ; and the network and the transistor. In a power converter comprising a control transistor Q3 connected to the emitters of Q1 and Q2 and turning off the transistors Q1 and Q2 ,
The network consists of a diode D 11 , a low resistance R 11 and a high resistance
When the transistors Q 1 and Q 2 are on, the excitation current is supplied to the primary side of the saturable transformer through the low resistance R 11 , and when it is off, the excitation current is supplied through the high resistance R 12 . , is achieved by exciting the saturable transformer by supplying a reverse excitation current to the primary side of the saturable transformer and controlling the control transistor Q3 .

以下本考案にかかる電力変換器の実施例につい
て詳細に説明する。
Embodiments of the power converter according to the present invention will be described in detail below.

第4図Aは本考案にかかる実施例を示す。図に
おいてR11は低抵抗、R12は高抵抗、D11はダイオ
ードである。第4図Aのごとく抵抗R11,R12およ
びダイオードD11を接続することにより主トラン
ジスタQ1,Q2がオフのときは抵抗R12、可飽和ト
ランスT1を介して定格出力パワーの送出可能な
範囲で抵抗R12を出来る限り大きくして変圧器T1
の励磁電流を少なくして出力電圧の高安定を得
る。また主トランジスタQ1,Q2がオンのときは
可飽和変圧器T1、ダイオードD11、抵抗R11を介
して変圧器T1の励磁電流のバラツキや外乱によ
るスイツチング動作の誤動作を防止するため抵抗
R11の値をできるだけ小さくして高安定なスイツ
チング動作をうる。
FIG. 4A shows an embodiment of the present invention. In the figure, R 11 is a low resistance, R 12 is a high resistance, and D 11 is a diode. By connecting the resistors R 11 and R 12 and the diode D 11 as shown in Figure 4A, when the main transistors Q 1 and Q 2 are off, the rated output power is transmitted through the resistor R 12 and the saturable transformer T 1 . Make the resistor R 12 as large as possible and transformer T 1
A highly stable output voltage is obtained by reducing the excitation current. Furthermore, when the main transistors Q 1 and Q 2 are on, the voltage is passed through the saturable transformer T 1 , the diode D 11 , and the resistor R 11 to prevent malfunctions in the switching operation due to fluctuations in the excitation current of the transformer T 1 or disturbances. resistance
Highly stable switching operation can be achieved by minimizing the value of R11 .

第5図および第6図は第4図Aの回路における
具体的特性の1例であり、第3図において負荷の
抵抗値を変化させた場合の負荷に印加される電圧
(Vput)と電流の関係を示す。第5図は垂下特性
を従来の回路と本発明にかかる回路を比較して示
したもので図中縦軸は電圧、横軸は電流を示す。
図において曲線A1およびA2は従来の回路の特性
を示し、A1はRC=20Ωの場合をA2はRC=100Ω
の場合を示す。なお曲線B1,B2,B3は第4図A
の回路における特性を示すものでB1はR11=20
Ω、R12=47Ωの場合、B2はR11=20Ω、R12=100
Ωの場合、B3はR11=20Ω、R12=200Ωの場合を
示し、抵抗R12の挿入により垂下特性の得られる
ことを示す。また第6図は本考案にかかる回路に
おいて抵抗R11およびR12を変化させた場合を示
し、曲線C1,C2,……,C7はR11=10Ωの場合で
さらにC1,C2,C3,C4,C5,C6,C7はそれぞれ
R12=30Ω、50Ω.67.5Ω、100Ω、133Ω、150
Ω、205Ωの場合、曲線D1,D2,D3,D4はR11
100Ωの場合でさらにD1,D2,D3,D4はそれぞれ
R12=50Ω、71.5Ω、100Ω、133Ωの場合を示
す。いずれの場合も抵抗R12の挿入によつて垂下
特性を得られることを示す。
Figures 5 and 6 are examples of specific characteristics of the circuit in Figure 4A, and in Figure 3, the voltage ( Vput ) and current applied to the load when the resistance value of the load is changed. shows the relationship between FIG. 5 shows a comparison of drooping characteristics between a conventional circuit and a circuit according to the present invention, in which the vertical axis represents voltage and the horizontal axis represents current.
In the figure, curves A 1 and A 2 show the characteristics of the conventional circuit, where A 1 is for R C = 20 Ω and A 2 is for R C = 100 Ω.
The case is shown below. Curves B 1 , B 2 , and B 3 are shown in Figure 4 A.
B 1 is R 11 = 20
Ω, R 12 = 47 Ω, B 2 is R 11 = 20 Ω, R 12 = 100
In the case of Ω, B 3 shows the case where R 11 = 20Ω and R 12 = 200Ω, indicating that the drooping characteristic can be obtained by inserting the resistor R 12 . Further, Fig. 6 shows the case where the resistances R 11 and R 12 are changed in the circuit according to the present invention, and the curves C 1 , C 2 , ..., C 7 are in the case where R 11 = 10Ω, and further C 1 , C 2 , C 3 , C 4 , C 5 , C 6 , C 7 are respectively
R12 = 30Ω, 50Ω. 67.5Ω, 100Ω, 133Ω, 150
Ω, 205Ω, the curves D 1 , D 2 , D 3 , D 4 are R 11 =
In the case of 100Ω, D 1 , D 2 , D 3 , and D 4 are each
The cases where R 12 = 50Ω, 71.5Ω, 100Ω, and 133Ω are shown. In either case, it is shown that the drooping characteristic can be obtained by inserting the resistor R12 .

第4図、B,C,D,Eはいずれも第4図Aの
応用例であつて抵抗R11,R12はそれぞれ第4図A
の場合と同じ効果を有していることは明らかであ
る。
Figure 4, B, C, D, and E are all application examples of Figure 4 A, and the resistors R 11 and R 12 are respectively Figure 4 A.
It is clear that it has the same effect as in the case of .

以上詳細に説明したごとく本考案にかかる回路
は従来回路の欠点の1つであるスイツチング動作
の不安定を解消するため抵抗R11を小さくして励
磁電流のバラツキが多いときあるいは外乱によつ
て抵抗R11に印加される電圧を下げてトランジス
タQ3が容易に導通しないようにし、また出力電
圧の低安定度を解消するため抵抗R12の値を定格
出力パワー送出可能な範囲でできうる限り大きく
して変圧器T1の励磁電流の変化分を小さくして
出力電圧の高安定度を得るものである。さらに励
磁電流の変化分を小さく取ることができるため出
力端短絡時において出力電流に垂下特性が得られ
るものである。
As explained in detail above, the circuit according to the present invention solves the instability of switching operation, which is one of the drawbacks of conventional circuits, by reducing the resistance R 11 and reducing resistance when there are large variations in excitation current or due to disturbances. In order to reduce the voltage applied to R 11 so that transistor Q 3 does not easily conduct, and to eliminate the low stability of the output voltage, the value of resistor R 12 is made as large as possible within the range that allows the rated output power to be delivered. This reduces the amount of change in the excitation current of the transformer T1 , thereby achieving high stability of the output voltage. Furthermore, since the amount of change in the excitation current can be kept small, a drooping characteristic can be obtained in the output current when the output terminal is short-circuited.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は電力変換回路の基本回路の1例、第2
図は第1図の回路の各部波形を示すタイミングチ
ヤート、第3図は従来の電力変換回路の1例、第
4図は本考案にかかる電力変換回路の実施例、第
5図および第6図はそれぞれ第4図に示す回路の
動作特性を示す図である。 図においてR11が低抵抗、R12が高抵抗、D11
よびD12がダイオードである。
Figure 1 shows an example of the basic circuit of a power conversion circuit;
The figure is a timing chart showing the waveforms of each part of the circuit in Figure 1, Figure 3 is an example of a conventional power conversion circuit, Figure 4 is an example of the power conversion circuit according to the present invention, and Figures 5 and 6. 4 are diagrams showing the operating characteristics of the circuit shown in FIG. 4, respectively. In the figure, R 11 is a low resistance, R 12 is a high resistance, and D 11 and D 12 are diodes.

Claims (1)

【実用新案登録請求の範囲】 1 電源をオン・オフするトランジスタQ1,Q2
と、該トランジスタQ1,Q2のコレクタに接続
された変圧器T2に含まれる巻線NPと、該巻線
と変圧器T2で結合される巻線NBと、該巻線N
Bに接続される可飽和変圧器T1の一次側と、該
可飽和変圧器T1の一次側に直列に接続される
抵抗、ダイオードの回路網と、前記回路網と前
記トランジスタQ1,Q2のエミツタに接続さ
れ、前記トランジスタQ1,Q2をオフする制御
用トランジスタQ3よりなる電力変換器におい
て、前記回路網はダイオードD11、低抵抗R11
高抵抗R12により構成され、前記トランジスタ
Q1,Q2がオン時には前記低抵抗R11を介して該
可飽和変圧器の1次側に励磁電流を供給しオフ
時には前記高抵抗R12を介して、該可飽和変圧
器の1次側に逆励磁電流を供給することによつ
て該可飽和変圧器を励磁し、前記制御用トラン
ジスタQ3を制御することを特徴とする電力変
換器。 2 前記ダイオードD11のアノードが前記可飽和
変圧器の一次側に接続され、前記低抵抗R11
前記ダイオードD1のカソードと前記トランジ
スタQ1,Q2のエミツタ間に接続され、前記高
抵抗R12が前記ダイオードD11のアノードと前記
トランジスタQ1,Q2のエミツタ間に接続さ
れ、前記ダイオードD11と前記低抵抗R11との接
続点が前記制御用トランジスタQ3に接続され
たことを特徴とする実用新案登録請求の範囲第
1項記載の電力変換器。 3 前記ダイオードD11のアノードが前記可飽和
変圧器T1の一次側に接続され、前記低抵抗R11
が前記ダイオードD11のカソードと前記トラン
ジスタQ1,Q2のエミツタ間に接続され、前記
高抵抗R12が前記ダイオードD11のカソードと前
記トランジスタQ1,Q2のエミツタ間に接続さ
れ、前記可飽和変圧器T1の一次側と前記ダイ
オードD11の接続点が前記制御用トランジスタ
に接続されたことを特徴とする実用新案登録請
求の範囲第1項記載の電力変換器。 4 前記ダイオードD11のアノードが前記可飽和
変圧器T1の一次側に接続され、前記高抵抗R12
が前記ダイオードD11に並列に接続され、前記
低抵抗R11が前記ダイオードD11のカソードと前
記トランジスタQ1,Q2間に接続され、前記ダ
イオードD11と前記低抵抗との接続点が前記制
御用トランジスタに接続されたことを特徴とす
る実用新案登録請求の範囲第1項記載の電力変
換器。 5 前記ダイオードD11のアノードが前記可飽和
変圧器T1の一次側に接続され、前記低抵抗R11
が前記ダイオードD11のカソードと前記トラン
ジスタQ1,Q2間に接続され、前記ダイオード
D12のカソードが前記ダイオードD11のアノード
に接続され、前記高抵抗R12が前記ダイオード
D12のアノードと前記トランジスタQ1,Q2間に
接続され前記ダイオードD11と前記低抵抗R11
の接続点が前記制御用トランジスタに接続され
たことを特徴とする実用新案登録請求の範囲第
1項記載の電力変換器。 6 前記ダイオードD11のアノードが前記可飽和
変圧器T1の一次側に接続され、前記低抵抗R11
が前記ダイオードD11のカソードと前記トラン
ジスタQ1,Q2のエミツタ間に接続され、前記
ダイオードD12のカソードが前記ダイオードD11
のアノードに接続され、前記高抵抗R12が前記
ダイオードD12のアノードと前記トランジスタ
Q1,Q2のエミツタ間に接続され、前記可飽和
変圧器T1の一次側と前記ダイオードD11の接続
点が前記制御用トランジスタに接続されたこと
を特徴とする実用新案登録請求の範囲第1項記
載の電力変換器。
[Scope of claims for utility model registration] 1 Transistors Q 1 and Q 2 that turn on and off the power supply
, a winding N P included in the transformer T 2 connected to the collectors of the transistors Q 1 and Q 2 , a winding N B coupled to the winding by the transformer T 2 , and the winding N
the primary side of the saturable transformer T 1 connected to B , a network of resistors and diodes connected in series to the primary side of the saturable transformer T 1 , and the circuit network and the transistors Q 1 , Q In the power converter, the circuit network is composed of a control transistor Q3 connected to the emitter of No. 2 and turns off the transistors Q1 and Q2 , and the circuit network is composed of a diode D11 , a low resistance R11 , and a high resistance R12 , the transistor
When Q 1 and Q 2 are on, the excitation current is supplied to the primary side of the saturable transformer via the low resistance R 11 , and when it is off, the exciting current is supplied to the primary side of the saturable transformer via the high resistance R 12 . A power converter characterized in that the saturable transformer is excited by supplying a reverse excitation current to the side thereof, and the control transistor Q3 is controlled. 2. The anode of the diode D 11 is connected to the primary side of the saturable transformer, the low resistance R 11 is connected between the cathode of the diode D 1 and the emitters of the transistors Q 1 and Q 2 , and the high resistance R12 is connected between the anode of the diode D11 and the emitters of the transistors Q1 and Q2 , and a connection point between the diode D11 and the low resistance R11 is connected to the control transistor Q3 . A power converter according to claim 1, characterized in that: 3 The anode of the diode D 11 is connected to the primary side of the saturable transformer T 1 and the low resistance R 11
is connected between the cathode of the diode D11 and the emitters of the transistors Q1 and Q2 , the high resistance R12 is connected between the cathode of the diode D11 and the emitters of the transistors Q1 and Q2, and the high resistance R12 is connected between the cathode of the diode D11 and the emitters of the transistors Q1 and Q2 . 2. The power converter according to claim 1, wherein a connection point between the primary side of the saturable transformer T1 and the diode D11 is connected to the control transistor. 4 The anode of the diode D 11 is connected to the primary side of the saturable transformer T 1 and the high resistance R 12
is connected in parallel to the diode D11 , the low resistance R11 is connected between the cathode of the diode D11 and the transistors Q1 and Q2 , and the connection point between the diode D11 and the low resistance is connected to the low resistance R11. The power converter according to claim 1, characterized in that the power converter is connected to a control transistor. 5 the anode of the diode D 11 is connected to the primary side of the saturable transformer T 1 and the low resistance R 11
is connected between the cathode of the diode D 11 and the transistors Q 1 and Q 2 , and the diode
The cathode of D12 is connected to the anode of the diode D11 , and the high resistance R12 is connected to the anode of the diode D11.
Claims for registration of a utility model characterized in that the anode of D12 is connected between the transistors Q1 and Q2 , and a connection point between the diode D11 and the low resistance R11 is connected to the control transistor. The power converter according to item 1. 6 the anode of the diode D 11 is connected to the primary side of the saturable transformer T 1 and the low resistance R 11
is connected between the cathode of the diode D11 and the emitters of the transistors Q1 and Q2 , and the cathode of the diode D12 is connected to the diode D11.
The high resistance R 12 is connected to the anode of the diode D 12 and the transistor
A utility model registration claim characterized in that the emitters of Q 1 and Q 2 are connected to each other, and a connection point between the primary side of the saturable transformer T 1 and the diode D 11 is connected to the control transistor. The power converter according to item 1.
JP16505179U 1979-11-30 1979-11-30 Expired JPS6230467Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16505179U JPS6230467Y2 (en) 1979-11-30 1979-11-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16505179U JPS6230467Y2 (en) 1979-11-30 1979-11-30

Publications (2)

Publication Number Publication Date
JPS5683995U JPS5683995U (en) 1981-07-06
JPS6230467Y2 true JPS6230467Y2 (en) 1987-08-05

Family

ID=29675977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16505179U Expired JPS6230467Y2 (en) 1979-11-30 1979-11-30

Country Status (1)

Country Link
JP (1) JPS6230467Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0753028B2 (en) * 1985-07-08 1995-06-05 株式会社日立製作所 Switching power supply

Also Published As

Publication number Publication date
JPS5683995U (en) 1981-07-06

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