JPS6229832B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic computing device including a monolithic integrated circuit electronic device, a keyboard, and an output device, and more particularly to a versatile electronic device that incorporates the basic functions of an electronic computing device into a single semiconductor integrated circuit, and a keypad thereof. An ultra-compact, versatile electronic computing device that has a keyboard input device connected with a number of input lines smaller than the number of input lines, and an output device that is operated by an output signal of the calculation result obtained in the electronic device. It is related to. With the development of semiconductor integrated circuit technology, the miniaturization of electronic desk calculators and the diversification of circuit designs are progressing, but the following difficult problems arise in this regard. In other words, manufacturers of semiconductor integrated circuit chips demand that designers produce integrated circuits that are as uniform as possible in order to lower the cost of the chips and shorten the manufacturing cycle. In order to sell new models one after another, the manufacturers perform a wide variety of calculations (arithmetic calculations, constant calculations, memory,
Semiconductor chip manufacturers are required to provide various types of integrated circuits capable of performing square root calculations, etc., and this creates a trade-off problem. In order to meet the demands for a variety of calculation functions, it is necessary to make changes inside the integrated circuit each time, and it becomes necessary to start over from the photomask manufacturing mask corresponding to each calculator model, so the manufacturing of integrated circuit chips is difficult. This takes time and money, and there is a risk that the essential benefits of integrated circuits may be lost. As one solution to this problem, attempts were made to standardize each of the many integrated circuit chips and create various calculator models by combining multiple chips, but the reliability of the lead wire connections between multiple chips was There are also problems, such as limitations on the combination of chips, and the fact that the concept of a desktop calculator still cannot be overcome. On the other hand, although computers are versatile,
Its range of applications is limited due to its large size, high price, high power consumption, and the fact that storage devices usually include non-semiconductor parts such as core memory or magnetic tape. There is. In addition, the CPU (central processing unit) uses a semiconductor integrated circuit, but in order to increase the calculation speed, it uses many bipolar type integrated circuits, which have a lower integration density than MOS type, and requires extremely complicated connections. As a result, it is difficult to downsize the system. An object of the present invention is to solve the above-mentioned problems in the prior art, and to solve the above-mentioned problems in the prior art by using a versatile electronic device that is configured in a monolithic semiconductor integrated circuit and incorporates the basic functions of an electronic computing device. It is an object of the present invention to provide a variable function fixed program electronic computing device capable of performing not only complex calculations but also calculations requiring complicated program control. Another object of the invention is to provide a device that acts as a basic desktop calculator. In particular, this is to provide computational functions including multi-digit floating-point input and floating-point output, and basic decimal operations such as addition, subtraction, multiplication, and division. This purpose is achieved according to the invention by, for example, a dynamic charge storage random access memory shifter for recording numbers and control data.
This is done by providing an array. The calculator has a control memory such as a programmable logic array (PLA), a program memory such as a read-only memory (ROM), and a binary coded decimal (BCD), bit-serial-number-parallel decimal arithmetic, set-bit Reset toggle (SRT) flag (FLAG)
Includes apparatus for performing arithmetic and logical modifications of recorded data, including data modification. Another object of the invention is to provide a computer device that can be manufactured as a monolithic semiconductor device. In particular, it is an object of the present invention to provide a computing device that can be manufactured as a monolithically integrated metal-insulator-semiconductor device using current metal-insulator-semiconductor technology. This purpose is achieved according to the invention by
A random access memory shift register device that requires only about one-third the area of a conventional shift register device is provided, and a unit phase that is included in the calculator but external to the monolithic structure is provided. Internally generates a multi-phase clock from the input clock,
This is accomplished by providing a common program scanning device within the monolithic structure for both keyboard encoding and display decoding with minimal external connections between the monolithic structure and the keyboard and display. The total number of connections from the monolithic structure to other subsystems such as the keyboard, display and power supply is thus minimized, and the monolithic structure can fit into a conventional 28 or 40 pin package. Another object of the present invention is to provide flexibility in that the functions and input/output interfaces of a computer can be changed without changing the basic computer structure, especially without changing the basic computer structure such as an integrated semiconductor device. The purpose of the present invention is to provide a computer device. This object is achieved according to the invention by providing a programmable read-only memory which provides a fixed program of the computing device according to the desired functionality of the computing device, and by masking the input/output and operational data to the desired format. This is done by providing a programmable logic array that decodes and encodes the .
Programmable read-only memory and programmable logic arrays are manufactured using metal-insulators during the manufacturing process.
This can be easily corrected by changing the gate insulator mask of the semiconductor integrated device. Still another object of the present invention is to provide an improved apparatus for encoding keyboard commands and status information and for operating as a direct interface device between a display decoder and a segment display and/or individual decimal display. This object is accomplished in accordance with the present invention by providing a programmed scanning device that operates on both keyboard input and display output to minimize the hardware requirements of the key input device. The four keyboard input pins combine with the eleven scan output pins to allow for a total of 44 different keys and/or switches. Programmed routines residing in read-only memory encode input from the keyboard array under program control. The scanning device operates at a speed low enough to eliminate the need for external keyboard drive circuitry;
Enables direct driving of large capacitance loads with scanning speed consistent response. The scanning program includes an encoding routine that substantially cancels out transient noise and key vibration type disturbances from the keyboard. Another advantage of the keyboard scanning device is that it requires few diodes, no amplifiers, and the switches need not be simple switches and low resistance or low vibration time switches. Display output is internal segment,
or includes numeric day code, numeric blanking and zero suppression logic and uses the same scanning device as the keyboard. The display itself includes a light emitting diode, liquid crystal, cold cathode gas discharge display element, fluorescent display element, multi-digit single envelope cold cathode gas discharge tube,
Including incandescent display elements, etc. Multiple display capabilities are variable by commonly configured digit scanning and segment or digit decoding devices and by application of leading and trailing edge blanking spacing and either segment drivers or digit drivers or both. This is provided by providing an internal number blanking signal. Output decoder can be any 7, 8, 9, 10
Includes programmable logic array segment decoder circuitry to apply left and right shifts of the decimal point for segmented representation or decimal representation addition.
The calculator device of the invention is thus essentially independent of the choice of display element used. Yet another object of the present invention is to provide an internal device for erasing invalid leading zeros from a calculator display.
This objective is accomplished by a programmed scanning device that first scans the most significant output digits and minimizes the hardware device to detect and erase leading zeros. Another object of the invention is to enable both constant arithmetic numbers and chained intermediate result type calculations in a completely algebraic manner. The purpose of this is to provide an operator selection control, or mode switch, to distinguish the constant arithmetic mode from the chained intermediate results mode of operation, and to provide a fixed read-only memory to detect and execute the desired mode. This is done by providing a program determination routine. Yet another object of the present invention is to provide a calculator device including a device for automatically rounding down to 50 solutions in order to increase the accuracy of calculations. This purpose is accomplished in accordance with the present invention by using a fixed program routine stored in read-only memory that adds the number 5 to the least significant digit that is lost. In this way, when the minimum digit that is lost is 5 or more, 1 is added to the second digit that is retained. Another object of the present invention is to provide a computing device with minimal power dissipation in order to provide a portable desktop calculator that does not consume much battery. This purpose is achieved in accordance with the invention by providing special control circuitry to turn off the functional elements except when they are actually in use, and by providing read-only memories, programmable logic arrays, arithmetic logic unit functional subsystems, etc. System metal
This is accomplished by providing a special precharge ratioless circuit within the insulator-semiconductor embodiment. For example, instruction output from read-only memory only needs to be probed once per instruction cycle, and 2/1 of the nominal quiescent power dissipation is required to eliminate DC current.
Power control is added to a read-only memory decoder that performs a duty cycle of 3 to avoid excessive
Only the power of CV ² f is dissipated. Further objects and advantages of the invention will be apparent from the following detailed description and claims describing the invention, as well as from the accompanying drawings. In accordance with the present invention, a variable function programmed calculator containing a fixed program stored in a read-only memory can be manufactured as a monolithically integrated semiconductor device. In particular, the described embodiments are based on current metal-
It can be manufactured as a monolithic integrated MIS device using insulator-semiconductor (MIS) technology. The calculator device is programmed to perform desktop calculator functions including floating point operations or other useful operations. The monolithic structure of the computing device contains a fixed program that is programmed into a programmable read-only memory by modifying one of five or seven masks (gate insulator mask) during the manufacturing process. . Furthermore, the data inputs, outputs, and arithmetic formats within the computing device can also be programmed into the programmable logic array by changing the same mask. The following sections first describe the functional relationships between the various subsystems, then specific circuits, and finally fixed programs stored in read-only memory. Functional explanation of the computer device FIGS. 1 and 2 show the functional dependencies among the five internal functional subsystems in the computer device of the present invention,
and relationships between internal subsystems and external functional elements. In this embodiment, the five internal functional subsystems are implemented as a monolithic integrated circuit, and the external functional elements are constructed outside the integrated circuit. Program block 201 includes a read only memory (ROM) 278 and a program counter (PC) 209 that store fixed programs for operating the calculator in a desired manner. Control block 202 includes an instruction register (IR) 190 for storing control instructions, a control decoder 191 for decoding control instructions, and a jump condition circuit 192. Timing block 203 includes clock generator 193, timing generator 194, numbers and
Includes FLAG mask decoder 195 and key input logic 196. Data block 204 includes a random access memory shift register unit and FLAG data storage array 206, decimal data arithmetic logic unit 207, and FLAG logic unit 229.
including. Output block 205 includes a segment output decoder 198 and a numeric output scanner 197. Data Block 204 Referring to FIG.
A detailed functional description is provided. data·
Block 204 includes devices for decimal or hexadecimal data storage and basic arithmetic operations. Since the memory structure of this embodiment is parallel to decimal or hexadecimal digits,
Each interconnect 210 that couples to various functional elements actually symbolizes four interconnects. Memory array shift register device 20
6 A register 211, B register 212 and C
Register 213 contains the basic decimal or hexadecimal storage of the calculator logic unit. A one-bit dynamic shift register delay circuit 214 is used to perform recirculating updates of main registers 211, 212, and 213. The outputs of A register 211 and C register 213 are U data selector gate 2.
15 is input. The output of B register 212 and a constant N provided by device 223 are input to V data selector gate 216. A binary or binary coded decimal (BCD) adder 217 calculates the sum or difference between U and V, ie, U+V or UV. U is on the plus side of the adder and V is on the minus side of the adder. Σ data selector gate 218 provides a facility for short or long shift operations. The output from adder 217 into Σ data selector gate 218 corresponds to the normal path where no shifting occurs. ΣData selector gate 2
The 1-bit delay circuit 225 at the delayed adder input to 18 corresponds to the long path on which the left shift is performed. The UV logic OR gate 224 at the input to the Σ data selector gate 218 corresponds to a short circuit that performs a right shift. Data selector gate 219 connects the input to A register 211 to the Σoutput of Σdata selector gate 218, delayed B
Select from either register 212 output or delay A register output. Data selector gate 220 connects the input to the B register to the Σoutput of Σdata selector gate 218, delayed A register 2
11 output and the delay B register 212 output. Data selector gate 22
1 selects the input to the C register from either the Σ output of the Σ data selector gate 218 or the delayed C register 213 output. Latch condition circuit 192, which latches the jump condition, is loaded by the carry borrow of adder 217. In this embodiment, A register 211, B register 2
12, each of the C registers 213 has 13 decimal or
Provides dynamic recirculating storage of hexadecimal digits. Adder 217, U data selector gate 215, V data selector gate 216, Σ
Data selector gate 218, A data selector gate 219, B data selector gate 220, and C data selector gate 2
21 provides a means for performing arithmetic and logical modifications of the contents of registers 211, 212, 213 by synchronized operation of selector and adder controls, which will now be described in detail in the section describing the control blocks. Referring to FIG. 4, the contents of data block 204 are illustrated in terms of one bit state or FLAG element storage and operation. The coupling of functional elements is indicated by interconnects 230. Two 12-bit registers, FA register 226 and FB register 227
gives storage of state, ie FLAG information. The outputs of FA register 226 and FB register 227 are delayed by one bit by dynamic, shift register element 228 before being input to FLAG arithmetic logic unit 229. FLAG arithmetic logic unit 2
The A and B outputs of 29 are FLAG registers 226, 2
27. The FLAG arithmetic logic unit operations recirculate, set, and recirculate individually addressed FLAGs.
Includes reset and toggle and FLAG exchange and comparison of FA and FB pairs. Control SUB, FFLG, RFLG,
FLAG, and XFLAG are specific addressed
Generated to perform desired operations on a FLAG or FLAG pair. Arithmetic comparison FLAG and arithmetic test FLAG
generates an output from the FLAG arithmetic unit to jump condition circuit 192. The control mechanisms for these FLAG operations are described below in the section describing control block 202 in detail. Control Block 202 The function of control block 202 is to receive instructions from program control block 201, interpret the instructions and conditional flip-flops as instructions for subsequent instruction cycles, and process data block 204, program block 201, and Output block 2
05 data selectors and the specific controls that operate the logic units. The basic command word format and command map are illustrated in FIG. Referring to FIG. 5, I bit 23
0 distinguishes jumps from non-jump instructions. I
When bit 230 is a logic 0, the instruction is a jump instruction, and M bit 231 distinguishes between true and false condition jumps, while the remaining bits in M field 232, S field 233, R field 234, and Σ field 235 are jump instructions. Contains the absolute address associated with. The command is a jump command (I
(indicated by a logic 0 bit), but if the jump condition is not satisfied, normal program counter incrementation occurs. If the I bit is a logic one, a register or FLAG operation is decoded. The entire M field 232 is used to distinguish registers from FLAG operations as detailed in Table 1 below. M field 23
If the binary code contained in 2 is between 0 and 9, the register operation is decoded and the M field 23
FLAG if the binary code contained in 2 is between 10 and 15
Operations are decoded. For register operations, 10 from M=0 to M=9
The code is used to select one of a six number mask in combination with one of three constant values (N). The selections shown in Table 1 are used in programming the floating point calculator functions according to the present invention. In the case of FLAG operations, the 6 codes from M=10 to M=15 are the 6 types of FLAG codes: comparison, exchange,
Used to distinguish between set, reset, toggle and test.

【table】

[Table] S bit 233 of the command word is data block 2
Controls three functional elements of 04. S bit 23
3 distinguishes addition from binary or BCD adder 217 operations, left shifts from right shifts in the Σ shift logic, and A from B in the FLAG arithmetic logic. Addition, shift and FLAG operations are exceptional operations and do not require further decoding. R
Field 234 distinguishes between arithmetic, commutative, and keyboard input commands described with respect to the table below. The binary value contained in the R field 234 is 1
and 5, an arithmetic operation is indicated and the U data selector gate 215 and V data selector gate 216 are controlled to activate the variables shown in Table 1 as inputs to the adder 217. .
When the binary value contained in R field 234 is equal to 6, it bypasses summation value 217 and Σ gate 218 and enables the exchange of A and B without using a numeric mask. 2 included in R field 234
When the hexadecimal value is 0 or 7, no arithmetic operations are indicated and provide a device for implementing special commands for keyboard synchronization and encoding. The Σ field 235 inputs Σ data to the A register 211, B register 212, and C register 213.
Selection of output from selector gate 218 or Σ
Decide not to send the data selector output to any of these. As shown in the table, three types of codes can be decoded and the output of the Σ data selector gate 218 can be input to the A register 211, B register 212, and C register 213, and the fourth code is keyboard synchronization and encoding. Provides a device for non-operational codes to activate commands.

【table】

[Table] Jump condition circuit 192 reflects the state of the calculator at any point during the execution of a fixed program. This is combined with the Ma bit 231 to determine whether the jump instruction was executed or skipped. The jump condition circuit 192 includes the result of the arithmetic carry-borrow (C/B), the contents of a FLAG test or comparison (FA:FB) for FLAG pairs having a common (FMSK) address, and the keyboard in normal scan order.・Switch key matrix ・Scanned continuity of intersection points (closed equals 1)
state, or a specific digit scanner state, e.g. D11
is loaded. The carry-borrow and FLAG inputs to jump condition circuit 192 provide a convenient means for branching, so that continuous program execution is
data results, arithmetic register operations, and e.g. 2
This can be done depending on each of the current states of the computing device indicated by any of a plurality of state memories (FLAGs), such as in the illustrated embodiment where six FLAGs are available. The key matrix and numeric scanner inputs to the jump condition circuit 192 are provided by a plurality of keyboard inputs under program control, e.g., four in the illustrated embodiment.
To provide a device for conveniently and effectively synchronizing and encoding four inputs. The table shows the coding and operation of these instructions. The WAIT operation causes the controller to recycle program counter (PC) 209 to its current value (not incremented) until the WAIT condition (D11, KN, or KP) is satisfied.
Further, the register operation of subtracting the number 1 from the mantissa of the A register 211 is associated with the D11 WAIT condition, and associated with the KN and KP, WAIT condition instructions. Logical shift and FLAG initialization instructions are also shown in the table.

Timing Block 203 The function of the subsystems within timing block 203 is to generate a three-phase internal clock (internal to the monolithic structure of the preferred MOS embodiment) from an external unit phase oscillator voltage and to It generates internal state and digital timing and provides numeric and FLAG mask decoders. The basic instruction cycle timing of the calculator is illustrated in FIG. The φ system timing input 240 is a square wave provided by an oscillator with approximately a 50% duty cycle. The three internal clocks φ ₁ , φ ₂ , φ ₃ each have a signal 24
1,242,243, which is a circular ring
A counter is derived from the φ system clock. Due to the binary coded decimal parallel arithmetic used in accordance with the present invention, each digit added or subtracted uses a complete set of clock pulses φ ₁ , φ ₂ , φ ₃ . A complete set of clock pulses is considered a state, e.g., the first
Just consider the state _S1 . Data block 204
There are 13 said states S ₁ -S ₁₃ corresponding to the 13 digit cycles of the registers 211-213. The 13 states are the feedback shift counter (17th
state counter 589 and its feedback loop). 13 states and 13
The numeric registers allow storage of a number consisting of 13 digits at the timing indicated by the solid line in Figure 6, but the generalized floating point notation is more convenient from the point of view of program storage and data processing. Used according to the invention. This is done by masking or sub-addressing registers 211-213 to mask or isolate the following six specific field masks: the mantissa field 245 with N digits, the first of which is the least significant digit (LSD), the last of which is the overflow digit (OVF) and its (N-1)th digit is the most significant digit (MSD), so mantissa, LSD,
Masks are used for MSD and OVF. There is also provision for exponential (EXP) and decimal point (DPT) masks. These six masks are generated in the numeric mask decoder as commanded by the M mask field 232 of the instruction word. According to the invention, since the masks are separately adjustable, it is possible to accommodate variable function devices within the calculator device. In MOS embodiments, mask changes are made by changing the gate oxide mask during the manufacturing process to change computer operation. For example, one variation example sets one or more of six masks to cover two numbers,
The adder circuit of the data block is controlled to operate in hexadecimal instead of binary coded decimal notation, allowing the computing device to process 8-bit binary characters. In addition to the numeric mask unit, the timing block 203 subsystem controls FLAG addressing. FLAG addressing is basically
This is a 1 out of 13 selection and is made by the FLAG mask decoder. FIG. 7 illustrates the scan cycle timing of the keyboard and display scanner and relates the scan cycles to command cycle timing times. According to this embodiment of the invention, keyboard input and display output are scanned by the same scanning signal. In this manner, the number of pins required to accommodate the device as a monolithically integrated semiconductor structure is reduced to a minimum and internal device logic is simplified. In addition to conventional displays, such as neon tube displays, for example, it is desirable to scan at a sufficiently slow speed that is consistent with liquid crystal displays, while at the same time calculating at very high speeds. The scanning apparatus of the present invention therefore operates by including multiple instruction cycles within one scan cycle. In the illustrated embodiment, a ten-digit numeric display plus an error (E) signal or one such as a minus (-) sign.
There are 11 scanning signals, enough for numerical control display.
This also allows efficient encoding of keyboard input routines. During each digit time, one digit of a particular register, such as D11 with a logic 1 signal 251, is decoded synchronously. To play the various numbers in a particular register in sequence, the output decoder is doubly buffered. The buffer input is state 2 corresponding to (equivalent: Si◎Di)
The time is set to 52. The output is timed to a fixed state, eg signal 253 in state _S13 , which is synchronized with the digit scanning cycle. In this manner, each digit from the register is played in sequence and displayed synchronously during the digit scanning cycle. The numeric counter itself is timed by a specific state, _e.g.
It is operated by a feed back shift counter similar to a counter. That is, D ₁₁ shown in FIG.
_At each scan timing from D1 _{to D1} , these correspond to each of the state scan timings _S11 to S1 ( _D11 corresponds to S11, _D10 corresponds to _S10 ... _D1 corresponds to
S ₁ ) to play various numbers in each register.
In this example, the numerical feed, back, shift,
The counter counts down with modi-euro 11, while the status counter counts up with modi-euro 13. The real-time maximum digit first scan produced in this manner provides a means for implementing the zero erasure logic of the display. The illustrated numeric mask described with respect to FIG. 6 is more clearly illustrated in FIG. Figure 8 shows A register 211, B register 212, and C register 21.
3. Data formats of the FA FLAG storage element 226, the FB FLAG storage element 227, and the display section are illustrated.
An example number is shown in register format 260 to clarify the operation of the number mask. In the illustrated example, the decimal point (DPT) is shown as being equal to two. Therefore, in display format 261, the decimal point appears at position D3. In the example above, the mantissa field is shown for an 8-digit calculator device and is S ₁₁
Exist between S _{and 13} . Although there are no general requirements for the FLAG format 262, in this embodiment the _S11 mask or time address of the FA FLAG storage element 226 and the FB FLAG
It is convenient to allocate storage element 227 to storage of negative (-) and error (E) FLAGS for display. In this way, the segment decoder 19
8 and output block 205 are greatly simplified. Finally, the timing block 203 subsystem includes key input logic. The function performed by this logic is synchronization with internal instruction cycle buffering. With the present calculator device, there is no need to provide hardware hardware to counteract transient noise, mechanical key vibration or double keystrokes; each of these functions is included in fixed program routines. Program Block 201 As shown in FIG. 2, the subsystems of program block 201 include read-only memory (ROM) 208 and program counter (PC).
209 included. Read-only memory 208 serves as storage for a linear program list, which in this embodiment contains 320 11-bit instruction words to provide fixed programs to perform specific computer functions. Various embodiments of the computing device can therefore be obtained by providing a program-like combination of read-only memory 208. The read-only memory 208 is described in U.S. Pat.
Programmed according to the technique described in No. 3541343. The program includes keyboard input routines, internal format routines, internal calculation routines, and display format routines. Specific programs used in connection with the desktop calculator function of the calculator device of the present invention and programs for the calculator device that perform other functions are described in the following sections. In this application, program counter 209 is a 9-bit counter that receives new input during each instruction cycle.
It is a dynamic storage register. The new input is either the program count itself, the program count incremented by 1, or the 9 bits from the previous instruction word. These three inputs provide each of a WAIT instruction, a normal arithmetic instruction, and a jump instruction. One function of program block 201 is to provide a cancellation mechanism to prevent malfunctions in the keyboard encoding process. The input sensing program provides protection against transient noise, double input, leading edge vibration, and trailing edge vibration as shown in FIG. The ``IDLE'' routine KOs until it detects a non-stationary input.
Continuously scan [KN] and [KQ] inputs. The input is sampled again by the "TPOS" routine after 2.5 milliseconds to distinguish correct key presses from excessive noise. If the test result is positive, then (5 milliseconds after the first detection) the program jumps to the 'NBR' or 'OPN' input routine, otherwise returns to the 'IDLE' routine. The 'NBR' routine places the keyed number into the display register, and 'OPN' executes the keyed operation. Both routines terminate with a jump to the 'TNEG' routine. ``TNEG'' uses [KN], [KO] to determine that all keyboards are in a static state.
and [KQ] Executes scanning of input. If the test is successful (if negative), the program jumps to the ``IDLE'' routine. The following five types of keyboard input and result program routines are used to perform computational or logical functions on a calculator device. These are number keys, mode switch, decimal point switch, arithmetic keys, and interlock keys. The difference between a "key" and a "switch" is that a key is momentarily and exceptionally operated, whereas a switch is generally stationary and has a normally closed position. The types of programs are explained by examples, for example a calculator keyboard using these keys is number 10 and 1.
This is shown in Figure 1. Numeric keys: There are 10 keys and a decimal point key.

[0], [1], [2], [3], [4], [5], [
6],
[7], [8], and

The operation of the [9] key shifts the display register one digit to the left and puts the corresponding number in the minimum digit. The [...] keys are operated in the normal sequence for entering numbers. If this is not used, the decimal point is assumed to follow the last digit entered. Input mode is always floating format. Mode switch: Constant switch [K] selects chain operation and constant operation. Normal operations on a calculator with the constant key [K] turned up (open) enable chain calculations without losing intermediate results.
An alternative operation that downs (closes) [K] allows constant arithmetic operations. Decimal point switch: 11-position switch [F]- for floating or fixed mode operations

[9]-[8]-[7]-
[6]-[5]-[4]-[3]-[2]-[1]-[
0].

From [0]

Positions up to [9] are used for fixed-point calculation results, and position [F] selects floating calculations. Arithmetic keys: 10 numeric keys, 2 mode switches, 11-position decimal point switch, and 44 matrix crossover points, leaving space for a total of 21 possible keys. These key positions are number 10
and 11 are sufficient to include the two primary keyboard features illustrated in FIGS. [+] stores an addition command and executes a possible preceding operation, [-] stores a subtraction command and executes a possible preceding operation, and [×] stores a multiplication command and executes a possible preceding operation. execute,
[÷] memorizes the division command and performs possible advance operations, [+/-] changes the sign of the display register,
[=] performs the preceding operation and stores a clear command for the next number entered, [〓] enters the last keyed-in number into the calculator and performs any possible preceding operations, and [ 〓〕 enters the last keyed-in number into the calculator as a negative number, [C] clears three registers and all preceding operations,
[CI] clears the display register. Interlock key: Routine (instantaneous)
It is a functional combination of arithmetic keys and a (static) mode switch. These provide a mechanism for interlocking the operation of a computing device with the operations of other devices. In particular, the calculator device is programmed for at least three different types of use cases by operation of interlock key routines: i.e. a computer device (master) controlling a slave device (e.g. printing mechanism or print control circuit), slave operation of the computer device by the master device (e.g. remote control by real-time communication medium), priority determination and mutual communication. multi-processing by a plurality of computing devices of the present invention according to pre-programmed interlock routines to perform the processing; Output Block 205 In the described embodiment of the calculator device, 22 outputs are provided for display and keyboard scanning and for synchronously decoding the contents of the display register. Referring to FIG. 12, numeric output scanner 197
number drivers (D1, D2, D3, D4, D
5, D6, D7, D8, D9, D10, D11)
The output is used to scan code the keyboard and scan the display. The internal digit blanking signal is gate mask programmed to disable the digit drivers of a particular display interface. The polarity of the digit signal is positive, i.e. D
During _i , D _i is conductive to VSS. This is provided in the MOS calculator device embodiment described to effectively scan the keyboard matrix. Segment driver of segment decoder 198 (SA, SB, SC, SD, SE, SF, SG,
The SH, SI, SJ, SP) outputs are gate mask programmed for direct compatibility with 7- and 8-segment (plus decimal point) displays. In addition to segment codes, it is possible to select both internal numeric blanking and segment polarity. The internal digit blanking signal is therefore programmable in 12 microsecond (nominal) increments and can be applied to the numeric drivers or the segment drivers or both.
All leading zeros (high zero or non-zero digits before the decimal point) are erased by deactivating the segment driver. The described calculator embodiment digit and segment decoder is programmed for a 7-bar digit blank characteristic with a positive segment decode (segment A "on" is decoded as SA conducting to VSS). has been done. The display characters are illustrated in FIG. The complete coding of numbers, error (E) and minus (-) indications is shown. SH is not used for display, but is useful for output information for testing. SI and SJ are available in hardware for use in numeric displays with one terminal (ie cathode) per digit. However, these outputs are not used for segment display in order to accommodate the monolithically integrated semiconductor implementation of the calculator device in a 28 pin package. For example, if the clock time is 4 microseconds, the scan rate is 156 microseconds per digit. For example, this embodiment uses 12 microsecond leading edge blanking and 12 microseconds for numeric drivers only.
Programmed to be microsecond trailing edge blanking. Therefore, as shown in FIG. 14, the segment drive covers the numeric drive. An interface circuit including a common cathode, 7-bar LED display bipolar transistor 15 is illustrated in FIG. The interface circuit of this embodiment is fabricated on a separate semiconductor substrate. FIG. 16 illustrates the key assignments of the described calculator embodiment. Each key, e.g. 340, is a normally open single-pole type single throw switch and represents a particular input routine programmed into ROM 208. Some of the "mode switches" mentioned earlier in the Program Blocks section may be in the form of jumper wires in some embodiments, allowing a particular mode to be permanently selected for a particular model or family of equipment. Conceivable. In this way, a "master program" containing an embodiment of the invention can cover all cases of different computational characteristics economically and easily. Logic and Circuit Description of MOS Calculator Device Embodiment The calculator device according to the present invention has been described in terms of functionality within each block of FIGS. In the following sections, the computer equipment is the current MOS
Alternatively, logic devices and circuit elements including this computer device embodiment that can be processed as a monolithic integrated semiconductor device using MIS processing technology will be described. Keyboard shown separately in Figure 16, Nos. 12 to 1
The complete calculator device of this embodiment will now be described, except for the display element shown separately in FIG. 4 and the display driver shown separately in FIG. 15. Logic of Figure 17/
The circuit diagram includes 26 drawings, drawings 17A through 17Z which are grouped together as shown in FIG. The functional elements described in the previous section are identified by the same numbers in FIG. In the program block 201, the program counter 209 is
A 9-bit address 501 is given to ROM2
Data output 502 from 08 is the instruction register 19
Sent to 0. In control block 202, instruction register 190
The output 503 of the jump control circuit 192 and the R decoder 191 of the control decoder 191 of the control section 202
A, control decoder 191B, Σ decoder 191
C, and the mask of timing block 203.
FLAG mask decoder circuit 195A of decoder circuit 195 and numeric mask decoder circuit 195
distributed to B. R decoder output 504 controls u data selector gate 215 and V data selector gate 216 of data arithmetic logic unit 207. Condition output 5 of jump condition circuit 192
07 controls jump gate 508 in program counter functional element 209. Σ decoder 1
91C output 509 is data arithmetic logic unit 207
A data selector gate 219, B data selector gate 220, and C data selector gate 221 are controlled. Control decoder 1
Output 513 of 91B operates condition selector gate 514 in jump condition circuit 192. Output 515 of control decoder 191B operates WAIT-KN-KP selector gate 516 of keyboard input circuit 196. The output 517 of control decoder 191B is connected to Σ gate 218 in arithmetic logic unit 207.
operate. In timing block 203, the output 518 of FLAG mask decoder 195 drives FA FLAG arithmetic logic gate 519 and FB FLAG arithmetic logic gate 520. FLAG mask decoder 1
The output 521 of 95A is the keyboard input logic section 19
6, the keyboard synchronization buffer control circuit 522 is operated. Output 523 of FLAG mask decoder 195A provides a sync time pulse to jump condition circuit 192. The output 524 of the numeric mask decoder 195B is input to the R decoder 191A, and is also used to separate the FLAG command from the data calculation command.
It is input to FLAG mask decoder 195A.
Output 526 from numeric mask decoder 195B
is the sub-addressing timing mask.
Σ decoder output 5
A data in the arithmetic logic unit 207 through 09
Selector gate 510, B data selector
Gate 511 and C data selector gate 5
12 and further to the carry borrow detection gate 528 of the jump condition circuit 192. The output 529 of numeric mask decoder 195B provides a right shift command to Σ gate control circuit 527 in arithmetic logic unit 207. The output signal 536 of the A register 211 of the FLAG and data storage array 206 is transmitted to the AA buffer circuit 542 in the segment decoder 198. The following sections provide a detailed circuit description of blocks 201-205. For a better understanding of the calculator device, logic notation and its MOS circuit equivalents will now be described with reference to FIGS. 18A-D. FIG. 17 is written using conventional logic notation using positive logic. However, other notations are included to clarify the particular MOS circuit implementation selected to meet the transient, voltage level, and timing requirements of the device. FIG. 18A illustrates five different inverters appearing in FIG. 17 and their respective equivalent MOS circuits. Similarly, FIG. 18B illustrates five corresponding NAND gate types and their associated equivalent MOS circuits, and FIG. 18C illustrates five corresponding NOR gate types and their equivalent MOS circuits. The individual different types of MOS circuits shown in each of Figures 18A-C are as follows: Logic symbol 552 without internal symbols is a conventional load ratio circuit. A logic symbol 553 with one numeric symbol 1, 2 or 3 indicates a dynamic implementation of a logic function with a clocked load .phi.I, where I is a symbol. This type of circuit is used for low power consumption and to reduce the number of supply lines (DC voltage and clock) used in arrays that do not require a gate bias voltage V _GG . Logic symbol 554 with two numerical symbols IJ represents the residual charge and conditional discharge of φI.
shows the implementation of a logic function using a special ratioless form circuit with J, where I and J represent the set (1,
The elements and conditions of 2 and 3) are logical conditions for conduction. This form of circuit reduces power, so
Used to reduce cell size and/or increase circuit speed. Logic symbol 555 having the symbol G is hereinafter referred to as performing a logic function using the boot strap load circuit described in detail. Finally, the logic symbol 556 with the symbol OD signifies the implementation of the logic function using an open drain circuit. This type of circuit is used in wire-OR logic, where only one of several combined logic gates requires a load. Logic and circuit description of data block 204 Data block 204 includes A register 211,
B register 212, C register 213, FA
FLAG data storage register 226 and FB
Random access type memory including FLAG data storage register 227, array shift register unit 206 and decimal data arithmetic logic unit 2
07 and FLAG logic 229. memory·
Array shift register device 206 is 12×14
, a 12.times.14 array of charge storage cells 10 , or matrix 546 , and a commutator device 545 for operating a dynamic shift register delay circuit 214 . Charge storage cell 1
A matrix 546 of 0 and dynamic shift register delay circuits 214 provides parallel shift storage for three 13 digit numbers and 26 binary numbers FLAG. The commutator device 545 has 12 shift register cells 541 (19th (shown in detail in the figure). In this manner, shift register cell 541 can continuously distribute a common read/write control signal to adjacent rows of matrix (storage array) 546. To provide a rotationally stable image exchange corresponding to the desired characteristics of 14 parallel shifting shift registers of 13 bit length with one input and one output for each of the 14 columns of the array. has another device 547,5 in the switching circuit.
44 will be provided. NAND circuit 547 and delay element 5
44 eliminates multimode oscillations corresponding to cycling one or more read/write controls to rotation. An equivalent MOS circuit for shift register cell 541 is illustrated in FIG. Each shift register cell 541 includes a conventional six MOS transistor shift register bit section and uses a capacitive boot strap effect to provide superior transient response compared to conventional load circuits. It includes a load circuit 548 and includes an RP pulse activation 550 from a cell 543 and kill circuit 551 that limits the time interval of read/write control pulses to the time interval of clock φ2. The circuit of cell 543 is shown in detail in FIG.
The timing pulse RP is generated by a counter-inverting amplifier circuit with inputs from 2. Referring again to FIG. 17, A data selector gate 219, B data selector gate 220 and C data selector gate 221 are connected to A register 211 (columns A1, A2, A4 and A8), B register 212, respectively. (Columns B1, B2, B4
and B8) and C register 213 (columns C1, C
2, C4 and C8) are coupled to respective selector gates 510, 511, 512. A register 211, B register 212 and C
Output devices 536, 537, 53 of register 213
Each of 8 is connected to a data selector through a 1-bit dynamic shift register delay circuit 214.
Normal input NA of gate 219, NB of data selector gate 220 and data selector
Return to Gate 221 NC and complete the circulation path.
In addition to the normal path, Σ data selector gate 2
18 is ΣA of A data selector gate 219
Σ of control or B data selector gate 220
It can be selected by B control or ΣC control of C data selector gate 221. In addition to these paths, output devices 53 of A register 211 and B register 212 are transmitted through delay cell 214.
6,537 is capable of energizing B data selector gate 220 and A data selector gate 219, respectively, by an exchange control in combination with the ΣA and ΣB controls as described above with respect to FIG. All of the normal Σ and exchange control parts are connected to the data selector gate 21 by the Σ decoder 191C.
9,220,221. Dynamic shift register delay circuit 21
A register 21 delayed by the first half of 4
1 output device 536 and C register 213 output device 538 are selected by U data selector gate 215 to be on the positive side of adder 217 (usually only here). Similarly, dynamic shift
The output device 537 of B register 212 delayed by the first half of register delay circuit 214 and the constant N generated by device 524 are selected by data selector gate 216 to the negative side of adder 217 (usually only here ). Exclusive OR circuit 554 performs its normal (addition) operation at node 55.
Regarding polarity, it is used to conditionally complement the V input to adder 217 and when said complement condition is a subtraction command from output 503 of command register 190. U data selector gate 215
The U output 552 from It is summed by a ripple carry adder cell 556 along with a carry input 557 to generate an advance carry signal. Binary sum generated at node 558 and node 5
The carry that occurred at 59 is processed by logic unit 563.
Depending on the states of the CK control section 564 and the CBRS control 565, the decimal sum and the carry at the T adder node 560 and internal digit carry node 561 are corrected. Controls 564 and 565 are used to select binary codes rather than binary coded decimal (BCD) operations and to block internal digit carries in selected fields of register data rotation. The output 560 of the T adder 563 is a no shift (NS) or ripple carry addition cell (delay element) 5
56 and the left shift (LS) Σ path through the Σ data selector gate 218. Σ data selector gate 218 also enables a right shift path by using inverted U and inverted V inputs 553 at input 552. The Σ gate control circuit 527 sends a left or right shift command to the Σ data selector gate 218.
and energizes the no-shift path if both left shift or right shift commands are not present. In addition, if a left shift command is present, the Σ gate control circuit 527 controls the digits used by the left shift delay element 566 to block the first digit and ensure zero insertion at the masked lowest digit. Generates leading edge detection on output 526 for mask control. FLAG logic 229, which is generally similar to the register manipulation logic of arithmetic logic unit 207, completes the loop generated by data storage array 206. F.A.
The output devices of storage cell 568 and FB storage cell 569 are normally circular inputs to FAFLAG arithmetic logic gate 519 and FBFLAG arithmetic logic gate 520 of FLAG logic unit 229 and jump condition circuit 1.
92 to FLAG selection gate 570.
This is the output from the numeric mask decoder 195B.
FLAG command input 518 is input to command register 503,
FMSK control signal 5 by the SUB bit of (FA or FB) and from FLAG mask decoder 195A.
19' allows a particular FLAG (selecting one of 13 time slots or states) to be set, reset or toggled when addressed. Furthermore, the FA and FB pair of FLAG in the same time slot (FMSK) is the FLG which is the output from the numeric mask decoder 195B.
It is replaced by command 518. FA and FBFLAG
Arithmetic logic gates 519 and 520 provide FLAG data to FLAG data storage array input devices 505 and 506, respectively, to complete the intermediate gates for FLAG. Logic and Circuit Description of Control Block 202 The control block 202 includes instruction registers 190,R
It includes a decoder 191A, a control decoder 191B, a Σ decoder 191C, and a jump condition circuit 192. The instruction register 190 has 11 converters 575
, whose input is the boot strap
Data output 502 of program block ROM 208 is sampled by NAND gate 571 once per instruction cycle. The R, control and Σ decoder 191, illustrated in FIG. 17 along with other decoders, is programmable and structurally similar to a read-only (ROM) decoder/encoder circuit, except that the decoder is not fully generated. implemented in a logical array. That is, in an N-bit address ROM, ^2N locations are decoded, whereas in a PLA, only the desired state is decoded. For example, the PLA illustrated in FIG.
think of. True and complement polarity A and B inputs 5
71' are both the first half of PLA (decoder)
given to. In this example, four product terms (decoder outputs) 572 are provided as inputs to the second (encoder) array. Decoder gate 57
The circuits 2' and encoder gate 573 are similar branch gates. That is, it is a logic NAND gate. However, NAND-NAND logic
Since it is reduced to AND-OR logic, if the dependence of a particular product term on a particular input is represented by a circle at the junction as shown in 574, for example,
It is convenient to use sum-of-products notation to describe PLA circuit implementations. Due to the programmable gate mask used during fabrication of the MOS embodiments, the circles also correspond to the physical placement of the MOS gates. According to the above notation for the decoder (PLA), the Σ decoder 191C controls the output 509 obtained from the ΣA and ΣB inputs from the output 503 of the instruction register 190, and the output 504 for the EX exchange command from the R decoder 191A. Output 526 for numeric mask from numeric mask decoder 195B
It has a 4-term decoder circuit 578 and a 4-line output encoder section 579 for decoding. Similarly, the R decoder 191A converts the output 503 of the R field 234 of the instruction 190 into the 7-term decode array 58.
Output 504 for UV commands CU, AU, BV and EX using 1 and 5 line output encoder array 582
and converts it to R7WAIT condition code 580. All terms of R decode matrix 581 are output 50
I-bit 23 of instruction register 190 at
Conditioned by the true state of 0 and by the inverted state of the FLAG signal 525. Control decoder 1
91B decodes command control for specific keyboard commands: output 513 indicating keyboard condition, output 515 indicating keyboard WAIT, and output 517 indicating left shift right shift. Control decoder 1
91B uses a 12-term decoder 583 and a 9-line output encoder array 584. Jump condition circuit 192 includes keyboard condition selector gate 514, carry borrow selector
Gate 528 and FLAG test and comparison gate 5
A latch circuit 584 cross-coupling the input from 70 to the SET side of the latch, a timing input 585 to the reset side of the latch, and a condition output 507 for decoding the jump command and controlling the jump condition when the jump condition is true. and a gate circuit 586 that energizes the jump gate 508. Logic and Circuit Description of Timing Block 203 Timing block 203 includes a clock generator 193, a state and numeric timing generator 194,
Numeric and FLAG mask decoder array 195
and key input logic 196 . The total timing information of the calculator device is approximately 250
It is provided by a KHz square wave generator or oscillator (external to the monolithic semiconductor device shown in FIG. 17). Input clock lead C, as shown by φ terminal 503 in FIG. 17X, provides a means for applying an external clock signal to the monolithic calculator device. Both the basic clock shown in FIG. 17X and the three-phase clock shown in FIG. 17Z are incorporated into a monolithic semiconductor device. The square wave φ is immediately divided into 5
31,532, it is divided into square waves φ _B1 and φ _B2 having half frequencies of opposite polarity. 2-phase clock output φ
_B1 and φ _B2 are also 3-bit ring counters 58
The three-phase clock φ _1L φ, φ _2L , φ _3L as the basic clock system for all logic and circuit elements of the computer device embodiment of FIG.
is given by 533,534,535. A timing generator 194 for generating state and numeric timing signals includes dynamic shift register elements to provide a state counter 589, a numeric counter 590, a state digit comparator 591, a state decoder 592, and a numeric decoder 593.
It uses PLA logic. The recoded state decoder output 594 is distributed to other functional elements to provide a means for making arbitrary selections of state timing for each of six independent timing buses. State decoder output 595 is also distributed as required by other circuit elements of FIG. In addition to providing a means for obtaining the correct feed back of the numeric feed back shift register, the output of numeric decoder 593 drives numeric output scanner 197. Here, PLA of Figure 17I
is used as an array for searching for the decimal place and sending information for displaying the decimal point to the segment output decoder 198 shown in FIG. 17E. The 13 product terms of FLAG mask decoder 195 are the R
and from each of the Σ fields 234 and 235.
FLAG address, SA, SB of status counter S,
596 generates a FLAG addressing signal FMSK which is used to correspond to the 1 to 13 states decoded from the SC and SD inputs and is gated to the FLAG operation logic gates 519 and 520 as the timing address for the FLAG operation. let Similarly, numeric mask decoder 195B outputs 503
M field 23 of instruction register 190 in
2 and provides a numeric mask signal 526 from the state counter 589. In this way, arbitrary set-reset related correspondences between states and masks for each of six different masks can be obtained. In addition to the numeric mask, the numeric mask decoder 195B
FLAG control output 518, right shift control output 5
29 and the constant N generation output 524 are decoded. Logic and Circuit Description of Output Block 205 The segment output subsystem 198 includes a delay element 542 that buffers the output device 536 of the data storage array 206, a segment decoder (PLA) 601, and a terminal 576 with eleven decoded segment output signals. It includes an output buffer circuit 602 that drives the . The segment decode array has 10 product terms for devices that decode numeric information for selective recombination. namely, the encoding of the numeric segment output 602' and the product term and feedback signal 603 for decoding FLAG information (eg, error or minus sign) and zero erasure. The digit output scanner 197 has 11 two inputs that block the output of the digit decoder 593 with a digit BLANK signal 606 for internal digit blanking capability.
It includes a NAND gate 604 and an output buffer circuit 605 that drives a terminal 576 for scanning the keyboard and display section as described above. Logic, circuit and program description of program block 201 As mentioned above, program block 201
includes a program counter (PC) 209 and a read only memory (ROM) 208. Both program counter 209 and read-only memory 208 perform the address modifications required for each instruction and provide control block 202 with, for example, an 11-bit input to instruction register (IR) 190 in the described embodiment. Address modifications required for the current instruction include no modification for a WAIT operation, a binary 1 addition for a normal increment operation, and a 9 from instruction register 190 for a jump operation that is not executed, or a jump operation that is executed. Program the bits
Either replace all 9 bits of the counter. An unmodified WAIT operation, a binary 1 addition for a normal increment operation, and a jump operation that is not executed are stored in the program counter 209.
Either recirculate the LSD output 652 or add 1 to the LSD and send it to the program counter 209.
Key input logic 196 in timing block 203, each of which cycles to MSB.
This is satisfied by sending a serial input 651 from to the MSD of program counter 209. In both cases the circulation is synchronous with the instruction cycle.
For a jump operation to be performed, replacing the 9 bits from instruction register 190 with a full 9-bit count is performed in state S12 of the instruction cycle.
jump condition circuit 192 to input 653 of all bits of program counter 209 simultaneously during
is satisfied by strobing the output 503 of the instruction register 190 in parallel with the output of . The output of the instruction word to the control block's instruction register 190 is strobed by a NAND gate 654 which provides a new input to the instruction register 190 every instruction cycle during state S13. The serial circulation of program counter 209 is from S3 to S12.
is provided by a conventional shift register bit 656 which is clocked by a NAND gate 655 in between. The ROM is configured for each bit output 503 of the instruction register 190 to drive an array of 5 NAND gates per bit or a total of 55 NAND gates.
Contains a decoder that extracts one of the 64 items. One of these five gates is addressed by an encoder that takes one out of five gates for each bit. Therefore, a maximum of 320 11-bit word stores are provided to be selected (decoded and encoded) for random addressing of any one word. The program block 201 of this calculator embodiment includes a programmable read-only memory 208 for storing fixed programs.
including. In another embodiment, however, a read-write memory replaces the read-only memory 208, providing a device for continuously changing the stored program and therefore the operation of the calculator device. Calculator calculations can be performed by making a computer calculation program resident in memory, but flow charts corresponding to program processing in one embodiment of the variable function computer device are shown in 22A to 22T. Illustrated in the figure. In addition, an example of the operating procedure for solving calculation problems by keyboard operations is shown in Table 1.

【table】

【table】

【table】

[Table] Referring to FIG. 22, the flow of the calculator program logic is as follows. Figure 22A provides the key to flow chart notation. The shape of the box is used to distinguish between different types of instructions, and the symbol inside the box is used to designate a particular instruction within the specified type. Yen symbols are labels, e.g. GO and Figure 22A.
Used as CONT. Rectangles represent assignments. Arrows are used for register operations with subscripts representing numeric masks. For flag operations, a rectangle with extra lines is used and instructions are provided along with a memory or alphanumeric identification of the flag to be modified. The inertia symbol is used for all test operations including test flag, compare flag, and compare register instructions. Diamonds are used for branch conditional instructions, where the indicated condition is related to a preceding test or register (carry/borrow) operation. Hexadecimal symbols are used for WAIT operations.
In addition to the WAIT condition, a related operation D ₁₁ or KN, such as 1 addition, is indicated. In Figures 22B to 22T, the three-digit hexadecimal code number written at each step of the flowchart is the ROM location (PC value) of the corresponding IR code written in the read-only memory (ROM) 208.
represents. Referring to Figure 22B, the basic control combines the four basic operations (〓, 〓, ×, ÷) routines, determines the current operation and previous operation state by flag testing, and updates the illustrated decision tree. The routine is shown. Referring to FIG. 22C, the clear entry (CE), decimal point (DPT), clear (C), and data entry routines are shown. CLEAR is described in 000-003 and provides a means to clear all flags and A and C registers and return to LOCK. The clear input is located at location 058 and is used at 021 to clear the A register and associated flags.
Branch to D2 routine. Data entry is a control routine for numeric key input and decimal point switch routines, starting at location OIE. Referring to FIG. 22D, all operating routines with LOCK provide a device to prevent double keystrokes and multiple executions of single operation entries by testing the quiescence (open circuit) of all momentary keyboard inputs. end. LOCK is at positions 004 to 008 and branches to IDLE for quiescence. In the two WAIT loops at positions 009 to 010, IDLE provides a means to cancel leading edge key vibrations and transient noise. Referring to FIG. 22E, OPN provides a device for interrogating keyboard input (KO key) to determine which operation is requested.
This is done by a list of branch conditional instructions,
Its execution order corresponds to the order of key connections to the numeric scanning output, and the WAIT D11 instruction synchronizes the query to the scanning cycle, and the KO→
COND allows conditional branching of the state of keyboard input. OPN is located in ROM 011 and 01D, and if no previous jump is performed,
Ends with a data entry jump for numeric input. Referring to Figure 22F, the NBR provides a system for interrogating, scanning and encoding numeric keyboard input, such as numeric keys and decimal point switches.
This is done by the single instruction WAIT (D11+KN) in location 03A by (A-1A) to subtract "1" from the mantissa of A for each instruction cycle of the wait. Referring to Figures 22G, H, I, J, K, L, and M, addition/subtraction (AS) and prenormalization (PRE) are illustrated. These routines include various testing and formalization operations in addition to the actual execution of addition or subtraction. Referring to Figure 22 N, O, P, Q, R, R, S and T, multiplication/division (MD) and post normalization (POST) are shown. These routines use iterative additions and subtractions combined with shift, test, and count operations to perform the desired functions. FIG. 23 illustrates the actual relationship between the above-described signals and functions of this embodiment and the packaging technology of current integrated circuit technology. For example, the input/output terminals of this embodiment may be made of ceramic or plastic package leads using wire conductors and thermocompression bonding to make the device more accessible using conventional DIP printed circuit board processing. attached to the frame. In the described MOS embodiment of the computer device of the present invention, in the regular operating state, V _SS -V _DD and V _DD -V _GG
For example, nominal 7.2 volts (maximum 8.1 volts, minimum 6.6 volts)
bolt). Clock (φ) frequency is nominal
250KHz, minimum 200KHz, maximum 330KHz. Programming the Calculator Device for Non-Calculator Functions The calculator device of the present invention is a variable function calculator in that it can be programmed to perform functions other than the desktop calculator functions described above. The variable functionality of the device is essentially provided by the programmability of the various subsystems used in the device, such as programmable read-only memory and programmable logic arrays. As mentioned above, these programmable subsystems are optionally programmed during fabrication of the MOS or MIS embodiment by simply modifying the gate insulator mask. In other calculator embodiments, a number of other functions can be performed using different keys on the keyboard and/or different programs stored in ROM, such as right shift, exchange operation, square root, exponential operation, logarithm operation, It is possible to provide a device that includes double and triple zero operations and key order confirmation. The calculator device of the present invention includes program control, data control arithmetic and logic units, and input/output subsystems in various embodiments, but may also be programmed to perform non-calculator functions. For example, the calculator device may be programmed to perform meter functions such as digital volt meters, event counting, meter smoothing, taxi fare meters, odometers, weight scale meters, and the like. The device may also be programmed to perform cash register operations, act as controllers, arithmetic teaching devices, clocks, display decoders, automobile rally computers, and the like. As described above, according to the present invention, an electronic device controls a program storage means that permanently stores program instruction information for at least an input routine, an operation, and an output routine using a mask during the manufacturing process. (1) A mask such as a photomask in the printing process during the manufacturing process of the semiconductor device. By changing the program instruction information for operations, you can perform not only calculation functions but also various non-calculation functions,
For example, it can perform control functions, can be combined with a wide variety of input/output devices if the program instruction information for the input routines and/or output routines is modified for the input and/or output devices, Various electronic devices can be formed with a simple structure. (2) The fact that the function of a semiconductor device can be changed simply by changing the mask as described above during the manufacturing process of a semiconductor device means that the design and manufacturing of other aspects of the semiconductor device can basically be shared by all electronic devices. Therefore, it is possible to reduce the manufacturing cost of electronic devices and shorten the development period. (3) The fact that all means except the input device and the output device can be integrated on a single semiconductor substrate contributes to the miniaturization of electronic devices, which makes it possible to reduce the size of devices that were previously difficult or inconvenient to control electronically. For example, various devices such as household electrical appliances and office machines can be converted into electronic devices. (4) Being able to integrate each means on a single semiconductor substrate also reduces the number of semiconductor devices that make up an electronic device, which simplifies the assembly of electronic devices and facilitates component management. Contribute. Furthermore, as the number of semiconductor devices that make up an electronic device increases, chips for interface circuits between them are often required, and by eliminating the need for such chips for interface circuits, it is possible to reduce the manufacturing cost of electronic devices. I can figure it out. (5) Since the minimum necessary program command information determined from the functions of the electronic device is selected and fixedly stored in a part of the semiconductor device, each means can be integrated on a single semiconductor device. In turn, it can contribute to lowering the manufacturing cost of electronic devices, improving mass productivity, etc. Further, according to the present invention, each means integrated on a semiconductor substrate is connected by internal connection lines so that each information can be transmitted, so that (1) external wiring connecting semiconductor devices as in the conventional case;
Alternatively, it becomes unnecessary to use a substrate with a complicated conductor pattern, thereby reducing the manufacturing cost of the electronic device. (2) Being able to eliminate the need for connections using external wiring or conductor patterns printed on the board makes it possible to prevent poor connections that occur during the assembly of electronic devices, as well as disconnections that occur during use. reliability can be improved. Further, as described in the description of the embodiments, according to the present invention, the following excellent effects can be obtained. (1) By using a versatile electronic device in which the basic functions of an electronic computer are incorporated into a single semiconductor integrated circuit, an ultra-small and versatile electronic computing device can be obtained. (2) Make the number of keyboard input lines smaller than the number of keys,
The number of input terminals in a monolithic electronic device can be reduced. (3) An extremely small electronic device that has various functions capable of performing not only computer functions but also non-calculator functions by means of a program fixedly stored in a program storage circuit within a monolithic semiconductor integrated circuit. I can do it. A desired program can be arbitrarily set using a mask such as a photomask in the printing process during the manufacturing process of this semiconductor device. Therefore, the present invention can be applied to a very wide variety of fields. A user of this electronic device can recognize this semiconductor integrated circuit as a whole as a single, very small system. Therefore, even users who are not familiar with computers can easily use the present semiconductor integrated circuit as a subsystem within a larger or higher level system. (4) The design cycle of electronic devices with new programs can be shortened. According to the present invention, new devices requiring new functionality can be designed by changing the mask for the program storage circuit without fundamentally changing the rest of the monolithic semiconductor circuit. Testing steps normally required for new equipment essentially only need to be performed on the new program storage. Therefore, the process cycle from design, prototyping, testing to manufacturing can be significantly shortened. (5) The electronic device of the present invention can be easily mass-produced using semiconductor manufacturing technology. Therefore, manufacturing costs can be reduced and the fields of application of the electronic device of the present invention can be expanded. (6) The size of this electronic device, which can be applied to various fields with fixedly stored programs, is several mm.
can be reduced to within a square and traditional 28 pin or
It can be stored in a 48-pin package. Further, by using the electronic device of the present invention, a variable function fixed program computing device can be similarly miniaturized because the electronic device, which is an important part thereof, is small. (7) The size of the monolithic integrated circuit of which the electronic device according to the present invention is constructed is such that it has two memory functions.
two parts, namely read-only memory (ROM)
This can be reduced by dividing the memory into a program storage circuit, such as a program storage circuit, and a data memory circuit, such as a random access memory (RAM). This separation into two different types of memory allows efficient use of the limited area of the semiconductor chip. In the present invention, by configuring the semiconductor integrated circuit with insulated gate type transistors, the integration density within the monolithic integrated circuit can be made higher than that of bipolar type transistors. (8) The electrical reliability of electronic devices that can be applied to various fields is determined by configuring program memory, data memory, control circuits, arithmetic logic units, input circuits, and output circuits in small monolithic integrated circuits. Improvements are achieved by reducing the number of package pins and connecting lines by interconnecting within the circuit. Package pins and connecting wires introduce undesirable capacitance that can pick up electrical noise and cause malfunctions in electronic devices, but the present invention eliminates these disadvantages by reducing the number of package pins and connecting wires. can be prevented. Because the timing circuits that provide multiphase clock signals are integrated within a monolithic integrated circuit, various circuits according to the invention can receive clock signals within the chip, which also reduces the number of pins and connecting lines. can be done. (9) The mechanical reliability of the present electronic device, which can be applied to various fields, can be improved by reducing the number of package pins and connection lines in the system in which the present invention is used. This is because problems such as poor connections and disconnections that occur during the manufacturing process are reduced. Furthermore, when a computing device is configured using the present invention, its mechanical reliability can also be improved. (10) The number of integrated circuit chips for interface circuits in a system to which the present invention is applied can be reduced, and the design thereof can be easily performed.
That is, if an electronic device is composed of several integrated circuit chips, interface circuit chips are often required for connections between integrated circuit packages, and how many of these integrated circuit chips are used? It operates through that interface circuit. According to the present invention, since each circuit is constructed with a single chip, the number of chips for interface circuits can be reduced and the design of the entire system can be facilitated. As described above, the present invention can provide many valuable technical advantages, and at the same time can provide economic benefits to related industries. Although several embodiments of the invention have been described in detail, these descriptions of specific embodiments are merely illustrative of the principles underlying the inventive concept. Various modifications of the disclosed embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art without departing from the scope and spirit of the invention.

[Brief explanation of the drawing]

1 and 2 are block diagrams illustrating the computer apparatus of the present invention. FIG. 3 is a block diagram functionally describing data block 204 of one embodiment of the computer device of the present invention. Figure 4 is
2 is a block diagram of the FLAG register illustrating the operation of the register; FIG. FIG. 5 shows the basic command word format and command map used in the embodiment of the computer device.
FIG. 6 is a graph illustrating the basic instruction cycle timing of a computing device. FIG. 7 is a graph representing scan cycle timing for keyboard and display scans, relating scan cycles to instruction cycle timing times. Figure 8 shows A register, B register, C register,
FIG. 3 is a diagram showing data formats of a FA FLAG register, a FB FLAG register, and a display section. Figure 9 shows
2 is a graph representing keyboard program timing showing that the input sensing program provides protection against transient noise, double entry, leading edge vibration, and trailing edge vibration. Figures 10 and 11
The figure is a plan view showing an example of a computer keyboard used in connection with the present computer device. 1st
FIG. 2 is a circuit diagram of the display element showing the input connections to the numeric scanning circuit. FIG. 13 is a diagram showing typical display fonts of the display unit used in connection with the embodiments of the present invention. FIG. 14 is a graph illustrating how segment drives include numerical drives in an embodiment of the present invention. FIG. 15 is a circuit diagram of an interface circuit between a display element and a scanning circuit in an embodiment of the present invention. FIG. 16 is a circuit diagram of a keyboard used in conjunction with the described calculator embodiment, including interconnections to the scanning circuitry. 1st
FIG. 7 is a logic circuit diagram of a metal-insulator-semiconductor embodiment of the computer device of the present invention, including FIGS. 17A to 17Z. Figures 18A to 18D are the first
7 is a diagram showing equivalent metal-insulator-semiconductor circuits of the various logic gates shown in FIG. 7; FIG. FIG. 19 is a circuit diagram illustrating an equivalent metal-insulator-semiconductor circuit of a shift register cell used in the commutator of the random access memory array shift register device used in the embodiment of FIG. It is. FIG. 20 is a circuit diagram illustrating a metal-insulator-semiconductor driver circuit for the shift register cell of FIG. 19. Figure 21 is the first
FIG. 7 is a diagram illustrating a circuit equivalent to a programmable logic array (PLA) used in the embodiment of FIG. 7; Figures 22A-22T are flow charts illustrating programs stored in programmable read-only memory of an embodiment of a calculator device to provide desktop calculator functionality including floating point operations, input routines, and output routines; It is. FIG. 23 is a plan view of the packaged monolithic structure showing the terminal interconnections to the keyboard, display driver and power supply. 201...Program block, 202...
Control block, 203...Timing block, 204...Data block, 205...Output block, 208...Read-only memory, 20
9...Program counter, 190...Instruction register, 191...Control decoder, 192...Jump condition circuit, 195...Numeric and FLAG mask decoder, 196...Key input logic section, 20
6...Random access memory shift register and FLAG data storage array, 207...
Decimal arithmetic unit, 229...FLAG logic unit, 19
8...Segment output decoder, 197...Numeric scanner output.

Claims (1)

[Claims] 1. (a) An input device having a plurality of keys capable of generating input information and outputting the input information through output terminals smaller than the number of keys; program storage means for fixedly storing program instruction information for at least an input routine, an operation, and an output routine by a mask; a control means for receiving the program instruction information and generating control information; input means for reading the input information in response to control information generated based on program instruction information; and performing an arithmetic operation in response to control information generated based on program instruction information for the operation;
Arithmetic logic means for generating operation result information and output means for outputting operation result information in response to control information generated based on program instruction information for an output routine are integrated on a single semiconductor substrate, and each of the above (c) an electronic device comprising: a monolithic semiconductor device in which means are connected by internal connection lines so that each of the above information can be transmitted; and (c) an output device that operates upon receiving calculation result information from the output means of the semiconductor device. .