JPS62298163A - Manufacture of solid-state image sensor - Google Patents

Abstract

PURPOSE:To form an overflow drain and a barrier region very finely and highly accurately, by introducing first impurities in a substrate through a mask opening part, diffusing the impurities in the lateral direction by heat treatment, and introducing second impurities. CONSTITUTION:An ion implanting mask layer 10, which can resist heat treatment, is deposited and formed on one main surface of a P-type Si semiconductor substrate 1. Thereafter a photoresist layer 11 is applied and formed. After an opening part 12 is formed in the photoresist layer 11, an opening part 13 is formed in the layer 10, with the resist layer 11 as a mask. Then, with the layers 11 and 10 as masks, P-type impurities 100 are implanted. The layer 11 is removed, and a P-type region is diffused by heat treatment. With the layer 10 as a mask, N-type impurities 101 are implanted, and an N<+> type overflow drain 4 is formed. Then, the P-type region remaining on both sides is formed as an overflow barrier region 5.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of manufacturing a solid-state image sensor, and particularly to a method of manufacturing a blooming suppression mechanism in a solid-state image sensor.

[Conventional technology]

In a solid-state imaging device using a CCD (charge-coupled device) or the like, an overflow drain structure is required to flow excess charge exceeding the handling capacity of a light receiving section or a vertical shift register in order to suppress pluming. FIG. 2 is an example showing a cross-sectional view of the main part of a solid-state image sensing device having one of such structures. FIG. 2A is a cross-section including the light receiving part, and FIG. It shows. In Fig. 2, l is a P-type semiconductor substrate, 2 is a light receiving section, and 3 is a P-type semiconductor substrate.
is a vertical shift register, 4 is an overflow drain,
5 is an overflow barrier region, and 15 is a polysilicon gate electrode. As shown in FIG. 2, an overflow drain of the second conductivity type is formed on the semiconductor substrate 1 of the first conductivity type and is located close to the light receiving section 2 of the second conductivity type or the vertical shift register 3 and has a higher concentration than these regions. 4 is provided, and the light receiving section 2
or vertical shift register 3 and overflow drain 4
An overflow barrier region 5 whose impurity concentration is adjusted so that the potential is shallower than that of the light receiving section 2 or the vertical shift register 3 is provided between the light receiving section 2 and the vertical shift register 3.

In this solid-state image sensor, when excessive charge is generated due to strong incident light during light reception, which exceeds the handling capacity of the light receiving section 2 or the vertical shift register 3, this excess charge is flowed to the overflow drain 4 through the overflow barrier region 5, and plumping is suppressed. It will be done. This is N channel C
This will be explained by taking a CD frame transfer type image sensor as an example. The solid line A and the point yAB in FIG. 3 are potential distribution diagrams of the charge storage section and the barrier section of the channel section 6 during driving, respectively. The potential barrier 30 for the charge storage section of the barrier section is the potential barrier 3 for the charge storage section of the overflow barrier.
If it is set to be higher than 1, excess charges generated by strong incident light will flow over the overflow barrier and into the overflow drain before overflowing into the barrier portion, so that flooding will be suppressed. In addition, in Figure 3, 32
indicates the charge stored in the charge storage section.

Now, the conventional method of forming such an overflow drain 4 and overflow barrier region 5 is mainly as shown in FIG. 4A.
-C, after forming a silicon oxide film 40 on the surface of the semiconductor substrate 1 of the first conductivity type, this oxide film 40 is patterned to form an opening 41, and the opening 41 is opened using the oxide film 40 as a mask. A second conductivity type overflow drain 4 is formed on the substrate surface by diffusion or ion implantation through the silicon oxide film 41. Next, a silicon oxide film 42 is formed again, and an opening 43 larger than the opening 41 is formed therein. 42
Using this as a mask, diffusion or ion implantation is performed through the opening 43 to form overflow barrier regions 5 on both sides of the overflow drain 4.

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, the overflow drain and the overflow barrier region are not formed in the self-alignment line, and the masking process is required twice, so that the mask misalignment is caused as shown in FIG. 4C'. Due to this problem, it is difficult to form the overflow drain 4 and the overflow barrier region 5 in an ultra-fine manner, and furthermore, due to differences in the way uneven exposure and development occur during the two mask processes, it is difficult to form the overflow barrier region. This causes variations in the amount of charge handled by the light receiving section or the vertical shift register, and uneven sensitivity, making it difficult to manufacture a high-resolution solid-state image sensor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a solid-state imaging device that eliminates the above-mentioned conventional drawbacks and makes it possible to form an overflow drain and an overflow barrier region with ultrafine precision.

[Means for solving problems]

The gist of the invention is to form both the overflow drain and overflow barrier regions by the same mask process. That is, first, a first impurity that forms an overflow barrier region of the first conductivity type is introduced into the semiconductor substrate through the opening of the mask, and is laterally diffused by high-temperature heat treatment. A second impurity is then introduced into the overflow barrier region through an opening in the same mask to create a conductivity opposite to that of the overflow barrier region, thereby canceling out a portion of the first impurity in this region. forming an overflow drain having a second impurity concentration higher than the impurity concentration of the second impurity concentration; Thereafter, an impurity forming a second conductivity type semiconductor region such as a light receiving section or a vertical shift register adjacent to the overflow drain structure is introduced into both regions of the overflow drain and the overflow barrier ml region, thereby causing the overflow barrier region to overflow. The second conductivity type semiconductor region adjacent to the drain structure has a shallower potential than the overflow drain.

[Effect]

According to this manufacturing method, since the masks forming the overflow drain and the overflow barrier region are the same, the problem of mask misalignment caused by the conventional manufacturing method does not occur at all. This eliminates the need for a margin for mask alignment, and furthermore, the width of the overflow barrier area is determined by the thermal diffusion process, and is not affected by limitations due to the minimum microfabrication dimensions of the mask and uneven exposure and development during the mask process. , the dimensions of the overflow drain structure can be reduced with high precision, making it possible to manufacture a high-resolution solid-state image sensor.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing an N-channel CCD frame transfer type image sensor, which is an embodiment of the present invention, will be described in detail below with reference to the drawings.

FIG. 1 is a cross-sectional view showing the process steps for manufacturing an N-channel CCD frame transfer type image sensor.

First, a layer 10 of silicon oxide or silicon nitride that can serve as an ion implantation mask and can withstand heat treatment is deposited on the entire surface of a P-type silicon semiconductor substrate 1 (FIG. 1A).
Next, a photoresist layer 11 is formed by coating on this layer lo. Then, the photoresist layer 11 is exposed to light through a mask having a pattern corresponding to the overflow drain to be formed, and then developed to form an opening 12 corresponding to the overflow drain (FIG. 1B). Further, the layer 10 is etched using the photoresist layer 11 as an etching mask to form an opening 13 of the same size at a position corresponding to the opening 12. And this photoresist layer 11
P-type impurity 100 is ion-implanted through the openings 12 and 13 using JiIO and JiIO as a mask to form a P shadow region 14 whose width is defined by the opening 12 on the surface of the substrate 1 (FIG. 1C). Next, the photoresist layer 11 is removed and the P shadow area 14 is removed.
is laterally diffused to a predetermined size by heat treatment (first
Figure D). Next, using the layer 10 as a mask, N-type impurity 101 is ion-implanted through the opening 13 to form an N-shaped overflow drain 4 whose width is defined by the opening 13 in the center of the previously formed P shadow region 14. . Accordingly, the P shadow areas remaining on both sides are formed as overflow barrier areas 5 (FIG. 1E). After removing layer 10, N-type impurities 102 are introduced throughout the active region, thereby forming channel portions 6 in the regions between the overflow drain structures (FIG. 1F). The concentration of the N-type impurity 102 is defined by the characteristics of the channel portion 6.

The amount of diffusion of the P-type impurity 100 is determined by the amount of diffusion in the channel portion 6. The concentration of the P-type impurity 100 is determined by the dimensions of the overflow drain structure, etc., and the concentration of the P-type impurity 100 is controlled so that the overflow barrier region 5 has a shallower potential than the overflow drain and channel portion with respect to its diffusion amount and the concentration of the N-type impurity 102. Ru.

〔Effect of the invention〕

According to the present invention described above, the overflow drain structure provided between the elements to absorb excess charge caused by strong incident light on the light receiving part can be created with higher precision and finer details than conventional techniques, and blooming can be prevented. It is possible to obtain a high-sensitivity solid-state image pickup device by suppressing the unevenness of the photosensitive material while maintaining high density and low sensitivity unevenness, and by increasing the aperture ratio of the light-receiving section.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the process order showing an embodiment of the present invention, FIG. 2 is a main cross-sectional view of an example of a solid-state image sensor having an overflow drain structure applicable to the present invention, and FIG. 3 is a cross-sectional view of an example of the present invention. FIG. 4 is a potential distribution diagram for explaining the process. 1... Semiconductor substrate 4... Overflow drain 5... Overflow barrier region 6... Channel portion 10... Layer 11 of silicon oxide or silicon nitride, etc.
... Photoresist layers 12, 13... Openings 14... Yoshiyuki Iwasa, Patent Attorney, Patent Attorney for P Shadow Area Figure 1 Figure 2 q Figure 3

Claims (1)

[Claims] (1) A solid-state image sensor having an overflow drain structure as a blooming suppression mechanism, in which an overflow drain is provided close to a light receiving section or a vertical shift register, and an overflow barrier region is provided between the light receiving section or vertical shift register and the overflow drain. In the manufacturing method, a semiconductor region of the first conductivity type is formed on the semiconductor substrate through an opening in a layer that can be used as a mask for ion implantation formed on the semiconductor substrate, and then the semiconductor region is removed by high-temperature heat treatment. lateral diffusion of a second conductivity type semiconductor region through the opening and into the first conductivity type semiconductor region.
An overflow drain of a conductivity type is formed, and an impurity is commonly introduced into the first conductivity type semiconductor region and the second conductivity type overflow drain to form a second conductivity type semiconductor region adjacent to these regions. A method for manufacturing a solid-state imaging device, comprising controlling the potential of an overflow barrier region made of a semiconductor region to form an overflow drain structure.