JPS62296252A - Buffer storage control system - Google Patents

Abstract

PURPOSE:To reduce the capacity (in the lateral direction) of storage elements that realize a directory BAA by limiting the number of bits at an absolute address registered in the directory BAA to the number of bits at an accessible address, which are decided by the physical limit of a main storage address MS. CONSTITUTION:All 31 bits apart from the high order three bits are stored at the absolute address in the BAA 107. The output of each row for the column concerned in the BAA 107 is inputted to a comparator 108, and compared with bits corresponding to the absolute address in an address conversion buffer TLB, which are transmitted from a gate 105. The output compared by each comparator 108 is inputted to an encoder 109, and a row in a buffer storage BS 110 registering block data is entry-encoded. Absolute addresses that are slightly below the upper limit of the MS capacity are transferred to a BS. As for any more address, address exception is detected.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention provides a buffer storage (BS) that stores a copy of data on a main memory (MS), and This relates to an information processing device that has a directory (BAA) in which the main memory address (MS address) of the data stored in the data is registered.
The present invention relates to a buffer storage control method that reduces the number of bits in the data.

[Conventional technology]

A conventional buffer storage control system will be explained with reference to FIG. In FIG. 2, it is assumed that the BS uses a set associative method. An example of this type of computer is HITACM-180°M-200H.

In FIG. 2, 201 is an address (logical address) given by the program, and consists of 24 bits (numbered 08-31 starting from the leftmost bit).
Can access 16MB of logical (virtual) space. 202
is from the logical address to the address translation buffer ("l'L+
3) This is a control circuit that obtains the en1 to rear address of 203. The TLB 203 is a dynamic address translation mechanism (which calculates the address for relocating a page (usually 4 bytes), which is the unit of replacement from the virtual space to the real storage MS, onto the MS.
DAT), and each entry stores a logical address (08-15) and a one-to-one corresponding absolute address (08-19) (this is called a page address). . The logical address part of TLB 203 is input to comparator 2.4 and compared with the logical address of 201. The output of comparator 204 is TLB2
It is input to the output of 03 and gate 205, and gates the absolute address part (08-19) of TLB 203.

On the other hand, r3s209 has multiple columns (1 in the example in Figure 2).
28), and each column is divided into multiple rows (8 in the example of FIG. 2). Correspondingly, the MS is also divided into the same number of columns. That is.

In each row (called a block) of a column on the B5209, data of an arbitrary block (block data) of the corresponding column on the MS is stored. BAA206
is also divided into multiple columns and multiple rows similar to B5209, and when data (block data) is transferred from a certain column of MS to the same column of B5209, the BS column address ( 2
The upper bits (08-19) of 0-26) are recorded 42 in the entry accessed in the relevant column and row of B5209 where the block data is written.

Among the logical addresses 201, the in-page address (20-
31) remains unchanged after address translation and prefix translation, and the output of each row of 6BAA 206, which is also an absolute address, is input to each comparator 207 to be compared with the gated output of the absolute address of TLB 203. .

The output of each comparator 207 is input to the row encoder 208 and indicates the row of B5209 in which block data is registered.If the corresponding address is not registered in any row of the BAA 206, no row will be accessed. , a block transfer request to the MS is issued.

[Problem that the invention seeks to solve]

The above conventional technology does not take into account the number of bits of the absolute address of the MS registered in the BAA, and as the real space expands and the absolute address accessed by the SCP (system control program) becomes larger, There is a problem in that it is necessary to increase the number of bits of the absolute address registered within the address space. For example, in the configuration shown in Figure 2, if the logical address is expanded from 24 bits to 31 bits to cope with the expansion of the user area, and the virtual space is made 2 GB, and the real address is also 31 bits, then the MS will also be 2 GB.
Although it becomes possible to access up to B, it becomes necessary to add 7 bits to the absolute address <tU in BAA. but,
The storage elements required for BAA are often bipolar high-speed memories.

4JX, the speed of expansion of the integrated circuit is faster than that of MOS. Therefore, it is extremely difficult to increase the capacity by 7 bins or more due to physical implementation limitations.

An object of the present invention is to provide a buffer storage control method that can reduce the increase in the number of bits of absolute addresses registered in BAA even if the real space is expanded.

[Means for solving problems]

In the present invention, the real address is m bits, and a maximum of 2"-1
Focusing on the fact that even if the ti area becomes accessible, the capacity of the memory element that can actually be mounted on N13 is less than that, and the maximum address that can be mounted on the MS is accessible with an n-bit absolute address, and m) In the case of n, means is provided for detecting that all of the upper m-n bits of the absolute address m at the time of BS access are +10 +1.

[For production]

When registering to BAA, the lower n bits are recorded only when the upper m - n bits are all "0", and the comparison between the address in BAA and the BS access address is performed using the upper m - n bits.
This is performed when the bits are all 0, and only if the lower n bits compare and match, it is determined that the specified data is stored in the BS.If the upper m - n bits are not all N OI+, an address exception or issue a direct fetch request to the MS and detect an address exception within the MS.

〔Example〕

FIG. 1 shows the conceptual structure of the system of the present invention in comparison with FIG. 2. 101 indicates a logical address expanded to 31 bits. Correspondingly, T I, B I O
The absolute address stored in 2 is also 19 bits (01-19
) is extended to The logical address field of the corresponding entry in TLB 102 and the logical address of 101 are compared by comparator 103 as in the case of FIG. On the other hand, TLB10
The upper bits of the absolute address part of the corresponding entry in No. 2 (the first
In the example shown in the figure, the output of 3 bits (01-03) is input to the non-zero detector 104 that determines whether all bits are 0, and TL
If the upper bits of the absolute address that existed in the corresponding entry in 02 are not all 0, the address exception detection circuit 10
6, an address exception detection signal is sent. Gate 105 is matched by comparator 103 and non-zero detector 10
4 are all zeros, the lower bits (04 to 19 in the example of FIG. 1) of the absolute address part of the corresponding entry in TLB 102 are gated.

In the BAA107, among the 31 bits of the absolute address,
Bits excluding the upper 3 bits (i.e., in the example in Figure 1, the maximum installed capacity of the MS is 256 MB, so the bits higher than the 28 bits required to access the maximum absolute address) Register. BAA107
The output of each row of the appropriate column is input to comparator 108 and compared with the corresponding bit of the absolute address in TL[3 sent out from gate 105. The comparison output of each comparator 108 is input to the encoder 109, and the row of B5ll0 whose block data is 37.8 is entry coded. In the case of Figure 2, B5ll0 and BAA107
The row of is divided into four classes (0 to 3), and decoder "1" decodes bits 18-19 of logical address 101 to indicate the corresponding class.

With the configuration of FIG. 1, the absolute address space up to the upper limit of the MS capacity is transferred into the BS, and address exceptions are detected for absolute addresses beyond that.

Next, embodiments of the present invention will be described in detail.

FIG. 3 shows an overall block diagram of the information processing device. M.S.
301 is a data bus 305. storage controller (via
(hereinafter abbreviated as SC) 302.

The 5C 302 is connected to a buffer storage device (hereinafter abbreviated as BU) 303 and an arithmetic processing unit (hereinafter abbreviated as EU) 304 via a data bus 307 . Further, the BU 303 is also connected to Eu2O3 via a data bus 308. BU303 is TLB403, BAA404. B542
It is equipped with 2.

The output of six logical address registers (hereinafter abbreviated as LAR) 401, which shows the details of the BU 303 in FIG.
3, and a buffer address array (BAA) 404. The output of the LARD 402 is divided into segment index (SX), page index (px), and byte index (B The other input of the TAA 406 has a register (STO) 40 that stores the segment table origin.
9. A register that stores the segment table length (STL
) 410, and read from BS, data register (T
The output of the shifter 4" which shifts the output of the BR) 414 is connected. The output of the TAA 406 is connected to the prefix conversion logic unit (PFX) 407. The output of the prefix address register (PXR) 408 is also connected to the PF
Connected to X407. The output of PFX407 is LA
R401 and absolute address storage register O (PARO)
412.

When the logical address sent from Eu2O3 is set in the LAR 401, the TLB 403 is accessed by the page address section (sx, px field section) of the LAR 401, and the comparator 417 connected to the TLB 403 reads the corresponding logical address. compared to bits. If they match, a launch (INTLB) indicating that an absolute address corresponding to the logical address exists in the TLB 403.
) 418 is set. If INTL841B is not set, DAT is activated and 5TO409, S
TAA40 using the values of the X field and PX field
9, the addition is performed and the real address is obtained. A detailed explanation of the operation of D A'r will be omitted since it deviates from the purpose of the present invention.

At the end of the DAT, the output of the TAA 406 is a real address, and the prefix conversion logic unit (PFX) 40
7 is input. PARO41 determined by PFX407
Of the absolute addresses set to 2, the page address part is the absolute address delay register (PARO).
Once set to 419, 'I' L B 403
is written to the absolute address field (P) 416 of the corresponding entry. At this time, the logical address before address conversion is also written corresponding to the logical address part (L) 415 in the same column. As a result, since the logical address exists in the TLB (hereinafter abbreviated as INTLB), the INTLB latch 418 is set. At this time, the absolute address part (P)
When the non-zero detector (NZD) 420 connected to the output of the upper bits of 416 (0l-03 in the example) detects that all bits are not '0', the output of the gate 421 becomes active and the An address exception signal is sent to the absolute address register 1 (PARl) 4 connected to the absolute address section (P) 416.
13, is set in the LARD 419, and sent to the 5C 302 as the address of the data transfer request.

In parallel with the access to TLB 416, BAA 4
A certain column of 04 is accessed and its multiple loads are read simultaneously. With this, the number of bits of the absolute address stored in the BAA 404 can be reduced to M by deleting the upper bits.
BAA404, which is the number of bits (04-20 in the example) required to access the maximum address on the implementation of S.
The absolute address read from becomes one input of comparator 425. The other input of the comparator 425 receives the absolute address (P) 416 of the TLB 403 or PARD to which the absolute address after DAT is set via the selector.
419 output. When INTLB, the former is selected; otherwise, the latter is selected, and the comparator 42
5 is compared with the output of BAA404.

[3S422 is accessed with an address including the logical address (18-19), so blocks in the same MS may be set to different columns of a row in the BS. Therefore, B5422 and BAA404 are divided into four classes (CLO-19) determined by logical addresses (18-19).
CL3), and each row is composed of four classes as shown in FIG.

Each output of the comparator 425 is connected to a circuit (hereinafter referred to as lNB5) that determines whether or not the address of LAR 401 exists in BAA.
(abbreviated as DETECT) 423. As mentioned above, in order to detect the double A1 record to B5422 of the same logical address, the logical address (18-19) is INB.
DETEC: Input to T423. lNB5 DE
The TECT 423 determines whether it is lNB5 based on the output of the comparator 425 and the class number (uniquely determined by 18-19). In the case of lNB5, the comparison was consistent (hereinafter referred to as H
(ITL, abbreviated as) Register the number (POW) 4
Set it to 2G. The output of the ROW 426 is connected as a select signal to the selector 427 to which each row output of the B5422 is connected. If it is not lNB5 (N I
BS), latch 425 is set.

In the conventional technology, in the case of NlB5, data (called a block) containing the double word to be accessed is unconditionally
A transfer request (referred to as a block transfer) from the MS 201 to the BU 303 was issued to the 5C 302, but in this embodiment, the output of the NlB 5425 is gated by the gate 424 using the output of the NZD 420. That is, if the NZD 420 detects non-zero, no block transfer request is issued. In this case, if I N T L B, an address exception is detected. Therefore, the part of the absolute address that exceeds the upper limit of the mounting capacity of MS301 becomes an address exception, and B542
The part that is not registered in 2 and does not exceed the upper limit is NlB5
Even if , the block transfer is started and the block is written to B5422 because it is not inhibited by gate 424, and BA
An absolute address is registered in the corresponding column of A.

〔Effect of the invention〕

According to the present invention, the number of bits of an absolute address registered in the BAA is not determined by the real address space defined by the architecture.

Since the number of accessible address bits can be limited to the number of bits of an accessible address determined by the physical limitations of the MS, the capacity of the storage element that realizes BAA! (lateral capacity) can be reduced compared to the conventional method. Furthermore, as the number of bits of the BAA is reduced, the amount of hardware required for a comparator that compares the output of the BAA and the absolute address of the TLB can be eliminated.

4.1! ! 1 is a diagram showing the conceptual configuration of the present invention, FIG. 2 is a diagram illustrating the prior art, and FIG. 3 is an overall block diagram of an information processing device targeted by the present invention. FIG. 4 is a detailed diagram of one embodiment of the buffer storage '4 device in FIG.

102.403...Address translation buffer (TLB)
, 107,404...Buffer address array (
BAA), “0,422...Buffer storage (BS
), 104,420...non-zero detector, 106,
421, 424...MS data transfer request circuit.

Figure 1 Figure 2

Claims (1)

[Claims] (1) In an information processing device that has a buffer memory that stores a copy of data on the main memory and a directory that registers the main memory address of the data stored in the buffer memory, the physical access address ( Of the m bits indicating the absolute address, the upper m-n bits are all 0, excluding the n bits (n<m) necessary to access the maximum absolute address determined by the physical implementation restrictions of the main memory. 1. A buffer storage control system characterized in that a means for detecting `` is provided, and when m−n bits are all 0, a directory is registered and referenced using the lower n bits.