JPS62294322A - Pulse width identification circuit - Google Patents

Abstract

PURPOSE:To surely output an output signal for identifying a pulse width by directly applying an input pulse signal to a 2nd delay circuit so as to hold the output of a 2nd output signal while the input pulse exists. CONSTITUTION:A 1st delay circuit 1 applies pulse width identification of an input pulse signal, the 1st output signal outputted from a 1st delay circuit 1 is inputted to a 2nd delay circuit 12, from which a prescribed level of the output signal is outputted and which control a control circuit 18, thereby supplying the input pulse signal to the 2nd delay circuit 12. Thus, the output signal of the prescribed level is being outputted while the input pulse signal whose pulse interval is a prescribed value or below is inputted.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (a) Field of Industrial Application The present invention relates to a pulse width identification circuit for identifying the pulse width of a pulse signal.

(B) Conventional technology A circuit is connected to a line through which two or more types of pulse signals are transmitted, a pulse signal having a desired pulse width is identified, and a desired circuit is controlled using the pulse signal having the desired pulse width. For example, a pulse width identification circuit that allows
As described in Japanese Patent No. 473, it is used to distinguish between a telephone dial impulse signal and a ringing signal, and to activate a desired device or circuit using only the ringing signal. A pulse width discrimination circuit that operates in this manner is generally constructed of complex gate circuits. More recently, I
With the development of C, pulse width discrimination circuits using ICs composed of flip-flop circuits have also appeared.

(c) Problems to be solved by the invention By the way, the pulse width identification circuit as described in -1- generally identifies the presence or absence of a pulse having a pulse width of a certain time or more. When the identification is confirmed, the identification signal that has been set in advance is output. In such a pulse width identification circuit, when pulses having a desired pulse width are continuously input, an identification signal is continuously outputted to a desired control circuit in response to the pulses. If noise generated from the contacts of each gate circuit is superimposed between the signals, there is a risk that the desired control circuit may malfunction due to the continuous identification signals that are output. Another problem is that in order to solve the above problems, the number of contacts in each gate circuit must be reduced, and in order to minimize noise generation, it is necessary to use expensive gate circuits. was occurring. In order to solve this problem, the present invention provides a pulse width identification circuit that is inexpensive and that performs pulse width identification reliably without taking noise countermeasures.

(d) Means for Solving the Problems The pulse width identification circuit of the present invention identifies an input pulse signal having a pulse width equal to or greater than the identification reference pulse width, performs a delay operation for a certain period of time, and outputs an identification signal. a second delay circuit that is activated by the identification signal of the first delay circuit, holds the output signal by an input pulse signal whose pulse width is equal to or less than a certain value, and performs a delay operation upon recovery; and the second delay circuit. The output signal output from the circuit causes the second pulse of the input pulse signal to be
It consists of a control circuit that controls input to the delay circuit.

(E) Function The present invention first identifies the pulse width of a high-power pulse signal in a first delay circuit, and then
By inputting the output signal to the second delay circuit, causing the second delay circuit to output an output signal of a constant level, and controlling the control circuit to input the input pulse signal to the second delay circuit, a constant level of the output signal can be achieved. The output signal continues to be output while a high-power pulse signal with a pulse interval of less than a certain value is input.

(v) Embodiment An embodiment of the pulse width discrimination circuit of the present invention is shown in FIGS. 1 and 2.
This will be explained using figures. (1) includes a first transistor (2) that performs on/off operation depending on the input signal in a first delay circuit that identifies the pulse width of an input pulse signal and outputs a first output signal; transistor(
The charging time T until the first capacitor (4) has a constant voltage is comprised of the first capacitor (4) and the first resistor (5), which perform a charging operation at the same time as the capacitor (2) becomes non-conductive.
, a first charging/discharging circuit (3) for identifying whether the pulse width of the input signal is longer or shorter, and the first capacitor (
4), one side is connected to a connection point C where a discharging diode (6) for instantaneously discharging the voltage charged in the first capacitor (4) and the collector of the first transistor (2) are connected. , and the other input terminal is grounded to form a NOR circuit (7).
and a second logic circuit (8) constituting a NOR circuit whose inputs are the output of the first logic circuit (7) and the input pulse signal.
), a first inverter (9) that inverts and outputs the high-power pulse signal applied to the input terminal S, and the first
A third circuit that detects the output of the inverter (9) and the output of the second logic circuit (8) and outputs a signal as the first output signal.
It is composed of a logic circuit (10). (11) is a first diode for preventing backflow to the output section of the third logic circuit (10); a second delay circuit that outputs a second output signal in response to a third logic circuit (10
) A second transistor (13) that performs on/off operations according to the output of the second transistor (13), a second resistor (15) and a second capacitor ( 16) and the second
It is comprised of a charge/discharge circuit (14) and a second inverter (17) that inverts and outputs the output signal of the second charge/discharge circuit (14). (tsubo) is a control circuit that controls the input signal to the second delay circuit (L8) in accordance with the output of the second delay circuit (L8), and the second diode (19) and the third diode
It is composed of a diode (20). The operation of the pulse width identification circuit configured as described above will be explained in detail below.

First, when a signal of r L J potential is input to the above-mentioned pulse width discrimination circuit, the first transistor (2) becomes conductive, and the power supply voltage V cc appears at point C, and the first logic circuit (7) Input rH and potential to the input terminal. Therefore, the first logic circuit (7tf'HJ potential and ground rL,
potential under NOR conditions - [at the point where r L ,
Outputs potential. Then, the second logic circuit (8) outputs the 1HJ potential to point B by inputting the r L and potential of the point and the signals of r L and potential. As a result, the first intensor (4) provided between point C and point B
are charged to equalize the voltages appearing on them. Therefore, when an input signal of 'L' is input, the point C holds the 'I(' potential, and the point C holds the r L potential. Therefore, the third logic circuit (10) always has the 'L' level input signal. L” potential and r
The output of the first potential inverter (9) is added, and the third logic circuit inverts the "L" potential input signal to the second potential inverter (9) through the first diode (11). It is output to the base of transistor (13). Therefore, the second transistor (13) becomes non-conductive, and the second charging/discharging circuit (14) supplies the power supply voltage Vcc from the power supply voltage supply path to the second capacitor (16) via the second resistor (15). Start charging. After a certain period of time T has elapsed due to the charging, a potential rH appears at point G. Yo-(r L , the potential input signal is for a certain period of time T2
If the above continues, the output of the second charging/discharging circuit (14) will be at rH potential, and an "L" potential will be output to point H via the second inverter (17). Also, - fixed time T.

The output of the second charging/discharging circuit (14) is “L” until the
, the potential is output to point H through the second inverter (17). On the other hand, since point J applies a reverse current to the third diode (20) of the control circuit (18) when the potential of point H is rH, the input signal r L ,
A potential appears and the point H is r 1. , when the potential is rL at point J regardless of the third diode (20)
”A potential appears. Therefore, when the input signal of "T7. potential is input, the point J always has the potential r L , and the 21st run sister (
No operating voltage is supplied to the base of 13).

Next, when a signal of H1 potential is input, No. 11 to Range Stark 2) become non-conductive, and the voltage of power supply '1' is applied to point C.
CC loses one power. Therefore, the first logic circuit (7
〉, the potential increases by 1 force r L from point C. Therefore-
7= The first logic circuit (7) processes the r L potential added from point C and the "L" potential due to grounding under the NOR condition and outputs it as r H, potential at the point. Since the circuit (8) receives a human input signal of 'HJ potential, N
In the OR condition, even if either the "L" or rH potential is applied to the other, the "L" potential is output to point B, so both points C have the potential rL.

Thereby, the first capacitor (4) is connected to the first resistor (5)
via the power supply voltage V. 0 starts, but point C is held at "L" potential until a certain time TI (charging time of the first capacitor (4)) has elapsed. Therefore, for a certain period of time T
When the input signal has a potential rH that does not reach 1, the point C becomes r
Only the "L" potential is applied, and only the "H" potential appears at the point through the first logic circuit (7). Therefore, the third logic circuit (10) processes the H4 potential of the dot and the rL potential signal inputted via the first inverter (9) that inverts the rH potential input signal under NOR conditions. A signal with a potential of rL is output to the base of the second transistor (13) via the first diode (11).Therefore, since the second transistor (13) is always in a non-conducting state, the second transistor (13) is in a non-conductive state. The 2:1 inverter (16) of the discharge circuit (14) is constantly charging the power supply voltage VCC through the second resistor (15).As a result, "H9 potential appears at point G, and the second inverter (1
7) Outputs "L" potential to point (1). Also, when the input signal is at the "H" potential for a certain period of time T1 or more, the first Z
The first charger (4) is charged via the first resistor (5) (7) and has a charging voltage of cC/2 or more, so it is charged for a certain period of time T,
At the later point C, 'Hrtlt' appears. As a result, the output of the first logic circuit (7) becomes rL, a potential, and the third logic circuit (10) applies a 'H, potential to the base of the second transistor (13) via the first diode (11).
7. The second transistor (13) is made conductive to discharge the charge stored in the second resistor (16) through the second resistor (15) of the second charge/discharge circuit (14). instantaneously (make point G 1■7" potential., 1
At point G, the potential is the second inverter〈17
), and a potential 'H' appears at point 1. The input signal appears as it is at point J in the control circuit (1B).Therefore, the input signal appearing at point J passes through the second diode (19) and then the second transistor (1B).
13) and the output of the third logic circuit (10) is r L .

If the point H is at "H" potential even when the potential is high, the second transistor (13) performs on/off operations in response to the input signal input via the second diode (19). and a second capacitor (1) of the second charging/discharging circuit (b).
6), when the second transistor (13) is turned off, the second transistor (13) is charged again via the second resistor (15), but unless the charging time is longer than the fixed time T, the point G is at the "L" potential. 2
It is inverted by an inverter (17) and a potential rH is applied to point H as an output.

Therefore, in the pulse width discrimination circuit of the present invention that performs the above operation, to(ta<'r+) and 1 as shown in FIG.
．． A signal having a pulse width of (1□>TI) is input.

First, when a signal with a pulse width of to is input, the first delay circuit (
The second logic circuit (8) of 1) is shown in FIG. 2A as shown in FIG. 2B.
The inverted signal is output to point B. At that time, the first transistor (2) also turns on and off depending on the input signal,
Controls the first charging/discharging circuit (good). As a result, the first
The charging/discharging circuit (β) is the non-conducting time of the first transistor (2), so-called t when the input signal is at rH level.
It is controlled to charge during the 0 period and to discharge instantaneously during the conduction period, and an output as shown in FIG. 2C appears at point C. The signal appearing at point C is then input to the first logic circuit (7) and processed under NOR conditions together with the value of the "L" potential due to grounding, resulting in an output as shown in the second diagram. As a result, the signals are applied to the input terminals of the second logic circuit (8) and the input terminals of the third logic circuit (10) connected to the dot, but the second logic circuit (8) remains unchanged as shown in Figure 2B. output to point B. On the other hand, the third logic circuit (10) processes the signal that appears at the dot together with the signal inputted through the first inverter (9) that inverts the input signal under NOR conditions, as shown in FIG. 2F. A signal of "L" potential indicating that the pulse width of the input signal is T1 or less is always applied to the base of the second transistor (13) of the second delay circuit (12) via the first diode (11). . As a result, the second transistor (13) becomes non-conductive due to the application of the potential r L . Therefore, the second charge/discharge circuit (
14), the power supply voltage V cc is connected to the second resistor (15
), the charging operation at the second capacitor (16) continues as long as there is an input signal with a pulse width of T or less (having a pulse width of to), so the charging voltage of the second capacitor (16) is V ec /2 or more, and a signal of rH and potential appears at point G as shown in Fig. 2G. Therefore, point G is T,
When a signal with the following pulse width is input, the rH potential is held, so a signal with the potential "L" is output to point H via the second inverter (17).Therefore, the control The third diode (20) of the circuit (18) biases the input signal input to the base of the second transistor (13) via the second diode (19) to maintain the non-conducting state of the second transistor (13). Therefore, the output to point H does not change, and a signal of "L" potential is always applied to point H.

Next, when a signal with a pulse width of tl is input, the second logic circuit (8) of the first delay circuit (1) outputs a signal obtained by inverting the signal shown in FIG. 2A as shown in FIG. 2B. Output to B. At that time, the first transistor (2) also turns on in response to the input signal.
It performs an off operation and controls the first charging/discharging circuit (3). First, when an input signal of r H and potential is input to the first transistor (2), the first transistor (2)
becomes non-conductive and point C becomes "L" potential. As a result, the first capacitor (4) of the first charging/discharging circuit (3)
Charging is started via the resistor (5). Since the charging operation at this time is performed for a time corresponding to the pulse width t1 of the input signal, the charging voltage of the first capacitor (4) is Vcc/
2 or more, and the potential of point C is set to rH from the "L" potential.

Then, at the same time that the input signal changes from rH, the potential to rL, the first transistor (4) becomes conductive, and in order to bring the point C to rH, the first capacitor (4)
) is controlled to allow instantaneous discharge via the discharging diode (6), and an output as shown in FIG. 2C appears at point C. The signal appearing at point C is then input to the first logic circuit (7).

In the first logic circuit (7), the first transistor (
When 2) is conductive, the "H" potential of point C is manually applied, and a "L" potential signal is output to the point, and when it is not conductive, the r of point C is
L, potential is manually input, rH, potential signal is output to the point. Further, when there is no conduction, the first capacitor (4) gradually charges through the first resistor (5), and the charging voltage becomes v c
When c / 2 becomes 1-, point C becomes r L , and r from the potential
The first logic circuit (7) changes to the "H" potential (charges for a period of T or longer) and outputs the "L" potential. (Second
Figure D) The second logic circuit (8
) and the input terminal of the third logic circuit (10), respectively, but the second logic circuit (8) remains unchanged as shown in Figure 2B.
Outputs point B as follows. On the other hand, the third logic circuit (10
) converts the signal that appears at the dot along with the signal input via the first inverter (9) that inverts the input signal.
Processing was performed under the OR condition, and only when the output of the first inverter (9) was at "L" potential and the signal appearing at the point was at r L J potential, it was revealed that the pulse width of the input signal was T+ or more ( A signal as shown in FIG. 2F having a pulse width of tl-T) is applied to the base of the second transistor (13) of the second delay circuit (ear) via the first guide (11). As a result, when a signal of LJ potential is applied, the second transistor (13) is in a non-conducting state (t
When a signal with a pulse width of l-'r) is applied, the second transistor (13) becomes conductive for a period of (tl-'r). Further, when the second transistor (13) is non-conductive, the second capacitor (1) of the second charge/discharge circuit (14)
6) is transferred to the second transistor (13).
) becomes conductive, and at the same time it is discharged through the second transistor <13), the point G has a potential of r L from the potential of r H,
A potential rH is output to point H via the second inverter (17). As a result, the input signal that was biased through the third diode (20) of the control circuit <18) is no longer biased, and the input signal is applied to the base of the second transistor (13) through the second diode-IF (19). do. On the other hand, in the second charging/discharging circuit (↓4), the same point G, where the signal with the pulse width of (t l - Tl,' makes the second transistor (13) conductive, is set to "L" potential, but ( t 1
- When the pulse width signal of (TI) disappears and the second transistor (13) becomes non-conductive, the second capacitor (16)
starts charging the power supply VCC through the second resistor (Dan), but the second capacitor (16) is charged and the point G is
H, a certain period of time T to reach the potential.

, the third logic circuit (
10) is the output of (t+'r) period, or the second
When an input signal (irrespective of pulse width) is applied via the diode (19), the second transistor (13)
becomes conductive and discharges the charging voltage of the second capacitor (16), so point G remains at rLJ potential and point H via the second inverter (17) also maintains rH potential. There is. And the second transistor (13)
Neither the pulse of period (tt'r) or the input signal is applied to the base of T for a certain period T, and the second capacitor (16) charges more than vcc/2 through the second resistor (15). When this is done, a potential rH appears at point G.

Therefore, the second inverter (17) outputs the r L J potential to point H. As a result, the third diode (20) of the control circuit j18) becomes biasable, and the input signal that was being input to the 21st run sister (13) via the second diode (19) is no longer applied, and the pulse width T, returns to the state before identifying the above input signals. Therefore, the pulse width identification circuit of the present invention can detect the set pulse width T.

When the above signals are input, the identification signal is reliably outputted, and after identification of a signal with a pulse width of 11 or more, regardless of the pulse width, if the input signal is within the T2 period, the identification signal is held and output. If it is not during the T3 period, the holding state is canceled after the T8 period ends, and the pulse width T returns to the state before the following signals were input.

(G) Effects of the Invention In the pulse width identification circuit of the present invention, the first delay circuit identifies a signal having the pulse width of the identification standard and outputs the first output signal, and the first output signal causes the second delay circuit to A controlled second output signal is output to control the control circuit so that the input pulse signal directly precedes the second delay circuit, and the output of the second output signal is held while the input pulse signal is present. By doing this, by once identifying a signal that has the pulse width of the identification standard, even if there is a signal that contains noise, it is possible to output a reliable pulse width identification output signal without causing malfunction due to that signal. Ta. Furthermore, since the circuit configuration is simple, it is inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG.
It is a waveform diagram of each part in a figure. Explanation of main drawing numbers (↓)...First delay circuit, (2)...First transistor, (tsubo)...Second delay circuit, (13)...
・Second transistor, (tsubo)...control circuit, (
20)...Third diode.

Claims (1)

[Claims] (1) In a pulse width identification circuit that identifies pulses with a desired bandwidth and outputs an identification signal, the input pulse signal having a pulse width equal to or greater than the identification standard is identified, a delay operation is performed for a certain period of time, and an identification signal is output. a first delay circuit that outputs
a second delay circuit that is activated by an identification signal of the delay circuit, holds the output signal by an input pulse signal having an interpulse width below a certain value, and performs a delay operation upon recovery; and an output output from the second delay circuit. A pulse width identification circuit comprising a control circuit that controls input of an input pulse signal to a second delay circuit according to a signal.