JPS6229369A - Picture binarization circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by providing a feedback control means and a comparator comparing the output signal of an amplifier with a video analog signal and outputting a binary signal. CONSTITUTION:When the analog video signal is inputted to a peak detection/ inverting circuit 11, the white peak level of the signal is detected and its inverting value is fed to an inverting input terminal of an amplifier 14 via a resistor r0. The amplifier 14 gives an output in response to a combined resistance comprising resistors not short-circuited by an analog switch 13 among resistors r1-rm+1 and a paralle resistor rf. That is, the output of the amplifier 14 is decided by the ratio of the combined resistance to the resistance of the resistor r0 and the output signal becomes the slice level of a comparator 15. Since the feedback changes with a pattern from a pattern generator 12, the output signal of the amplifier 14 is equal to the slice level of a pattern at each ocassion. Thus, the circuit constitution is simplified.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an image binarization circuit.

[Prior Art] Dithering is known as a method for reproducing halftones in facsimile machines, copying machines, etc., and there are image reading devices that use this dithering method.

In the second image reading device, a predetermined image league reads a predetermined image, outputs an analog video signal, and converts the analog video signal into a binary signal according to the dither method described above. The circuit that performs this conversion is
Conventionally, a circuit shown in FIG. 5 has been used.

That is, first, the peak level of the analog video signal (the level of the signal corresponding to the whitest part of the image) is
A large number of resistors R1, R2,...

Divide by RN+1 and set approximately the same number of slice levels as the number of these resistors. Then, each slice level and the analog video signal are each inputted into a comparator C1.
,C2,..., By comparing with CN,
It outputs multistage digital signals.

These multi-stage digital signals are input to the digital multiplexer 3, and a binary signal is obtained from the digital multiplexer 3 according to the selection signal of the pattern generator 12. A predetermined number of these binary signals are grouped together to reproduce halftones. This is halftone reproduction using the dither method.

Incidentally, the human sense of density difference has high density resolution at low density levels (bright levels), and photoelectric conversion elements have linearity. Therefore, although the photoelectric conversion element faithfully converts the density, it has distortion, so correction is required to reduce changes in the slice level, especially at low density levels. R1, R2, etc. in Figure 5
RN is given weight.

However, according to the above conventional example, the more the number of gradations, the more resistors that set the slice level.
Another problem is that the number of comparators increases. Therefore, as the number of parts increases, problems arise such as increased cost and increased complexity of the circuit.

[Object of the Invention] The present invention has been made by focusing on the problems of the conventional example described above, and provides an image binarization circuit that can simplify the circuit configuration in an image binarization circuit that reproduces halftones based on the dither method. The purpose is to provide a binarization circuit.

[Embodiments of the invention] FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The peak detection/inversion circuit 11 is a circuit that detects the peak value of an analog video signal output when an image league (not shown) reads a predetermined image, inverts the value, and holds the inversion result.

The pattern generator 12 generates a dither pattern in the dither method.

The analog switch 13 has a plurality of switches, these switches are turned on and off according to the digital signal from the pattern generator 12, and are connected in series with resistors rl, r2゜... . , rm are connected in parallel with each other.

Further, the resistance rf is the resistance rl, r2 .・・・・・・、r
m are connected in parallel with a series circuit connected in series.

The amplifier 14 amplifies the output signal of the peak detection/inversion circuit 11 according to the feedback amount, and the feedback amount is the combined resistance value of the resistors r1 to rm and the resistor rf, and the value of the resistor rO. It is determined according to the following.

The comparator 15 outputs a binary signal by comparing the output signal of the amplifier 14 and the video analog signal.

In addition, the pattern generator 12 and analog switch 1
3 constitutes a feedback control means that controls the amount of feedback according to the pattern.

Next, the operation of the above embodiment will be explained.

First, an analog video signal is detected by the peak detection-inverting circuit 1
1, the white peak value in that signal is detected and its inverted value is applied to the inverting input terminal of amplifier 14 via resistor ro.

The amplifier 14 amplifies a signal corresponding to the inverted value of the peak value of the analog video signal according to the amount of feedback. That is, the amplifier 14 has resistances r1 to r m +1
Output is performed according to the combined resistance value of the resistors that are not short-circuited by the analog switch 13 and the parallel resistor rf. Specifically, the output value of the amplifier 14 is determined by the ratio of the combined resistance value and the resistance value of the resistor ro, and the value of this output signal becomes the slice level of the comparator 15.

The amount of feedback changes according to the current pattern in the pattern generator 12, and therefore the output signal of the amplifier 14 is the same as the slice level of the pattern at that time.

FIG. 2 is a characteristic diagram showing the density of an input gray scale of 16 gradations. In the "white area" (lower left part), the slope is gentle. In addition, in the figure, the upper right part is the "black area".

The output level of the photoelectric conversion element when reading the gray scale shown in FIG. 2 has the characteristics shown in FIG. 3. In other words, the amount of change in the output level in the "white area" (upper right part of Figure 3) and the "black area" (lower left part of Figure 3) is smaller than that in the center (gray area). If the output signal of the amplifier 14 is not corrected, a "white area"
The density resolution decreases in the "black area" and the "black area".

In the above embodiment, since the resistor rf is provided in parallel with the series circuit, the above correction can be performed. Here are the results of this correction.

This is shown in FIG. FIG. 4 is a diagram showing the output characteristics of the amplifier 14 in the above embodiment.

As shown in FIG. 4, in the "white region" (the right part of FIG. 4), there is little change in the slice level of the comparator 15. In other words, in the "white region", the density resolution is not high. .

Furthermore, since human density sensitivity decreases in resolution in the "black area," reducing the resolution beyond a certain level does not pose a practical problem.

In actual visibility, the gradation difference with lower density (brighter) is felt to be larger than the gradation difference with higher density (darker), so correction by adding the above-mentioned resistance rf is necessary. When you do this, you will feel it as a natural change in concentration.

On the other hand, an analog video signal is input to the non-inverting input terminal of the comparator 15, and an output signal (signal corresponding to the slice level) of the amplifier 14 is input to the inverting input terminal of the comparator 15. Therefore, the comparator 15 binarizes and outputs the analog video signal according to the slice level corresponding to the pattern.

In the above case, the output setting time of the slice level signal by the amplifier 14 is sufficiently short with respect to the time width of 1 bit of the finally obtained binary signal, and the binary signal which is the output signal of the comparator 15 is After digitization, if sampling is performed within a time width of 1 beat, a correct binary signal can be obtained.

In the above embodiment, if a circuit for shading correction is added to the peak detection/inversion circuit 11, more faithful halftones can be reproduced.

The pattern generator 12 can select and output a pattern according to the image as well as -dimensional dithering and two-dimensional dithering. Furthermore, when performing general binarization, the pattern output from the pattern generator 12 may be fixed.

For the resistances r1 to rm, each resistance value may be increased by a multiple, for example, r2=(rl)X2)
r3= (r2)X2)−・−・, r m=(rm
-1) If you do it like X2, pattern generator 12
By outputting a binary value from , it is possible to output a slice signal with good linearity (rl-rm above indicates the resistance value of each resistor).

In the above embodiment, if the binary pattern is output as a matrix of (number of main scans) x (number of sub-scans) according to a predetermined rule, slice levels of 211 gradations can be obtained. Here, (number of main scans)
It is assumed that =(number of sub-scans)-2N/2 (=integer).

By doing the above, the number of resistors r1 to rm+1 can be changed to the fifth
The number of resistors R1 to RN in the figure can be much smaller than the number of resistors R1 to RN in the figure, and in place of the comparators CN-CN and multiplexer 3 in the conventional example, it is sufficient to provide an amplifier 14, a comparator 15, and an analog switch 13. The entire circuit configuration becomes very simple.

In order to increase the number of gradations, the number of resistors rm may be increased, but the amount of increase in the resistance rm may be small compared to the increase in the number of gradations.

[Effects of the Invention] According to the present invention, it is possible to simplify the configuration of one circuit in an image binarization circuit that reproduces halftones based on the dither method.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing the levels of a 16-tone input grayscale. FIG. 3 is a characteristic diagram showing the output level of the photoelectric conversion element when the gray scale of FIG. 2 is read. FIG. 4 is a diagram showing the output characteristics of the amplifier in the above embodiment. FIG. 5 is a circuit diagram showing a conventional example. DESCRIPTION OF SYMBOLS 11... Peak detection/inversion circuit, 12... Pattern generator, 13... Analog switch as feedback control means, 14... Amplifier, 15... Comparator. r1~rm, rf...feedback resistance. Ward! -Ichiha Figure 2 City Survey Figure 3 Kusunoki Electric Power Regulation Figure 5

Claims (5)

[Claims] (1) A pattern generator that generates a dither pattern in the dither method; An amplifier that amplifies a predetermined signal according to the amount of feedback; A series circuit in which a plurality of resistors are connected in series, and a series circuit connected in parallel with this series circuit; a feedback resistor of the amplifier; a feedback control means for controlling the value of the feedback resistor according to the pattern; and a feedback control means that compares the output signal of the amplifier with the video analog signal, An image binarization circuit comprising: a comparator that outputs; and; (2) The image binarization circuit according to claim 1, wherein the predetermined signal is a signal corresponding to a peak value of the video analog signal. (3) The image binarization circuit according to claim 1, wherein the resistors connected in series have values that increase by a multiple of two. (4) The image binarization circuit according to claim 1, wherein the feedback control means is a switch connected in parallel with each of the plurality of resistors forming the series circuit. (5) The image binarization circuit according to claim 4, wherein the switch operates according to the output of the pattern generator.