JPS62293657A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a three-dimensional structure characterized by excellent heat radiating characteristic, by fixing and connecting semiconductor substrates, on which semiconductor elements are formed through conducting linking balls. CONSTITUTION:A smiconductor substrate 6 for lamination, on which semiconductor elements, interconnections for the elements, Al interconnections and the like are formed, is etched. Thus tapered linking holes 7 are formed. Au balls 16 are fixed in the holes 7. An insulating organic resin body 18 is embedded in each hole so that a part of each ball 16 on the hole side is exposed. The substrate 6 is overlapped so that an Au ball 23, which is fixed on each pad 22 on a good chip 21, agrees with the ball 16. The ball 23 and the ball 16 are fixed to each other. Similarly another substrate is laminated on the substrate 6. Then, thermal stress is absorbed by the balls 23, 16 and 24. Therefore, yield of cracks can be prevented. Since a required gap is formed between the substrates, the heat radiating characteristic is improved.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) This defense relates to a semiconductor device, and relates to a three-dimensional device in which a plurality of semiconductor substrates on which semiconductor elements, etc. are formed are stacked. It relates to a semiconductor device having a structure.

(Prior art) In recent years, three-dimensional S○f (311 icon on l n5 ula
口〇n) Device development is actively underway. This is a technique in which a silicon single crystal is formed on an amorphous layer on the surface of a semiconductor substrate, a semiconductor element is manufactured using the single crystal layer, and the semiconductor element is three-dimensionally fabricated. Such technology is described, for example, in Nikkei Electronics, 1985, 1.
It is described in the October 17th issue, pages 229-253, "Three-dimensional LSI emerging as a highly integrated, multi-R capability device."

However, SOI technology has just entered the stage of development and has a number of drawbacks in its practical application.

The essential drawbacks are: - Layering multiple layers of different materials;
Since single crystallization is progressed through a high-temperature process, the stress is extremely large, making it easy for cracks to occur.
■Since the layers have a dense @ structure, heat dissipation is low and heat is easily trapped. Furthermore, it is impossible with current technology to stack semiconductor materials other than silicon.

(Problems to be Solved by the Invention) The present invention solves the problems of cracking and deterioration of heat dissipation caused by the conventional three-dimensional structure described above, and provides a semiconductor device that achieves high reliability, high integration, and multifunctionality. This is what we are trying to provide.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a semiconductor substrate on which at least a semiconductor element is formed and pads are formed on a predetermined portion of the surface, and a semiconductor substrate having a connecting hole in the thickness direction. , and at least one pad is formed around the connection hole including the bottom so that at least a part of the pad is exposed to the bottom surface, and a semiconductor element is formed.
a semiconductor substrate for lamination, a conductive interconnect is fixed to an exposed portion of a pad corresponding to a connection hole of the semiconductor substrate for lamination, and an insulating material is provided in the connection hole at least for the connection of the connection grain. The hole is buried so that the opening side part thereof is exposed, and the laminated semiconductor substrate and the pad of the semiconductor substrate are connected through the connecting grain and another conductive connecting grain arranged on the pad side of the semiconductor substrate. This is a semiconductor device characterized by being fixed and stacked.

(Function) The present invention provides a semiconductor substrate on which a semiconductor element or the like is formed, and a semiconductor substrate on which the same element is formed. By fixing and connecting between the IN semiconductor substrates and further between the laminated semiconductor substrates to the exposed part of the pad corresponding to the connection hole of the laminated semiconductor substrate and the mating pad via conductive connection grains, the semiconductor substrates 8I8 on top
! semiconductor substrates can be stacked three-dimensionally. Further, since the semiconductor substrates are laminated with each other using connected grains, thermal stress can be absorbed by the M-like grains, and racking can be prevented from occurring as in the conventional Sol structure. Further, since the semiconductor substrates are laminated with each other by connecting grains, and a desired gap can be formed between the substrates, heat is not trapped between the substrates, and heat dissipation is improved. In particular, since it is possible to circulate the coolant in the gap between the substrates, a significant heat dissipation effect can be exhibited. Furthermore, since the insulating material is embedded in the connecting hole so that at least the portion of the connecting grain located therein on the opening side of the connecting hole is exposed, there is no possibility of damage due to deformation of the connecting grain located within the connecting hole. It should be possible to prevent short circuits due to contact with the semiconductor substrate exposed on the inner surface of the connecting hole.

(Examples of the Invention) Examples of the present invention will be described in detail below along with manufacturing methods.

(I) First, the thickness was 450t using the two-dimensional paper 81 manufacturing method.
A 50 μm x 5 semiconductor device, wiring between the devices (all not shown) and an Aff film were placed on a 1 m silicon wafer 1.
Pads 2..., 3... of 0 μm were formed. In addition,
Among these pads, some of the pads 3 . . . corresponding to the connection holes described below are 1. A thin oxide film is embedded in the opening formed in the insulator and is formed on the substrate surface at the bottom of the opening.

This oxide film is used to prevent the pad from being electrically connected to the substrate surface, which would interfere with the die sort test. However, instead of the thin oxide film, an impurity diffusion layer for forming a pn junction may be formed on the peripheral substrate surface including the bottom of the opening. Subsequently, openings of 30 μm x 3 Q μm are formed on the back surface of the silicon wafer 1 corresponding to the pads 3 by a combination of isotropic etching and anisotropic etching.
, I wanted to drill a wine cup-shaped hole 4 with a depth of 50 um (as shown in FIG. 1(a)). Note that etching was performed using fluorine-based gas plasma in both cases.

(If) Next, after performing a die sort test on the silicon wafer, dicing was performed to produce individual chips, and the good chips 5 were obtained by sorting (Fig. 1 (b)).
(Illustrated). Subsequently, the entire back surface of the non-defective chip 5 was subjected to anisotropic etching to produce a thin plate-shaped semiconductor substrate 6 for lamination having a thickness of 45 μm (as shown in FIG. 1C). In this anisotropic etching process, the wine cup-shaped hole 4 opened on the back surface is etched while substantially maintaining its shape, so that a tapered connecting hole 7 is formed.

Further, during the etching, the thin oxide film at the bottom of the opening was removed, so that a part of the pad 3 was exposed at the bottom of the connecting hole 7 corresponding to the opening.

(III) Next, the connecting hole 7 of the semiconductor substrate 6 for lamination
For example, spherical connected grains made of AU are fixed to the surface.This method is carried out using a connected grain fixing machine unit consisting of a gun barrel 12 with an inner diameter of 30 um and equipped with a heater 11 on the outside, as shown in FIG. This will be explained with reference to a device consisting of a holding table 15 having a built-in heater 14 and a holding table 15 on which a semiconductor substrate is set.

First, the semiconductor substrate 6 for lamination is set on the holding table 15 so that the opening of the connecting hole 7 is facing upward, and then the gun barrel 1
2 to the connecting hole 7 of the semiconductor substrate 6 (second
Figure (a) shown). Subsequently, the temperature of the holding base 15 is raised to 300°C by the built-in heater 14, and then the outside of the gun barrel 12 is maintained at about 350°C by the heater 11, and the gun barrel 12 is heated to about 350°C.
A spherical Au particle 16 with an inner diameter of 30 μm is inserted into the connecting hole 7 as shown in FIG.
It is fixed by hot pressure welding onto the exposed part of the bottom pad 3. In addition, 8 in FIG. 2(b) is a living space l! for electrically insulating the board 6 and the pad 3! A hole 9 is an opening formed in the insulating film 8 to expose a part of the pad 3 to the bottom of the connecting hole 7. Continuing, 4. An insulating organic resin body made of polyimide having heat resistance up to 00°C is injected and cured by heating to form an insulating organic resin body 18 in the connecting hole 7 as shown in FIG. The U grain was embedded so that 16 portions of the U grain were exposed to the opening side. Note that in this step, Au
If resin or paper is deposited on the part of the particle 16 on the opening side of the connecting hole 7, after curing, perform ashing treatment with oxygen plasma or the like to remove the resin film remaining on the AL116 part. Good too.

Through these steps, the AU grains 16 are fixed to the exposed portions of the pads 3 corresponding to the connecting holes 7 shown in FIG. A semiconductor substrate 6 for lamination is grown in which the Au grains 16 on the bottom side are embedded so as to be exposed.

(TV) Next, the thickness was 45 mm using the two-dimensional papermaking $1 manufacturing method.
A 50 μm x 50 f1 m pad consisting of a semiconductor element, wiring between the elements, and an Aa pattern was formed on a 0 μm silicon wafer. Subsequently, after the die sort test, the silicon wafer is diced, good chips 21 are selected, and Au particles having a spherical shape with a diameter of 40 μm are placed on the pads 22 on the surface of the good chips 21 using the above-mentioned connected particle fixing filter. 23 is shown in Figure 1 (e-illustration).

(Vl) Next, the semiconductor substrate 6 for lamination produced in the steps (I) to (III) above is placed on the good chip 21 produced in the step (1v) above, and the Au grains 23 on the pads 22 of the chip 21 and the Au grains 16 in the connecting hole 7 of the semiconductor substrate 6
After overlapping so that they match.

The semiconductor substrate 6 for lamination is attached to the chip 2 while being heated to 300°C.
1 (f) shown in FIG.

Next, a spherical Au film is formed on a predetermined pad 2.3 on the surface of the stacked semiconductor substrate 6 using the above-mentioned connection fixing method.
The grains 24 were fixed by hot pressure welding (FIG. 1 (1 diagram)).

(Vl) Next, a plurality of semiconductor substrates for the Wj root plate-like stack 11 are manufactured by the same steps as in (I) to (III) above, and these semiconductor substrates are assembled into a stack 1@shield according to FIG. 1(0) above. A multilayer semiconductor (device A (not shown)) was manufactured by sequentially laminating the semiconductor substrate 6 on the semiconductor substrate 6 using the same steps as in (V) above.

Therefore, in the semiconductor device of the present invention, between the non-defective chip 21 on which a semiconductor element etc. is formed and the semiconductor substrate 6 for lamination on which the same element is formed, each of the 81 semiconductor substrates 6B is connected to the semiconductor substrate 6 for lamination. Au grains 23.16 are connected to the exposed part of the pad 3 corresponding to the hole 7 and to the mating pad 22 as connected grains.
．． Since the semiconductor devices are fixed and laminated via the semiconductor device 24, it is possible to obtain a semiconductor device having a highly integrated and multifunctional three-dimensional structure.

In addition, the lamination between the non-defective chip 21, the semiconductor substrate for lamination 6, and each semiconductor substrate for lamination 6 is performed using Au grains 23 as connection grains.
．． 16.24 Cough A due to heat stress
Since it can be absorbed by U-grain 23.16.24, the conventional 801
It is possible to prevent the occurrence of racks due to the structure. Moreover, for the same reason, a desired gap can be formed between the non-defective chip 21 and the laminated semiconductor substrate 6, and between each semiconductor substrate 6.
Heat dissipation is improved without heat being trapped between each board.

Therefore, a semiconductor device having a highly reliable three-dimensional structure can be obtained.

Furthermore, an insulating organic resin body 18 as an insulating material is placed in the connecting hole 7 of the laminated semiconductor substrate 6 at a portion of the spherical Au grain 16 located in the connecting hole 7 on the opening side of the connecting hole 7, that is, the other side. Since the contact portion with the side Au grains 23 is buried so as to be exposed, even if the Au grains 16 are deformed when the Au grains 16 in the connecting holes 7 and the Au grains 23 of the substrate 21 are fixed, the lamination will not occur. Au grains 16 are formed on the inner surface of the connecting hole 7 of the semiconductor substrate 6 for
The insulating organic resin body 18 can prevent the insulating organic resin body 18 from coming into contact. As a result, short circuits caused by contact between the AU grains 16 and the laminating semiconductor substrate 6 can be prevented.

In the above embodiment, spherical Au grains were used as the connected grains, but for the purpose of cost reduction, etc., connected grains in which the surfaces of spherical stainless steel grains were coated with an ALI film may be used.

Specifically, a nickel film 32 with a thickness of about 3 μm is formed on the surface of a spherical stainless grain with a diameter of 30 μm by a plating method, and a nickel film 32 with a thickness of about 3 μm is further formed on the nickel film by a plating method.
Connected grains formed with a μm-sized AIJ film may also be used. In this case, particles of other metals, glass, ceramics, or heat-resistant plastics may be used instead of stainless steel particles. Further, the shape of the connected grains is not limited to a spherical shape, but may be any shape such as a cylindrical shape. However, from the viewpoint of thermal stress alleviation effect and operability, it is desirable to use spherical connected grains.

In the above embodiment, polyimide resin was used as the insulating material, but other insulating organic resins such as silicone resin and epoxy resin may also be used.

In the above practical example, a structure is described in which only a plurality of laminated semiconductor substrates made of silicon are used and these laminated semiconductor substrates are laminated on a chip, but the present invention is not limited to this. For example, a wiring board is inserted between the semiconductor substrates for lamination via a connecting grain, and the current between the semiconductor substrate for lamination on the lower layer side and the semiconductor substrate for W4 layer on the upper @ side with the wiring substrate as a boundary. The route may be changed. Further, as shown in FIG. 3, a chip 31 is formed of silicon, a silicon semiconductor substrate 32 and a gallium arsenide semiconductor substrate 33 are laminated on this silicon chip 31, and further these silicon semiconductor substrate 32 and gallium arsenide semiconductor substrate 33 are laminated. The semiconductor device may have a three-dimensional structure in which a silicon semiconductor substrate 34 is stacked on top of the semiconductor substrate. If the configuration shown in FIG. 3 is adopted, the conventional 5o
A semiconductor device with a three-dimensional structure that is more versatile than that of an IL structure can be easily realized.

[Effects of the Invention] As detailed above, the present invention prevents the occurrence of cracks due to thermal stress, improves heat dissipation, and further improves the conventional S
It is possible to provide a semiconductor device with a three-dimensional structure that is highly integrated and highly reliable and can be multi-functional compared to the OL structure.

[Brief explanation of the drawing]

Figure 1 (a) to (Q) are three-dimensional, one-kiri, half-R of one light.
Cross-sectional view showing the manufacturing process for obtaining body rigidity, Figure 2 (a
) to (C) are A to the pad of the connecting hole of the semiconductor substrate for lamination
FIG. 3 is a cross-sectional view showing the process of fixing LL grains and embedding an insulating material in the connecting holes. FIG. 3 is a cross-sectional view showing an example of the connected grain pond used in the present invention. FIG. 3 is a cross-sectional view showing a three-dimensional structure semiconductor device showing another example. 1... Silicon wafer, 2.3.22... Pad,
6...Semiconductor substrate for lamination, 7...Connection hole, 8...
Interlayer insulating film, 9... Opening part, 12... Gun barrel, Yu...
・Connected grain fixing machine, 15...holding stand, 16.23.24
... AU grain, 18 ... Insulating resin body (insulating material), 21 ... Good chip, 31 ... Silicon chip, 32.34 ... Silicon semiconductor substrate, 33 ... Gallium Arsenic semiconductor substrate. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 1 Figure 2

Claims (3)

[Claims] (1) A semiconductor substrate having at least a semiconductor element formed thereon and a pad formed on a predetermined portion of the surface, and a semiconductor substrate having a connecting hole in the thickness direction, and at least a pad around the bottom of the connecting hole. at least one laminated semiconductor substrate formed such that a portion thereof is exposed on the bottom surface and on which a semiconductor element is formed, and a conductive material is provided in the exposed portion of the pad corresponding to the connection hole of the laminated semiconductor substrate. At the same time as fixing the connecting grains, embedding an insulating material in the connecting hole so that at least a portion of the connecting grain on the opening side of the connecting hole is exposed, and connecting the semiconductor substrate for lamination and the pad of the semiconductor substrate. A semiconductor device characterized in that the connecting grains are fixed to each other through another conductive connecting grain arranged on the pad side of the semiconductor substrate and stacked. (2) The semiconductor substrate for lamination consists of multiple sheets, each of which has pads in areas other than the area corresponding to the connecting holes, and the pads other than the connecting holes of the semiconductor substrate for lamination of the first layer and the pads for lamination of the second layer. The exposed part of the pad corresponding to the connection hole of the semiconductor substrate is
Claim 1, characterized in that the semiconductor substrates for lamination of the third and subsequent layers are fixed and laminated through two conductive connecting grains, and similarly, the third and subsequent layers of semiconductor substrates are successively fixed and laminated through the conductive connecting grains. semiconductor devices. (3) The semiconductor device according to claim 1, wherein the thickness of the semiconductor substrate for lamination and the size of the connected grains are substantially the same.