JPS62289996A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the layout of an address buffer circuit and a refresh address counter by providing the address buffer circuit for external address and that for refresh address independently of each other and connecting their outputs by wired OR. CONSTITUTION:At the time of normal operation, an external address signal is amplified by an address buffer circuit 4 and is inputted to a decoder circuit 6. In such case, the output of an address buffer circuit 3 is made high-impedance because the address signal outputted from the circuit 4 is connected to that from the circuit 3 in the circuit 6 by wired OR. In a refresh cycle, the output of a refresh address counter 2 is amplified by the circuit 3 and is supplied to the circuit 6 to make the output of the circuit 4 high-impedance. By such constitution where the address buffer circuit for normal address and that for refresh address are made independent of each other, the number of degrees of freedom for the layout of the circuit 4 and the counter 2 is increased, and the input capacity of address is reduced and drawing-around of wiring is made unnecessary to improve the operation speed characteristic.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit in which the input capacitance of an external address input signal is reduced.

[Conventional technology]

Due to the miniaturization of semiconductor memory IJH patterns, capacity increases are progressing. Among these, dynamic random access memory (hereinafter referred to as DRAM), which is composed of one transistor and one capacitor memory cell (hereinafter referred to as IT cell), which can be highly integrated, is mainstream, and as of p1, 25
The content has been expanded from the 6 kilobit mass-produced type to the 1 megabit 14-shot type.

However, since DRAM relies solely on capacitors for information, information is lost over time, and the need to rewrite (hereinafter referred to as refresh) the memory cells within a certain period of time is a factor that makes them difficult to use. It becomes. The most common method of refresh operation is RAS only refresh (Only Refresh), which specifies only the row address. However, since it is necessary to specify the address externally, there is currently no refresh address specification internal to the chip. Counter k of 11
L, RA S (o address strop) and CAS
CA8 Before RA that operates the refresh address counter and serially selects the word line based on the input timing of the column address strobe.
In addition to the S refresh a, (几refresh) and the counter, there is also an auto refresh that generates a refresh pulse using a timer.
), but when a chip has a counter for specifying a refresher address or performs a refresher operation like this, the address buffer circuit generally uses both the external address signal and the output signal of the refresh address counter. It is true. In this case, the layout of the address buffer circuit and the refresher address counter becomes a problem due to bonding and address input capacitance depending on the position of the refresh address terminal.

Figure 2(a) shows a 300 mil 16 py DIP (
FIG. 2 is a plan view of a dual-in-line package.

For example, a standard DRAM package (256 kilobits) is 300 m1 with 16 bins as shown in Figure 2(a).
l DIP (Dual-In-Line-Packa)
ge), whose pin configuration is the second one for compatibility.
It is standardized as shown in the Ca1 diagram. FIG. 3(a) is a pad layout diagram of each bonding pad on the chip of the 300 ml 16-bin DIP shown in FIG. 2(a). For simplicity, if we assume that the side where the ground pad Vss is located is the Vss side, then of the 80"" A@ address pads, A0 to AI, A? is on the VDD side, A6. k@ is V
It will be laid out on the ss side. If the refresh cycle is t-256 cycles, mAo to A1 will be the refresh address terminals.
Since A6 becomes the refresher address terminal, either install only the address buffer circuit on the 1Vss side and route the output of the counter installed on VDD, or install the buffer circuit and counter on VDD[ll and route the address input signal. become.

2nd Φ) is a 300ml 18 pin DIP (D plan view. For example, a standard package of 1 megabit DRAM is a 300ml 1118 bin DIP shown in Figure 2(b), and if the refresh cycle '!+1-
If it is 256 cycles, it is a reflation of AO, A.

Although it can be installed on the shared address terminal '1VDD side, as many as 4096 sense amplifier circuits are required, resulting in a significant increase in current consumption, so 512 reflex cycles are common. Therefore, among the refresher address terminals Ao-As, either terminal Ao or A8 must be installed on the Vss side.

Figure 35) is the 300ml 18 pin y DIP in Figure 2-)
FIG. 3 is a pad layout diagram of each bonding pad on the chip of FIG. In the case of the bonding pad layout shown in Fig. 3), the same problem as explained in Fig. 305) occurs.

[Problem that the invention seeks to solve]

As mentioned above, the conventional address buffer circuit with a freshly shared address counter is a circuit that also serves as an external address signal and the output signal of the freshly shared address counter, so the external address signal line is routed and refreshed to the VDD side. It is necessary to layout the address counter and address buffer circuit, or to separate the address counter and route the output signal of the refresher address counter for the address buffer circuit and refresher, so that the maximum standard value of the input capacitance of the address input is satisfied. However, there are disadvantages in that it may become impossible to use, or it may have a large effect on characteristics such as memory speed.

Also, if an 18-pin package is used at the 300m point up to 4 megabits, the size of the largest chip that can fit in the case in the short side direction will not change, so the above problem will inevitably be solved. , the disadvantage is that it becomes even more serious.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a first address buffer circuit that receives an external address signal as an input, a refresher address counter for specifying a refresh address, and a second address buffer that receives an output signal of the refresh address counter as an input. The address buffer circuit has a structure in which the outputs of the first address buffer circuit and the second address buffer circuit are wired OR-connected.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 1 is a refresh control circuit, 2 is a refresher address counter, 3 and 4 are address buffer circuits, 5 is an address control circuit, 6 is a decoder circuit, and Ai
(EXT) is an external address signal, a is a refresh control signal, a' is an address buffer circuit output high-impedance signal, bi, bi are refresher address counter output signals, Ci, Ci, fi, fiti address signal, d is an address It is a control signal.

Next, the operation of this embodiment will be explained. First, in the case of a normal read/write cycle, an external address signal Ai (EXT) input from an external address is amplified by the address buffer circuit 4 and input to the decoder circuit 6. At that time, the address signal f t output from the address buffer circuit 4
*” H, address signals C+ and Ci output from the address buffer circuit 3 and wired O via the decoder 6t-
Since it is R-connected, all outputs of the refresh address buffer circuit 3 are made high impedance. Further, in the case of a refresh cycle, the refresher address counter output signal bi, which is specified by the refresher address counter 2, is amplified by the bit-address buffer circuit 3 and input to the decoder circuit 6.

At this time, the output of the address buffer circuit 4 is set to high impedance. The output of the address buffer circuit 4 and means for making it high impedance are provided by the refresh control circuit 1.
Which address buffer circuit is set to high impedance can be easily controlled by the address buffer circuit output high impedance signal %at used to determine whether or not the reflex operation is performed.

〔Effect of the invention〕

As explained above, the present invention provides an address buffer circuit for external address designation and an address buffer circuit for fresh share address counter designation separately, and connects the outputs of each with a wired OR connection. The layout of the circuit and refresher address counter becomes easier, the address input capacitance is reduced, wiring is no longer necessary, and characteristics such as speed can be significantly improved.

Of the two address buffer circuits, the address buffer circuit for specifying the refresher address counter is
Since the input signal is at the level of the power supply voltage or ground voltage, it can be configured with a simpler buffer circuit than an address buffer circuit for external address designation, and the area need not increase significantly.

In addition, from 1 megabit DRAM to 4 megabit) DRA
Up to M, there is a possibility that a 300ml 18by DIP may be used and it extends in the long side direction of the chip, so the present invention becomes even more effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
) The figure is a plan view of a 300ml 16-bin DIP, the second
俤)Figure t! Plan view of 300ml 18-bin DIP,
3rd (a1 figure is 2nd (- figure's 3oomtl 16biyD
Pad layout diagram of IP, Figure 3 Φ) is a pad layout diagram of the 300ml 18 pin DIP in Figure 2(b). 1... Refresh control circuit, 2...
Refresh address 0 counter, 3...address buffer circuit, 4...address buffer circuit, 5...address control circuit, 6...-decoder circuit.寥 1 Former 2nd (Gengensen 2 Fuchida

Claims (1)

[Claims] The first address buffer circuit includes a first address buffer circuit that receives an external address signal as an input, a refresh address counter for specifying a refresh address, and a second address buffer circuit that receives an output signal of the refresh address counter as an input. 1. A semiconductor integrated circuit characterized in that an address buffer circuit and an output of a second address buffer circuit are wired OR connected.