JPS6228628B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to data compression in image data processing systems, and more particularly to digital data compression, such as raster scanned binary image systems.

BACKGROUND OF THE INVENTION Records (ie, printed and handwritten documents, drawings, and photographs) are essentially more or less continuous two-dimensional reflection patterns. Thus, an image data processing system classically includes a raster input scanner that sequentially rearranges or converts the information content (i.e., an image) of an input document into a corresponding one-dimensional video signal;
and a raster output scanner for sequentially copying or facsimileing the input record in response to the video signal. Since there are hybrid systems that have the ability to convert to or from raster scan video signal formats, raster input and output scanners can be interfaced with devices having other signal formats, such as teletype terminals using ASCII codes. (interconnection). However, typically raster input and output scanners are used in complementary combinations to form so-called raster scan imaging systems.

Raster input and output scans configure unique scans so that the image has a predetermined number of picture elements (often called "pixels") for each of a plurality of approximately equally spaced scan lines. It is represented by a constructed video signal. Therefore, the resolution of a raster scan is typically the product of a given number of scan lines per centimeter, for example in the vertical axis, and a given number of strokes or line pairs per centimeter in the orthogonal or horizontal axis. expressed in terms of For example, the Xerox 200 Telecopier facsimile transceiver manufactured and sold by Xerox Corporation has units of scanning lines per vertical centimeter and pixels per horizontal centimeter.
It allows you to select the resolution according to a conveniently determined speed (corresponding to the nominal recording transmission time for standard 21.59cm x 27.94cm recording), and for recording transmission times of 3 minutes and 6 minutes, it is approximately 96 96, approximately 64×96 when the recording transmission time is 4 minutes, and approximately 77×80 when the recording transmission time is 2 minutes. It should be understood that these are more or less standard resolutions in current facsimile systems, and that they are generally near the lower limit of the raster scanner's effective resolution range. Significantly lower resolutions are typically avoided because there is an unacceptable risk of losing important visual detail.

Original video signals of the type mentioned above typically contain a significant amount of redundant information. Therefore, if the video circuitry for a raster input or output scanner consists of a transmission medium of limited bandwidth or a storage medium of limited capacity, increased data processing efficiency will eliminate redundant information from the video signal. This can generally be accomplished by providing an upstream data compression stage and a downstream data compression stage to recover this redundant information. Binary video signals are very well suited for data compression and decompression because the pixels are either black or white (“1” or “0”), but this eliminates all intermediate levels. Tonal gray is lost. For this reason, considerable effort and resources have been invested in developing methods and means for digital data compression and decompression.

Run-length encoding and decoding have received wide attention as techniques for compressing and decompressing binary video signals having a raster scan format, respectively. Basically, encoding is converting the white and/or black runs of a binary video signal into corresponding message codes, and decoding is converting these codes into white and/or black runs of appropriate length. The process is to convert the video signal into a video signal and reassemble the video signal. In this relationship, a "run" is defined as at least one or more uninterrupted consecutive pixels at the same logic level, and the "length" of a run is determined by the number of pixels it contains. It will be done.

When performing encoding, message codes are preselected to individually detect encoded run lengths. Message
The codes are of variable length (i.e., different bit counts) and have a given run length probability such that codes assigned to a given run length are no longer longer than codes assigned to run lengths with lower probabilities. Preferably, the run lengths are assigned to run lengths which are encoded according to a distribution.

Unfortunately, if the types are not restricted, the redundancy of all images is completely random, and an unrestricted record set does not provide a meaningful run length probability distribution.
Therefore, to take advantage of the run length probability distribution when assigning message codes,
It is necessary to focus on subsets of records that share common image characteristics. For example, when optimizing the compression of data prepared for regular business correspondence, the probability distribution of run lengths can be determined by pre-scanning a relatively small number of sample records based on alphabetic characters. It can also be based on the run length frequency statistics obtained. Of course, this subset is
The run length statistics are weighted in favor of those samples that we subjectively judge to be closest to the expected criteria, allowing for considerable variation in page extent and composition and text size and style. It is to be ensured.

In addition, it has been confirmed that data compression can be achieved by changing the basic run-length encoding process. In general, the proposed transformations tended to increase the average run length given for encoding.

In particular, HEWhite
“Dictionary Look for Shape Data”
−up) type encoding “(TS Huang (TS
Huang, Gordon and Breach, Image Bandwidth Compression, published 1972, Vol.
(pp. 267-281) suggest that the original video encodes ``instantaneous rates of change, or transient equivalence.''
In these implementations, the definition of a run is expanded to include not only uninterrupted consecutive pixels of one logic level, but also pixels of the opposite logic level with a single termination.

Another interesting proposal concerns a predictive coding process known as differential modulation.
When this process is executed, differences between corresponding pixels in successive scanning lines are compared, thereby generating a binary prediction signal (hereinafter referred to as a differentially modulated video signal). The differentially modulated video signal distinguishes pixels of subsequent scan lines that are at the same logic level as corresponding pixels of previous scan lines from those that are not.
The difference signal will have a relatively long run at logic levels indicating that the pixels in the two scan lines are the same. There is usually considerable inter-scan line redundancy. However, there is a risk that errors that occur when reproducing pixels of one scan line will be propagated through the next scan line. Therefore, in order to prevent the propagation of these errors, it is necessary to use, for example, U.S. Pat. No. 3,830,966 to WHAldrich et al. It is desirable to periodically encode and decode a scan line of original or unmodulated pixels, as shown in ``Apparatus and Method for Transmitting a Pixel.''

(Problems to be Solved by the Invention) Against this background, a first object of the present invention is to provide an improved method and apparatus for compressing binary video signals having a raster scan format. .

More particularly, in accordance with one aspect of the invention, its purpose is to convert terminated runs into run-length message codes and unterminated runs into end-of-line message codes. ) run length encoding method and apparatus. A related object is to provide a truncated run length encoding method and apparatus for encoding scan lines of differentially modulated and unmodulated pixels.

According to another feature of the invention, the purpose is to
An object of the present invention is to provide a method and apparatus for reducing the number of special message codes required for length encoding. A more specific object is to provide a method and apparatus for generating modular block length multiple plus remainder run length message codes.

According to yet another aspect of the invention, it is a further object to provide a method and apparatus for subtracting variable length bytes of data from fixed length bytes. A more specific and related object is to provide a method and apparatus for storing a look-up table of three-character messages for a run-length encoder utilizing word-oriented memory.

SUMMARY OF THE INVENTION In summary, to realize these and other features of the invention, pixels of a binary video signal having a raster scan format are serially applied to a differential modulator, The modulator is periodically energized and deenergized to sequentially provide scan lines of differentially modulated and unmodulated pixels to a truncated run length encoder.
Terminated runs in the truncated run-length encoder are converted to run-length message codes, and unterminated runs are converted to end-of-line message codes.
The same run-length message code is used to encode the finished runs of modulated and unmodulated pixels, but whether differential demodulation of the scan lines is needed to reassemble the video signal. There is a differential end-of-message code that conveys the . To limit the number of specialized message codes required to encode a terminated run, the run length message code has a modular structure. These runs are therefore represented by block length multiple codes when they exceed a predetermined block length plus run length remainder code and when they are not an integral multiple of the block length.

Still other objects and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.

While various features of the invention will be described in detail below with specific reference to a single embodiment, it will be clearly understood that the invention is not intended to be limited to this embodiment. On the contrary, the aim is to cover all changes, substitutions and equivalents falling within the spirit and scope of the invention as defined by the claims.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the figures, and particularly now to FIG. 1, there is a video data processing system 11 that includes a digital data compressor 12 for compressing a binary video signal in raster scan format in accordance with the present invention. As shown, the video data processing system 11 is a raster scanning video system, and more specifically includes a transmitting terminal device 13 and a receiving terminal device 14 connected to a communication line 15 on a demand basis, for example.
It is a digital facsimile system with Typically, the communication line 15 is a limited bandwidth transmission line constructed from a public switched telephone network.

To explain the transmitting terminal device 13 at a functional level,
There is a raster input scanner 16, which includes the original record (i.e.
Convert the information content of the “target copy”) into a corresponding video signal. Analog-to-digital converter 17 samples the video signal at a predetermined rate in response to internally generated clock pulses and quantizes these samples to obtain the original binary video signal in raster format. represents the information content of the target copy. As a practical example, the scanning pitch of the input scanner 16 and the sampling rate of the analog-to-digital converter 17 are
It shall be chosen to achieve a resolution of 80.3 pixels per horizontal centimeter for 37.8 scan lines. Under these conditions, a standard 3.35cm x 4.33cm recording scan produces a binary video signal with 1056 scanning lines and 1728 pixels per scanning line, or a total of 1824768 pixels per page. supply. However, in a typical case, most of these pixels only represent redundant information.

Therefore, to reduce redundancy, the binary video signal is encoded by the digital compressor 12 and sent to the digital signal via the rate matching buffer 18.
An encoded and data-compressed video signal to be supplied to the modem 19 is obtained. The optional carrier signal is modulated in digital modem 19 according to the encoded video signal and provides a passband signal to be transmitted via communications line 15 to receiving terminal equipment 14 . Apparently, the buffer 18 is connected to the modem 19 from the upstream element of the transmitting terminal 13.
, so that the data transmission rate of the passband can be selected somewhat independently of the input scanning and sampling rate.

The receiving terminal device 14 has a complementary modem 21, and demodulates the input passband signal to obtain the encoded video signal again. This video signal is then passed through an optional rate matching buffer 22 to a digital data decompressor 23 which performs the necessary decoding to reassemble the original binary video signal.
supplied to Raster output scanner 24 then prints a copy or "facsimile" of the target copy in response to the reassembled video signal.

As shown in FIG. 2, in accordance with conventional means, input scanner 16 periodically scans the target copy from scan line to scan line. Each successive scan cycle causes the input scanner 16 to first actively scan across the target copy in one direction (e.g., from left to right) and then passively fly back in the opposite direction. and prepare for the next cycle. This type of input and output scanner is
No. 3,869,569, issued March 4, 1975, to Peter J. A. Mason et al.
No. 1, “Facry Milli Transmitter/Receiver Apparatus”. Accordingly, this patent and the commercially available devices mentioned above are hereby incorporated by reference. However, it should ultimately be noted that the aforementioned scanner consists of a laser optically arranged with a scanning mirror of a galvanometric polarization mechanism. Thus, when the scanner operates in scanning mode, the scanning mirror oscillates periodically to sweep back and forth across the elongated scanning aperture, and the laser is activated and extinguished in synchronization with the oscillations of the scanning mirror. selectively provides a beam of light to illuminate the target copy while the scanning mirror is swept from side to side through the scanning aperture. However, this excludes the period when the scanning mirror flies back in the opposite direction, that is, from right to left.

The object copy is incrementally advanced in the longitudinal direction of the scanning aperture in cooperation with the scanning mirror to obtain the orthogonal motion necessary to generate the raster scanning pattern.

Referring to FIG. 3, the digital data compressor 12 includes a differential modulator 31 and a truncated run length encoder 32, which are controlled by a suppressor 33 to determine the next scan cycle. Successive scan lines of binary pixels are stored and encoded in each of the active and passive regions. It is clear that the differential modulator 31 is configured to be activated and deactivated periodically. In other words,
The encoding of scanlines of differentially modulated pixels is periodically interrupted to cause at least one scanline of unmodulated pixels to be encoded, thereby limiting the propagation of encoding errors between scanlines. On the other hand, the run length encoder 32 is a modular encoder in which the differentially modulated and non-modulated pixels encode a "white run ending in black".
The run-length message code structure and differentially modulated and non-modulated pixels represent unterminated white runs.
It is equipped with a truncated run-length encoding process characterized by using the message code.

In this case, "black" and "white" are used as convenient terms to distinguish between differentially modulated pixels and non-modulated pixels of opposite logic levels (ie, "1" and "0"). However, when color is intended to be meant by these terms, it is only that the original or unmodulated black and white pixels represent the image and background, respectively. Even such limited correlation is lacking in the case of differentially modulated pixels, since such modulation imparts a differential meaning to the logic levels of the modulated pixels.

From the above, in particular, the differential modulator 31 has a serial input/parallel output shift register means 41 that sequentially supplies pixels in parallel and sequentially to the differential detector 42 spatially corresponding to the next pair of adjacent scanning lines. Equipped with. Each of these pairs of pixels in a scan line is applied directly to a first input of a difference detector 42.
Conveniently, however, to prevent decoding errors from propagating between scan lines, the pixels of other scan lines are periodically de-energized by a self-resetting line counter 44 using an AND gate. 43 to the second input of the difference detector 42.
When AND gate 43 is activated, difference detector 42 generates a binary signal representing the modulo 2 difference (difference between two binary values) between two adjacent scan lines. Conversely, when AND gate 43 is deenergized, differential detector 42 passes the original pixels of the ungated, ie, current, scan line in an unmodulated form.

Focusing on the shift register means 41, the original binary pixels provided by the analog-to-digital converter 17 are responsive to write and read clock pulses and are transferred to the shift register means 41.
It can be seen that it is serially shifted through 1. These pulses are provided by controller 33 to one or more clock inputs of shift register means 41 in each of the active and passive regions of each scan cycle. Therefore, shift register means 41 is used to provide a stream of spatially corresponding parallel pixels in the current and previous scan line.
has 3n stages connected in series. where "n" is equal to pixels per scan line, and parallel outputs are taken from the n and 3n stages. The write clock pulses for the shift register means 41 are preferably obtained from the analog-to-digital converter 17, but arrangement is made within the controller 33 to generate the read clock pulses.

A single multi-stage shift register can be configured to perform the operations described above. However,
If the shift register means 41 consists of three line lengths, ie, n-stage shift registers 4 connected in series,
If it is represented as being formed by pixels 5 to 47, it will be easier to follow the flow of pixels. Of course, at the output of each scan operation, all stages of shift registers 45-47 are cleared to a low ("0") logic level in response to a scan start signal output from input scanner 16, for example. The original binary pixels of the first scan line are then clocked by the write clock supplied in the active region of the first scan cycle.
It is serially shifted into the first shift register 45 in response to a pulse. These pixels are then read out and added to the write clock pulses provided in the passive part of the first scan cycle and the active part of the second scan cycle, respectively, to the second stage of n stages. It is shifted via the shift register 46 to a third shift register 47 having n stages. Additionally, the original binary pixels of the next scan line are serially loaded into the first shift register 45 of n stages in response to a write clock pulse provided in the active region of the second scan cycle. Pixels provided in subsequent scan cycles follow a similar path. Thus, spatially corresponding original binary pixels in the current and previous scan lines are read out in shift register 45 and in response to readout clock pulses applied in the passive region of each scan cycle, except for the first scan cycle. It will be appreciated that each of the 47 final stages is fed in parallel. The first cycle is an exception for the simple fact that there are no pixels from the previous scan line at that time; this is because the n-stage third shift register 47 remains low (“0”) throughout this cycle. ) means at a logical level.

It may be useful to note here that "spatially corresponding" is used here as a convenient expression for pixels occupying the same relative position on different scan lines. . In a one-dimensional video signal, spatially corresponding pixels are pixels that occupy the same numerical position in separate scan lines (e.g., the fifth pixel in the first scan line and the pixel in the next 5th scan line
(spatially corresponds to the th pixel). Similarly, in a two-dimensional object copy, spatially corresponding pixels are pixels separated by spaces arranged in the direction of the scan pitch on the object copy, and these pixels or regions have their respective information content. I have it too. For example, if the scan pitch is measured in the vertical direction of the target copy, spatially corresponding pixels represent the information content of each vertically aligned area of the target copy.

Redundancy between scan lines is characterized by a statistically significant degree of overlap between spatially corresponding binary pixels for adjacent scan lines. Therefore, to increase the average run length of white or low ("0") logic levels, the difference detector 42
is provided, which converts a partial scan line of original binary pixels into a scan line of differentially modulated pixels, and this differentially modulated pixel corresponds spatially to the scan line being converted and the immediately preceding scan line. represents the difference in modulus 2 between binary pixels. Increasing the average run length tends to reduce the number of bits required to convey a given amount of information in a run length encoded format. In other words, it will be appreciated that this provides the possibility of achieving increased data compression. Nevertheless, there is an attendant risk that errors made when decoding pixels of one scan line will propagate to all of the next differentially modulated scan lines. This is because the reproduction of binary video signals is based on complementary differential demodulation processing. That is, the differentially modulated pixels of the scanning line being demodulated are demodulated by adding modulus 2 to the spatially corresponding original binary pixels reproduced in the immediately previous scanning line.

For these reasons, maximizing data compression and
A balance is struck between two competing goals: limiting inter-scanline propagation of decoding errors. For this purpose, one input of the difference detector 42 is connected to the output or final stage of the shift register 45 to receive directly the original binary pixel as the so-called current scan line. Meanwhile, the original binary pixels from the previous scan line are gated from the output or final stage of shift register 47 to the other input of difference detector 42 via AND gate 43. and gate 43
is periodically disabled by line counter 44, as previously described. To perform this gating function, AND gate 43 has one input connected to the output of shift register 47 , the other input connected to the output of line counter 44 , and one input connected to the output of line counter 44 , and one input connected to the output of line counter 44 . and an output connected to the second input.

Considering the function of the differential modulator 31, the differential detector 42 receives input from an AND gate 43 and a shift register 45. It will be appreciated that a binary output signal is generated representing a modulus 2 difference between the input signals. The original binary pixels of the current scan line are serially shifted out of shift register 45 in the passive region of each scan cycle. However, AND gate 43 is deenergized by a low ("0") logic level provided by shift register 47 throughout the first scan cycle. Therefore, the original binary pixels of the first scan line are detected by the detector 4 in the passive region of the first cycle.
It is played with 2 outputs. Conversely, as shown in FIG. 4, spatially corresponding pixels of the current scan line a and the previous scan line b are transferred in parallel from shift registers 45 and 47, respectively, in the passive region of each subsequent scan cycle. supplied to Thus, differential detector 42 responsively generates a scan line c of delta modulated pixels unless AND gate 43 is deactivated by line counter 44.

As will be recalled, line counter 44 disables AND gate 43 to limit the propagation of decoding errors between scan lines. For this reason, the line counter 44 is a multi-stage ring counter 48.
is suitably configured, the final stage of which is connected to the input of AND gate 43 via an inverter 49. Typically, ring counter 48 is reset or cleared at the beginning of each scan operation in response to the aforementioned initiation of the scan signal, and is then reset or cleared by input scanner 16, for example, at the end of the active region of each scan cycle. is incremented once for each scan line in response to the scan line end signal provided. At this time, there is a cycling high ("1") logic level pulse that advances from stage to stage of ring counter 48 at a line scan rate, thereby causing AND for one cycle from each of a predetermined number of scan cycles. A low (“0”) logic level signal is provided from inverter 49 which de-energizes gate 43.
As a result, the difference detector 42 is periodically inhibited from accepting pixels from the so-called previous scan line from the shift register 47. Therefore, in practice, the differential detector 42 is periodically switched between modulated and non-modulated modes of operation to scan differentially modulated pixels followed by a predetermined number of original or non-modulated pixels. Generate a repeating line sequence. As can be seen, decoding errors do not propagate through the scan lines of non-modulated pixels since the non-modulated pixels are reproduced without repeating the pixels of other scan lines. For example, when the ring counter 48 consists of 5 stages, one scanning line of original binary pixels has 5 stages.
Differential modulator 4 in the passive region every scan cycle
2 is generated again. This limits the propagation of decoding errors between scan lines to at most five scan lines. Still, it is possible to differentially modulate roughly 80 percent of the pixels. The reason for this is that when a five-stage ring counter 48 is used, the differential modulator 42 has five stages.
Because we regenerate one original pixel scan line for each book scan line, 4 out of 5 scan lines (i.e., 80 percent) are differentially modulated before being encoded. be. The fifth scan line consists of original pixels to limit the propagation of decoding errors.

In order to compress the delta modulated and non-modulated pixels provided by the differential modulator 31, the run length encoder 32 selectively compresses the delta modulated and unmodulated pixels provided by the differential modulator 31 by means including a binary run length counter 52 and a binary pixel counter 53. memory means 5 addressed to
1 to serially (a) convert white runs terminated with black into the corresponding run-length message code, and (b) convert unterminated white runs to the corresponding end-length message code.
and (c) converting unterminated black pixels into individual message bits at a predetermined logic level. There is no need to distinguish between differentially modulated pixels and non-modulated pixels while processing black terminated white runs and unterminated black pixels. However, a proper line-by-scanline indication of whether a pixel is differentially modulated is a separate endpoint that encodes differentially modulated and non-modulated pixels.
Obtained simply by using the off-line message code.

The run-length message code, the end-of-line message code, and the individual message bits are mutually exclusive and are therefore organized into a serial video data stream by the run-length encoder 32. It is desirable that the boundary between them be automatically identified even after the completion of the process. Therefore, as shown in FIG. The code is selected to have a unique bit sequence different from the code. Of course, these guidelines are compatible with the use of so-called tree codes or variable length (or bit counter) run length message codes. Therefore, the basic Huffman rule that takes advantage of variable length run length message codes states that codes assigned to a given run length are likely to be longer than codes assigned to run lengths with lower probabilities. It should be remembered that this should not be the case.

Black-terminating white runs and unterminated black pixels can generally be classified as sequences in which at least one or more pixels terminate in black. From this perspective, run length,
Counter 52 serially generates a fixed length binary count, which count is applied to differential modulator 31.
The number of differentially modulated or non-modulated pixels appearing at the output of , in a continuous sequence ending in black, is expressed numerically. The bits of each of these counts are provided in parallel to memory means 51 via gate 55 and address bus 56. This serially supplies the address code and reads from the memory means 51 the run length message code and the black terminated white runs and unterminated black pixels, respectively. Assuming again that there are 1728 pixels per scan line, a 12-bit binary counter is the appropriate configuration for the address code.
I think it will be well understood from what follows.
Twelve bits, even if included in this case, merely simplify the address interface of the memory means 51, since eleven bits are sufficient to individually define counts up to 1728.
i.e. 1728 in 11-bit binary is 110 1100
Equals 0000 or 0110 in 12-bit binary
Equal to 1100 0000. The differentially modulated and non-modulated pixels of the runs connected by black that appear at the output of the differential modulator 31 are assigned to corresponding binary counting addresses.
To convert to code, binary run length counter 52 is reset or cleared at the end of the active region of each scan cycle in response to the aforementioned end of scan line signal provided, for example, from input scan line 16; It is increased in the passive region of each scan cycle in response to read clock pulses provided by controller 33. Furthermore, a black level detector 57
monitors the logic level of the pixel provided by the difference detector 42 in response to the readout clock pulse. This ensures that whenever a black (i.e., high ("1") logic level) differentially modulated or non-modulated pixel is detected at the output of the differential detector 42, the controller 3
3 sequentially energizes gate 55, then the binary
Provides an asynchronous control signal that causes run length counter 52 to be reset.

Thus, the binary run length counter 52 generates a binary count one after the other, and not only when the output of the difference detector 42 for the first pixel of each scan line appears, but also after each black pixel. A new count also occurs when the first pixel appears. The readout clock pulse is a binary signal for each white (low (“0”) logic level) and each black (high (“1”) logic level) differentially modulated or non-modulated pixel provided by the differential detector 42. - Increase the count accumulated by the run length counter 52 by one. Normally, by closing the gate 55, the memory means 51
The binary run length counter 52 is separated from the binary run length counter 52. However, when the black level detector 57 detects the presence of a black modulated or unmodulated pixel at the output of the difference detector 42, the controller 33 opens or closes the gate 55, so that the binary run is interrupted at that point. - Bits specifying the count accumulated in length counter 52 are routed in parallel through address bus 56 to address memory means 51; The controller 33 then resets the binary run length counter 52 before providing the next readout clock pulse, so that it begins a new count as a new pixel is provided by the difference detector 42. . In case the normal period between the next read clock pulses is not sufficient time to sequentially address the memory means 51 and then reset the binary run length counter 52, the difference is stored in the controller 33. It will be appreciated that the next readout clock pulse may be delayed until a black pixel appears at the output of detector 42.

Similarly, the unterminated run of white (low (“0”) logic level) pixels appearing at the output of the differential modulator 31 is converted into a suitable address code and the pre-allocated end of・
When reading out a line message code, the binary pixel counter 53 is e.g.
6, and is cleared or reset at the end of the active region of each scan cycle in response to the end of scan line signal provided by controller 33, and at the passive region of each scan cycle in response to a read clock pulse provided by controller 33. will be increased. Furthermore, a gate 58 connected between the output of the binary pixel counter 53 and the output of the address bus 56 is normally left open and reads the binary pixel counter 53 from the memory means 51 until an unterminated white run is detected. Separate.
However, the detection operation is predictive based on the assumption that each scan line ends in one or more white pixels. In particular, a decoder 59 is provided for detecting the final white run. Decoder 59 is connected between the output of counter 53 and the control input of gate 58 so that when binary pixel counter 53 has accumulated a predetermined binary count equal to the number of pixels assigned to each scan line, The gate 58 is always closed. For example, when there are 1728 pixels per scan line, decoder 59 is selected to register binary pixel counter 53.
Closes gate 58 in response to a binary equal to a count of 1101100 0000.

Unterminated white runs of differentially modulated or non-modulated pixels are
It is recalled that it is preferably represented by another end-of-line message code. Therefore, to obtain an address code that distinguishes between the two, the bits provided by the binary pixel counter 53 are added with the logic level at which the modulated or non-modulated pixel was provided by the separate differential modulator 31. Replenished by bits. As shown, additional or supplementary bits can be added to the line
is preferably derived from the output of counter 44, and is typically derived from the output of binary pixel counter 53.
is organized at the input of gate 58 in parallel with a bit specifying the binary count to be accumulated by . The 11 bit binary count of binary pixel counter 53 is sufficient to represent the binary equivalent of a predicted allocation of 1728 pixels per scan line. Therefore, additional bits can be added to form a 12-bit address code without exceeding the 12-bit capacity of address bus 56.

The construction of the memory means 51 will be described below, with the additional bit preferably occupying one of the most significant bit positions of the end-of-line address code, which means that the scanning of differentially modulated or non-modulated pixels The address code (0110 1100
0000) means there is a potential conflict. Therefore, to avoid this conflict, there is a code converter 60 with built-in delay connected between the gate 58 and the address bus 56 to ensure that the bits do not conflict with the end-of-line address code.・Sequence (i.e. 0110 1110 0000 and 01111
1100 0000) and delaying the provision of end-of-line address codes for a period sufficient to allow run-length address codes to be processed preferentially. As mentioned above, complete 1
11 bits are required to represent a run length of up to 1728 pixels in a scan line, and the additional bits are
Used to indicate whether any encoded run is a run of unmodulated pixels or a run of differentially modulated pixels, allowing the decoder to reconstruct the original data. . As previously mentioned, this additional bit is followed by a run length code that is 11 bits long, so that the end-of-line message from counter 53 is
The need to distinguish between a code (e.g., a binary representation of a count of 1728) and a white run code (e.g., which also has a binary value of 1728) that terminates in a full scan line length of black from run length counter 52. There is. For this purpose, code converter 60 converts the binary output count of counter 53 into a binary number (i.e., a "non-conflicting bit sequence") with a value greater than 1728, which is reset whenever it reaches a count of 1728), thereby eliminating a potential conflict.

Referring to the memory means 51, it is noted that it is arranged to extract variable length data from fixed length data bytes or words. This feature is generally applicable to storing variable-length data in and extracting such data from word-oriented memory, so it is not necessary to disclose the broader concept while only describing a specific application. This means that Of course, applications of special interest here include the storage and playback of run-length message codes from which compressed video signals are formed, individual message bits and end-of-line message codes.

Focusing on this application, run-length messages for compressed video signals from fixed-length data words under the control of fixed-length control words.
It can be seen that there is a stripper circuit 61 for extracting the code, individual message bits and end-of-line message code. Data words and control words are transferred to first and second word-oriented memory banks 62 by address codes generated in response to black-terminating pixel sequences and unterminated white runs. 63 and 64,6
5, respectively. Stripper circuit 61 therefore includes each such sequence and run with predetermined data and control words. The data word contains a message code or bits representing a particular black-terminated pixel sequence or an unterminated white run, and the control word is a data word that determines whether relevant bits are between non-relevant bits. Stripper circuit 61 is thus able to extract the message code or bit from the data word.

In particular, the run length message code,
Individual message bits and end-of-line message codes are included in individual data words. As shown, a set of read-only memory (ROM) memory banks 62 and 63
and stores these data at another predetermined address or memory location. The data word length is selected to be at least the longest message code, and each data word is determined by any bits (i.e., message code or message bits) included to simply obtain the selected word length. • Organized to lead bits (ie, bits with low (“0”) logic level). Additionally, since the memory location of the data word is selected based on the address code, any message code, i.e., containing the message bits of a given black-terminating pixel sequence or end-terminating white run, can be selected based on the address code. Data words are selectively read from memory banks 62, 63 in response to address codes generated as a result of a particular sequence or run.

There are as many control words as data words to differentiate between the associated and filler bits of the data words. That is, the control word enables stripper circuit 61 to separate relevant bits of the data word from unrelated filler bits. Filler bits are added to data words to make them a constant bit length. Each data word has a special correspondence with a control word, so the number of control words is equal to the number of data words. Each control word is stored at an address or memory location in the other set of memory banks 64 and 65 selected such that each control word is associated with a respective one of the data words by sharing a common address code. Ru. Each control word therefore serves to distinguish between relevant and unrelated bits in its corresponding data word. For example, one way such a distinction may be performed is to have high (“1”) and low (“0”) logic levels at corresponding positions of relevant and non-relevant bits of corresponding data words, respectively. Each control word is selected.

In operation, address codes generated in response to black terminating pixel sequences and unterminated white runs are stored in parallel in first and second memories.
Each of the banks 62, 63 and 64, 65 is fed sequentially so that the next set of corresponding data and control words are sequentially read out in parallel and fed in parallel to the stripper circuit 61. Stripper circuit 61 then extracts the run length message code, individual message bits and end of line message code from the data word in accordance with the control word. In this way, compressed video signals are configured in series. When performing this function, the stripper circuit 61 is suitably constructed from a gated parallel-in/series-output shift register or equivalent (not shown) and can be selectively selected under the control of a control word. The associated bits of the data word are serially shifted out in response to read clock pulses output from controller 33 through gates (not shown) which are energized and deenergized.

To ensure the required memory capacity in memory banks 62, 63 and 64, 65, a block length multiple plus run length remainder code format encodes black-terminated white runs in delta modulated and non-modulated pixels. It is used to make The features of this format are as shown in FIG. That is,
A white run ending in black exceeding a given block length is represented by a block length multiple code d plus a run length remainder code e if the run is not an integer multiple of the block length. In other words, the block length multiple plus run length remainder code format eliminates the need to have separate data and control words for each predicted black-terminating white run length. Make it.

Address bus 56 is divided to encode white runs terminated in black according to the block length multiple plus run length remainder code format.
A first branch 56a directs the upper bits of the 12-bit address code to memory banks 62 and 64.
This results in a second branch 56b leading to the lower bits of the address code. The data words and control words of the block length multiple code are stored in memory banks 62 and 64, respectively, as previously described;
and is read. Similarly, memory banks 63 and 65 are used to provide data and control words, respectively, for the run length remainder code. The sequence of block length multiple and run length remainder codes is accomplished by delaying the reading of data and control words relative to one of these codes. For example, by including means (shown at 66 and 67) for delaying the readout of the data and control words for the run length remainder code, the stripper circuit 61 may
Before starting on the length remainder code e , the necessary block length multiple code d is first extracted.

The actual block length shown in the example is 32 pixels long. In this example, each 12-bit address
The seven most significant bits of the code are fed in parallel to memory banks 62 and 64 to provide a block length that is an integer multiple of 32 (i.e., the sum of one or more of the binary digit values 32, 64, 128, 256, 512, and 1024). Drive multiples. The remainder or least significant five bits of each address code are provided in parallel to memory banks 63 and 65 to drive the run length remainder code. A final note of this embodiment is that the address code obtained in response to an unfinished white run causes memory banks 62 and 64, respectively, to be used for storing data and control words. An end-of-line message code is obtained from these data words and control words. Similarly, the specific address code generated in response to an unfinished black pixel is the data address code for each message bit.
commands and control words to be stored in memory banks 63 and 65, respectively.

The present invention has described truncated run-length encoding by specifying a modular variable length code type.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a digital facsimile system in which the data compression device of the present invention can be used quite effectively, and FIG. 2 is a basic diagram of a typical raster input scanner for the system shown in FIG. 3 is a more detailed functional block diagram of a digital compressor constructed in accordance with the present invention, and FIG. 4 is a simplified encoding diagram illustrating the operation of the encoder shown in FIG. It is a diagram. 11...Video data processing system, 12...Digital data compressor, 13...Transmission terminal device,
14... Receiving end not equipped, 15... Communication line, 16
...Input scanner, 17...Analog-to-digital converter, 18,22...Bahua, 19,21...
Digital modem, 23...Digital expander,
24...Raster output scanner, 31...Differential modulator, 32...Run length encoder, 33...Controller, 42...Difference detector, 41...Shift register means, 43...And... Gate, 44...
Line counter, 45, 46, 47...Shift register, 48...Ring counter, 49
...Inverter, 51...Memory means, 52...
Binary run length counter, 53...
Binary pixel counter, 55, 58...gate, 56...address bus, 57...black level detector, 59...decoder, 60...code converter, 61...stripper circuit, 62, 63, 6
4,65...memory bank, 66,67...delay.

Claims (1)

[Scope of Claims] 1. A method for compressing a binary video signal having a predetermined number of serial pixels for each of a plurality of consecutive scanning lines and including white and black pixels of opposite logic levels, comprising: The method includes: converting pixels of some scan lines of the plurality of scan lines to a differentially modulated format and retaining pixels of other scan lines of the plurality of scan lines that are not differentially modulated. , then count the pixels contained in the pixel sequence in the scan line ending in black so as to obtain a count according to the corresponding run length, and then count the pixels contained in the pixel sequence in the scan line ending in black, according to the block length multiple plus run length remainder code format, terminating in said black. converting the count according to the run length into a corresponding block length multiple code, run length remainder code and individual message bits to represent the pixel sequence running in the scan line, so as to obtain the count of running pixels in the scan line; counting the pixels of successive scan lines of the plurality of scan lines; whenever the pixel count for modulated pixels and non-modulated pixels of a scan line each reaches the predetermined number; a message code and another end-of-line message code; A data compression method characterized in that it consists of steps of editing into a serial data stream. 2. A data compression device for compressing a binary signal in a format having a predetermined number of serial pixels for each of a plurality of consecutive scan lines having white and black pixels at opposite logic levels, wherein the data compression device comprises: pixels of several scan lines of the plurality of scan lines are converted into modulated pixels, and the modulated pixels have a modulus of 2 between the converted pixel and a spatially corresponding pixel of an adjacent scan line. differential modulation means for representing a difference; and a control signal for periodically inactivating the differential modulation means, thereby causing the modulation means to operate on other unmodulated scan lines of the plurality of scan lines. Line counter means for providing unmodulated pixels, a plurality of block length multiple codes, a plurality of run length remainder codes, and two different end-of-line message codes at different predetermined addresses.
memory means for storing codes and individual message bits; and memory means coupled between said modulating means and said memory means for storing a black pixel of each of said block length multiple code, run length remainder code and individual message bits. a run length for providing an address code in accordance with the run length to said memory means in response to said sequence for reading from said memory means a suitable representation of a pixel sequence within a terminating scan line; encoding means; means for counting said pixels to provide a predetermined signal for distinguishing said plurality of scan lines from each other; and means connected to said pixel counter means and said line counter means for modulating and decoding said scan lines. means for providing an address code to selectively read each of the end-of-line message codes from the memory means at the end of each of the modulated pixels; Data compression device. 3. In the data compression device according to claim 2, each of the address codes is composed of a predetermined number of bits, and some of the bits are stored in the block length multiple message code and the end address code from the memory means. - used for selectively reading out of line message codes, and other said bits being used for selectively reading said run length remainder message codes and individual message bits from said memory means; A data compression device characterized in that: 4. In the data compression device according to claim 2, the block length multiple message code, run length remainder message code, end of line message code, and individual message bits have variable lengths. , and stored in said memory means in discrete fixed length data words, and data strip means extracts said message code and said message code from said data words selectively read from said memory means in response to said address code. A data compression device, characterized in that it is connected to said memory means for extracting said message bits. 5. In the data compression device according to claim 4, each of the address codes is composed of a predetermined number of bits of a progressively increasing binary digit value, and the block length multiple code is an integer of a predetermined binary power. a data word representing a multiple and containing said block length multiple code is an address selected to be accessed by a bit of said address code that is of a value equal to and greater than said predetermined power. a data word stored in said memory means, wherein said run length remainder code represents a fractional multiple of said binary power, and said data word containing said run length remainder code is of a smaller order value than said power; Data compression apparatus, characterized in that the data is stored in said memory means at addresses selected to be accessed by said bits of said address code. 6. In the data compression device according to claim 2, the differential modulation means is connected to serial input parallel output multistage shift register means for serially accumulating the pixels, and the shift register means. clock means for providing readout clock pulses to shift spatially corresponding pixels of the next adjacent pair of scan lines from said shift register means in parallel; and a modulus 2 difference between the pair of binary input signals. difference detection means for generating a binary output signal representative of the difference detection means; circuit means for supplying one pixel of each of said scan line pairs to a first input of said difference detection means; gating means for gating the other part of the pixels of the pair of scanning lines with respect to the input; and a gating means connected between the line counter means and the control input of the gating means, for detecting the scanning line of the modulated pixel by the difference detecting means. means for selectively energizing and deenergizing the gating means responsive to the control signal to energize to provide and deenergize to provide a scan line of unmodulated pixels; A data compression device characterized by: 7. A data compression device according to claim 6, wherein the run length encoder includes a run length counter that accumulates a binary count, and between the run length counter and the memory means. normally open gate means connected to said run length counter means for clearing said run length counter for each of said scan lines; and reset means connected to said run length counter means for clearing said run length counter for each of said scan lines; - means for connecting said clock means to said run length counter means for incrementing said count by one for each pair of pixels that are turned out; black level detection means for providing other control signals in response to each black modulated pixel and each black non-modulated pixel provided thereby; said level detection means, said normally open gate means and said run length counter; asynchronously and sequentially closing said normally open gate means connected to said memory means to address said memory means, and then closing said run length pixel sequence in preparation for another black-terminating intra-scanline pixel sequence. and control means responsive to said other control signal by clearing a counter. 8. In the data compression device according to claim 7, the pixel counting means includes a pixel counter that accumulates another binary count, a reset means that is connected to the pixel counter and clears it synchronously, and a scanning means responsive to said readout clock pulse to increment said pixel counter in accordance with said other said counts representative of running pixels in a line, and for reading said end-of-line message code. Said means for reading out an address code is connected between said pixel counter and said memory means, said gate means being connected between said line counter means and said other said gate means. means for increasing said pixel count with said control signal; and means connected between said pixel counter means and said other said gate means to cause said memory means to increment said pixel count whenever said pixel count reaches a predetermined number of said pixels. and decoding means for closing the gate means so as to address the data. 9. In the data compression device according to claim 2, the run-length encoding means for encoding a run of pixels is configured such that when the run is not an integral multiple of the block length, the run-length encoding means encodes a run of pixels at least within a predetermined block length. Equal runs with block length multiple code plus
It must conform to the given pattern according to the block length multiple plus run length remainder code format so that shorter runs are represented by run length remainder codes and run length remainder codes only. A data compression device featuring: 10 In the data compression device according to claim 9, the binary video signal includes a predetermined number of pixels for each of a plurality of consecutive scanning lines, and the given pattern includes one or more pixels between the scanning lines. A data compression device characterized in that it is a white pixel column followed by a single black pixel and a white run terminated in black. 11. The data compression device according to claim 9, wherein the raster scanning means operates periodically to actively scan the target copy in one direction;
It then passively flies back in the opposite direction and further serially accumulates the pixels generated when the scanning means scans in the one direction and stores the pixels generated when the scanning means flies back in the opposite direction. A data compression device comprising shift register means for supplying encoding means. 12. The data compression apparatus of claim 2, wherein the memory means stores a plurality of fixed length data words and the same number of fixed length control words, each one of the data words being associated with each control word. first and second parallel memory banks, respectively, for storing each data bit at an address selected to store the data bit and any additional filler bits needed to obtain the fixed length; each said control word selected to identify filler bits of said data word from said words and data; said memory means being connected to said memory means for storing said selected one of said data words and said control word; addressing means for serially addressing the first and second said memory banks in parallel and serially reading from said first and second memory banks respectively; The above data
and output means for extracting associated data bits from a selected data word in response to a control word associated with the word. 13. A data compression apparatus as claimed in claim 12, wherein said data word is arranged to have an associated data bit preceding a filler bit. 14. The data compression device of claim 13, wherein the data word and the control word are of equal length. 15. The data compression apparatus of claim 13, wherein at least certain data bits of said data word define a run length message code, and said addressing means is configured to A data compression device characterized in that it includes first counter means for generating address codes for reading said data words and their associated control words from said first and second said memory banks, respectively. 16. The data compression apparatus of claim 14, wherein associated bits of at least other of said data bits define an end-of-line message code, and further said addressing means defines an end-of-line message code. and second counter means for generating an address code for selectively reading a control word associated therewith from the first and second said memory banks, respectively.