JPS62285277A - Digital data arranging system - Google Patents

Abstract

PURPOSE:To facilitate the detection of a synchronizing signal by using the combination of special signal patterns for the synchronizing signal succeeding to an ID signal even if the ID signal is changed in coding the signal pattern of the ID signal (address information) by the variable word length coding system. CONSTITUTION:In using the variable word length code system for coding a signal as an optional signal pattern of an optional length connecting plural ID signals and a signal pattern for the head part of the synchronizing signal succeeding thereto, even if the location of the data split in the coding differs, the combination of specific patterns is used so as not to change the coded pattern of the synchronizing signal. For example, even if the section of data of a 1st ID signal 5 and a 2nd signal 6 is changed, the combination of special pattern signals is used for the signal of the head of synchronizing signals 351, 352 and a GAP 39 so as not to change the pattern of the coded synchronizing signal by the variable word length coding system. Thus, the coded pattern for the synchronizing signal is identical and the synchronizing signal of the coded pattern is detected easily.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention provides an ID signal (address information) for each sector in a digital data recording medium, such as an optical disk, which requires compact density recording. This invention relates to a digital data arrangement method related to (information), and in particular to a digital data arrangement method for making it possible to read ID signals (address information) with high reliability. The address information (ID signal) for each sector that is preformatted on the recording medium can be done by recording the ID signal once per sector, as in the case of preformatted magnetic recording media. However, as recording density has gradually increased in recent years, the magazine [National Technical Report J'6Z] published by Matsushita Electric Industrial Co., Ltd.
, 29, A 5 (1983) pp. 88-99.
Page (NαtionaL TgchnicaLRepor
t Vol, 29, A 50Ct, +983
8B-99), it is sometimes necessary to record a plurality of ID signals in the preformat portion of one sector.

In other words, although the recording density has increased (・, the error rate when reading data has also increased, and if an ID signal is recorded only once, that is, only one, an error occurs while reading that ID signal). This increases the probability that the ID signal will be unreadable or will be read incorrectly and remain as is.Therefore, even if cylinder density recording is performed, error correction and detection codes are used to ensure that the ID signal can be read with high reliability. In addition to just reading it, the ID signal itself should be recorded multiple times, that is, multiple times, so that any one of the ID signals can be read to reduce the probability of misreading.

However, no consideration has been given to the problems that occur when these ID signals are recorded multiple times and are recorded in accordance with the variable word length encoding method.

This problem will be explained step by step below.

[Problem that the invention seeks to solve]

First, as an example of a variable word length code when data words are encoded and recorded according to the variable word length encoding method,
2-7 RLL (RurLLanqth Lim1t
ed) The case of using codes will be explained.

This means that one bit of data is decomposed into two digits, and a particular data word is divided into two digits, as shown in Table 1 below.
-7 It is encoded and recorded in an RLL code pattern. That is, the 2-bit data word "10"
For example, this is a 4-bit code pattern "010
Recorded as 0J.

The following is as shown in Table 1.

Table 1 Now, as a conventional example, the data pattern shown in Figure 2 (α) (
Consider a case where a pattern including two ID signals arranged with a pattern area of arbitrary length interposed between them is encoded using a 2-7RLL code.

In FIG. 2, the portion to the left from the broken line 21 [000J indicates the end of the previous ID signal, and the portion to the right from the broken line 22 ``+0000J indicates the beginning of the next ID signal (
In other words, the pattern from ++z to z++J between the broken lines 21 and 22 constitutes a pattern area that connects the previous ID signal and the subsequent ID signal. Assume that the number is pi and the number is an even number.

Due to the circuit configuration, these signal patterns are often treated as a unit of 2 to the power of 2, particularly 8 bits (1 byte).

Now, the pattern data as shown in Fig. 2(a) is shown in Table 1.
This is seen as a collection of data words and converted into a 2-7 RLL code, which is shown as a modulation pattern in FIG. 2(A).

In other words, in the data pattern of FIG. 2 (α), there are three O's lined up up to the broken MA21, so from Table 1, this can be determined from the modulation pattern of rooo+ooJ of the 2-7RLL code as the data word of ooOJ. encoded.

Next, since there are ``11'' data words between the dashed line 21 and the dashed-dotted line 23, this is encoded as a modulation pattern of ``100OJ''.
This repetition continues until.

Furthermore, the distance between the dashed line 24 and the broken line 22 is the same as above.
1" pattern, so the same pattern is repeated.

Next, the data words after the broken line 22 are divided into two data words: "10" at the broken line 251 and "000" after that, and are encoded into the modulation patterns of "OI 00 J and roootooJ" according to Table 1. In the 2-7 RLL encoding method, a data pattern is viewed as a collection of data words, and encoding is performed in which the code length can be different for each data word.

Next, consider a case where the contents of the ID signal, for example, the track address, sector address, and data patterns of error correction and detection codes related to these, have changed.

Figure 2 (cl) is an ID that has come to take a pattern different from the ID signal shown in Figure 2 (α) due to such reasoning.
Show signal. The ID signal shown in Figure 2 (Cl) is shown in Figure 2 (
The parts that have changed compared to the ID signal shown in α) are indicated by the broken line 2.
It is the 5th bit of the 3 data bits before 1,
All that happens is that [0OOJ has changed to [oo+J]. The subsequent cross-turn area from broken line 21 to broken line 22 is a fixed pattern that connects the previous ID signal and the subsequent ID signal, and after the broken line 22 is the starting part of the subsequent ID signal, Since it is a synchronization signal,
This also does not change and is a fixed pattern.

Here, the data pattern of Fig. 2<C) is changed as above,
If we consider the case where data words are viewed as a collection and encoded with reference to Table 1 above, first of all, if we assume that the data patterns are delimited as data words by broken i2+, then "oool" will be obtained. , since there is no data word with such a pattern in Table 1, next dot chain?
If l'-oo++J is used as a delimiter with fM26, this exists in Table 1 as a data word, so Table 1
encoded according to the modulation pattern l'-0000+00
It becomes 0J.

The next delimiter is the delimiter "11" defined by the dashed-dotted line 27 when viewed from the data words in Table 1, and this is encoded. After that, all the bits continue up to the dashed-dotted line 50, so they are encoded as a data word of 2 bits separated by ``11''.

In this case, 11 bits of the delimiter 22b of the synchronization signal pattern as the beginning of the rear ID signal have been violated. In other words, the "1" between the broken line 22 and the chain +11iI30 is originally a bit belonging to the synchronization signal, but this bit has been removed. and dash-dotted line 60
From now on, the data pattern of "000" will be separated as a data word, and its modulation pattern will be "0OO0" according to Table 1.
It becomes 100J.

When the modulation pattern encoded in this manner shown in FIG. 2 (, i+) is compared with the modulation pattern shown in FIG. This means that it is difficult to detect the synchronization signal that constitutes the beginning of the fi and ID signals on the encoded modulation pattern as shown in Figure 2 (dl), which is extremely inconvenient. .

As is already clear, the reason for this inconvenience is that the rear ID signals were not separated correctly as the contents of the ID signals changed, and this is the problem.

Therefore, in the present invention, the problem to be solved is to ensure that no matter how the contents of the ID signal change, the next ID signal following the ID signal is correctly separated without being disturbed.

An object of the present invention is to encode a plurality of ID signals using a variable word length encoding method, and when recording and reproducing them on a disk-shaped recording medium, even if the data pattern in the previous ID signal changes, the next ID signal is The signal at the front is to be detectable on a pattern encoded by variable word length encoding.

[Means for solving problems]

The above purpose is to provide an arbitrary signal pattern of arbitrary length that connects ID signals of orders, and a signal pattern at the beginning of a synchronization signal that follows it, when encoding using a variable word length coding method. This is achieved by using a combination of specific patterns so that the coded pattern of the synchronization signal does not change even if the data division position of the synchronization signal differs.

[Effect]

When the signal pattern of the ID signal is encoded using the variable word length encoding method, even if the ID signal changes, the subsequent synchronization signal uses a special combination of signal patterns as described above. As a result, the encoded signal pattern does not change, and synchronization signal detection is facilitated.

〔Example〕

The present invention will be explained in detail below, but first, the third
A signal arrangement on a recording medium to which the present invention is implemented will be explained with reference to the drawings.

In FIG. 3 (α), 41 is a disk-shaped recording medium, 42
is a recording track, and (A) is a sector configuration diagram of the recording track 42, where one sector is an index area 52 in which address information necessary for accessing recorded data is recorded.
1 and a data area 322 for recording data.

Furthermore, the index area 621 is further subdivided as shown in FIG. 3(c). Here, we will use a signal with the following configuration as an example of a signal that is subdivided and recorded in the index area.
think.

That is, in FIG. 3 (1), 33 is a sector mark indicating the beginning of the sector, 34 is a VFO signal for synchronizing with the clock for strobe the following data during reproduction, and 551 and 352 are the following data. Synchronization signal for bit synchronization with, 361,”,6
2 is the track address where your sector is located, 3
71 and 372 are the own sector addresses, 381 and 382 are CRC codes for checking whether there are errors in the track address or sector address.Here, a CRC code for detection only is used, but a code that can be corrected may also be used. good.

In this example, the first ID signal 5 is composed of 35+, 561, 371, and 381, and 35+, 561, 371, and 381 constitute the first ID signal 5.
2°562, 372.382 constitutes the second ID signal 6. That is, here, a case is shown in which the same ID signal is recorded twice in the index area of one sector.

39 is a gap as a pattern area interposed between these two ID signals. The gear knob 59 is included in consideration of burst errors or error propagation in variable word length encoding systems.

The number of ID signals to be recorded may be increased (1.degree.) Next, the state in which the signals recorded in this index area are reproduced by the data reproducing device will be explained using FIG. 4.

FIG. 4 is a block diagram showing an example of an apparatus for reproducing data from an optical disc. In Figure 4, 41
1. A disk-shaped recording medium, here an optical disk.

50 is an optical pickup, 43 is an amplifier, 44 is a data slicer, 45 is a PLL oscillation circuit, and 46 is a variable word length encoding/decoding circuit. Here, a composite circuit compatible with the 2-7 RLL encoding method is taken as an example. . 47 is a sector mark detection circuit, 48 is a gate signal generation circuit, 49 is a synchronization signal detection circuit, 51 is a CRC check circuit, and 52 is a CRC
A check signal output terminal, 53 a serial data output terminal, and 54 a sector mark detection clock input terminal.

First, the index area signal shown in FIG. 3(1) reproduced from the optical disc 41 by the optical pick amplifier 50 is amplified by the unmixing amplifier 43, and then converted from an analog signal to a digital signal by the data slice circuit 44. The signals digitized in this manner are transmitted to the PLL oscillation circuit 45.2-7, the RLL code decoding circuit 46, and the synchronization signal detection circuit 49. Sector mark detection circuit 4
Sent to 7.

Here, the first signal that enters from the beginning as the reproduction signal of the index area is first detected by the sector mark detection circuit 47. A signal for synchronizing with the sector mark at this time is generated by a clock input from the clock input terminal 54. Here, even if there is a slight jitter, it should be possible to detect it.

The sector mark detection signal detected here is input to the gate signal generation circuit 48. Here, a gate signal is generated to apply a gate so that the synchronization signal can be detected only in the vicinity where the synchronization signal exists and is spaced apart from the sector mark at a constant interval. In other words, this is to prevent a non-synchronizing signal from being mistakenly detected as a synchronizing signal in a place where no synchronizing signal should exist.

A VFO signal is input next to the sector mark, and a clock signal synchronized with this signal is generated in a PLL oscillation circuit 45 and sent to a 2-7RLL code decoding circuit 46 and a synchronization signal detection circuit 49, respectively.

The next synchronizing signal is detected by the synchronizing signal detection circuit 49, but at this time the detection is performed using the same pattern encoded by the 2-7 RLL code.

The detection signal detected from this synchronization signal detection circuit 49 is 2
-7 RLL code code combining circuit 46 determines the decoding timing for decoding signals after the synchronization signal, and decodes the 2-7 RLL code of ID signals such as track addresses, sector addresses, CRC codes, etc.

The incompletely decoded ID signal enters the CRC check circuit 51, where it is checked to see if there are any errors in the ID signal.The result is output from the check signal output terminal 52, and at the same time the decoded ID signal is is output from output terminal 55 and processed by another system (not shown).

Although the ID signal is reproduced in this manner, errors are likely to occur if high-density signals are recorded and reproduced, such as when recording and reproducing on a medium such as an optical disk.

Therefore, as shown in Fig. 3 (c), a method of recording multiple ID signals and recording them at intervals to deal with burst errors. Whether it is the second signal 6 or not, if the synchronization signal (SYN 351, 352) forming the beginning of the ID signal is not detected correctly, each subsequent signal will also be correct and follow the 2-7RLL coding system. Decoding becomes impossible, and the ID signal becomes unreadable.

In this playback method, as mentioned above, the synchronization signal is 2-7A.
The synchronization signal is detected on a pattern encoded by the LL code, but if the data pattern located before the synchronization signal changes, the delimiter pattern will differ when encoding by the 2-7RLL encoding method. , 2-7
As previously explained, the synchronization signal pattern encoded by the ALL encoding method may be different, making it impossible to detect it.

To prevent this, even if the data delimiter changes, 2
-7 GAP59 and synchronization signal 5 in which the pattern of the synchronization signal encoded by the ALL encoding method does not change.
The signals at the beginning of numbers 51 and 352 are combined with signals of special patterns.

This embodiment will be explained using FIG.

The same numbers in FIG. 1 and FIG. 2 have the same meaning.

In FIG. 1, the dashed line 21'! But the last part of the CRC code in the first ID signal, from broken line 21 to broken 1lil122
The area up to the broken line 22 is the gap, and the area after the broken line 22 is the synchronization signal in the second ID signal or the front part of the synchronization signal.First, let us consider the encoding of the data signal in FIG. 1(A). Please refer to Table 1 for the data of "000° up to the broken line 21".
When encoded as shown up to broken line 21 in B), ooo+oo
". Also, from the broken line 21 to the dashed line 231, "11°
The pattern will be ``+000°'' to my colleagues.

This data pattern continues up to the broken line 22. Broken line 2
After 2, the pattern of 100] Bi is “0OOOIOQO”
CB> in FIG. 1.

Next, consider the case of an ID signal of another sector. This changes the track address and sector address, which causes the CRC
Assume that the code pattern has also changed and the last 3 bits become "00 bits" as shown by the broken line 21 in <C> of FIG. 1. Encoding by the 2-7 RLL coding system in this case will be considered below.

In the data pattern of Fig. 1(C), first, the single-point chain M
A26′! It is delimited and encoded. In other words, “00
The data pattern of 11° is “00001000°” and the first
U (D> is encoded into the pattern shown by the dashed dotted line 26'1. Since all the subsequent patterns are "1 degree", they are "separated and encoded with a 1 bit pattern" +o
This pattern continues up to the dashed-dotted line 29. After that, the pattern of °10" from the dashed-dotted line 29 to the dashed-dotted line 6! ends at @011" from the dashed-dotted line 61 to the dashed-dotted line 62. It becomes one delimiter, and each is encoded as @01000.”001
000'''.

By changing the pattern to be encoded as described above, the encoded pattern on the synchronization signal remains the same even if the delimitation of encoding by the 2-7 ALL encoding method on the fixed pattern that continues thereafter is different. Therefore, the synchronization signal can be easily detected on the encoded pattern.

Note that even if the GAP 39 part is used as a VFO signal, the phase of the pattern differs only from the dashed-dotted line 21 to the dashed-dotted line 22'1 of the patterns in FIGS. 1(B) and (D). There is no problem as it serves as a signal.

〔Effect of the invention〕

According to the present invention, since the synchronization signal pattern becomes a fixed pattern even on a pattern encoded by the variable word length encoding method, the synchronization signal can be easily detected on this encoded pattern.

Further, even if an error occurs and the PLL is disconnected, the PLL0 pull-in is performed again using the VFO pattern before the synchronization signal, and the next synchronization signal can be detected correctly.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an encoding pattern as an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a conventional encoding conversion pattern, and FIG. 3 is a recording medium to which the present invention is applied. FIG. 4 is an explanatory diagram of the above signal arrangement, and FIG. 4 is a block diagram showing the system configuration when reproducing the recording medium shown in FIG. 3. 21・・・・・・・・・・・・End of ID signal 22・・・・・・・・・・・・Beginning of next ID signal 5.6・・・・・・・・・...ID signal 351...Synchronization signal 59...Gap area agent Patent attorney Katsuo Ogawa 1 [

Claims (1)

[Claims] 1. Divide an information track on a recording medium into sector areas,
In each sector area, at least two ID signals consisting of a synchronization signal, a track address signal, a sector address signal, etc. are provided, each as a first and second ID signal, with a pattern area of arbitrary length interposed between them. Furthermore, all the ID signals and patterns are recorded in an information format encoded for each specific segmented bit pattern according to the variable word length encoding method, so that they can be reproduced later. In the digital data arrangement method on the recording medium, no matter what kind of bit arrangement the entire bit arrangement (pattern area of arbitrary length and first ID signal) preceding the second ID signal takes, the entire bit arrangement is changed to the variable bit arrangement. In accordance with the word length encoding method, when the signal pattern is divided by a specific divided bit pattern, the signal pattern constituting the pattern area is precisely divided and the second ID signal is not affected by the division. and a digital data arrangement method characterized in that a combination of specific patterns is used as a synchronization signal pattern as the head of a second ID signal that follows. 2. In the digital data array system according to claim 1, the signal pattern constituting the arbitrary length pattern area is used to synchronize with data when decoding a variable word length encoded signal. A digital data arrangement method characterized by using a suitable signal pattern.