JPS62282480A - Formation of electrode - Google Patents

Formation of electrode

Info

Publication number
JPS62282480A
JPS62282480A JP12547086A JP12547086A JPS62282480A JP S62282480 A JPS62282480 A JP S62282480A JP 12547086 A JP12547086 A JP 12547086A JP 12547086 A JP12547086 A JP 12547086A JP S62282480 A JPS62282480 A JP S62282480A
Authority
JP
Japan
Prior art keywords
platinum
film
layer
mask
stripe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12547086A
Other languages
Japanese (ja)
Inventor
Tatsuya Sasaki
達也 佐々木
Motohiko Inai
稲井 基彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12547086A priority Critical patent/JPS62282480A/en
Publication of JPS62282480A publication Critical patent/JPS62282480A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a platinum stripe electrode to enable continuous oscillation at a high temperature, and to enhance the characteristic of an element by a method wherein after a part of a dierectric film is removed in a stripe type to expose the surface of a semiconductor, platinum is evaporated on the whole surface, alloying treatment is performed, and then a platinum layer on the dielectric film is removed. CONSTITUTION:A clad layer 6, an active layer 5, a clad layer 4 and a cap layer 3 are grown in order on a substrate 7, an SiO2 oxide film is laminated thereon, and photolithography is performed using a mask to form stripe type grooves. The wafer and ZnP2, ZnAs2, InP are put in a quartz ampoule to be sealed in a vacuum, Zn is diffused up to the middle of the p-type clad layer 4, and the SiO2 film is removed. An SiO2 film is adhered again, stripe type grooves of two pieces are formed performing positioning of a mask, and mesa etching is performed using a Br2-CH3OH solution. Then an SiO2 film 10 is adhered again, positioning of a mask is performed, and stripes are formed. Pt is evaporated thereon, and after alloying is performed, the platinum layer on the dielectric film is removed.

Description

【発明の詳細な説明】 λ発明の詳細な説明 (産業上の利用分野) 本発明は、半導体素子の電極形成方法に関する。[Detailed description of the invention] Detailed description of the λ invention (Industrial application field) The present invention relates to a method for forming electrodes of semiconductor devices.

(従来の技術) 半導体レーザには、高出力、低電力動作、高温動作−長
寿命といった特性向上をはかるために、数々の構造が発
明されてきた。
(Prior Art) A number of structures have been invented for semiconductor lasers in order to improve their characteristics such as high output, low power operation, high temperature operation and long life.

可視域の赤色光を発振する可視光半導体レーザにおいて
は、発振波長を短くしていくことが最大の目標である。
In visible light semiconductor lasers that emit red light in the visible range, the greatest goal is to shorten the oscillation wavelength.

しかし、発振波長が短い半導体レーザでは、活性層のバ
ンドギャップエネルギーが大きくなるからクラッド層と
のバンドギャップ差が充分にとっにくくなり、また活性
層組成が間接遷移領域に近付くから、発光効率が低下し
、注入キャリアが活性領域から漏れやすくなる。このた
め発振しきい値電流が増加し、室温で連続発根させるこ
とが困難になるという問題があった。そのためしきい値
電流Ithやしきい値電流密度J’thの低減、熱抵抗
Rth  の低減を可能とする素子構造が検討されてき
た。
However, in semiconductor lasers with short oscillation wavelengths, the bandgap energy of the active layer increases, making it difficult to create a sufficient bandgap difference with the cladding layer, and the composition of the active layer approaches the indirect transition region, resulting in a decrease in luminous efficiency. However, the injected carriers tend to leak from the active region. For this reason, there was a problem in that the oscillation threshold current increased, making it difficult to cause continuous rooting at room temperature. Therefore, device structures that make it possible to reduce the threshold current Ith, the threshold current density J'th, and the thermal resistance Rth have been studied.

従来可視光半導体レーザの構造としてはS10゜酸化膜
ストライプ、Zn拡散プレーナストライプが開発初期か
ら試作されている。これらは、製作が比較的簡単で発振
波長などを知りたい場合には効果的である。しかし1.
これらの従来構造では、ストライプ内部に狭窄された電
流がクラッド層内で広がってIthが増加すると、さら
に前者の構造では熱伝導率の悪い酸化膜に遣ぎられて熱
の放散が悪く連続動作する温度が高くならない。また両
側に逆バイアス領域を作って電流を閉じ込める埋め込み
構造やセルフ・アライン構造でも漏れ電流の存在は無視
できず、また2回以上結晶成長を行なわなければならな
いという問題があった。
Conventional structures of visible light semiconductor lasers include S10° oxide film stripes and Zn diffused planar stripes, which have been prototyped since the early stages of development. These are relatively easy to manufacture and are effective when it is desired to know the oscillation wavelength, etc. But 1.
In these conventional structures, when the current constricted inside the stripe spreads within the cladding layer and Ith increases, in the former structure, the current is transferred to an oxide film with poor thermal conductivity, resulting in poor heat dissipation and continuous operation. The temperature does not get high. Furthermore, even in a buried structure or a self-aligned structure in which reverse bias regions are created on both sides to confine current, the existence of leakage current cannot be ignored, and there is also the problem that crystal growth must be performed more than once.

これらの問題を解決するためにメサストライプ構造レー
ザが開発された。第2図にその実際例を示す。n −G
a As (11Pll、4/勺aAs組成グレーデツ
ト基板7上に成長したInGaAsP/InGaPダブ
ルへテロ構造結晶にまず幅7μmKZnをPクラッド層
4まで選択拡散してZn拡散領域2を形成する。次にA
uZn層10全10し合金化する。そして中央の幅が5
μm1その両側に5μmずつのストライのあるマスクに
よって2本のストライプをあけてAu Zn層を除去し
、さらに臭素−メタノール溶液でエクチングし、メサ溝
20廖21を形成する。
A mesa stripe structure laser was developed to solve these problems. Figure 2 shows an actual example. n-G
a As (11 Pll, 4/A
The entire uZn layer 10 is alloyed. and the width in the center is 5
The Au-Zn layer is removed by making two stripes using a mask with stripes of 5 μm on both sides of the 1 μm layer, and then etched with a bromine-methanol solution to form a mesa groove 20 squares 21.

溝20.21は活性層5に到達しないようにする。The grooves 20, 21 should not reach the active layer 5.

フォトレジストを除去して、その上にTi/Au電極1
を蒸着する。そして基板研磨後、n側電極8を蒸着し、
メサストライプ構造を完成する。
The photoresist is removed and a Ti/Au electrode 1 is placed on top of it.
Deposit. After polishing the substrate, the n-side electrode 8 is deposited,
Complete the mesa stripe structure.

この構造の特徴は、溝20.21を形成して電流の流れ
る領域を限定し、さらにZn拡散、 AuZn合金によ
って効果を強めていることと、溝20゜21に熱伝導率
の低い酸化膜をつけずに、合金化していない金属が積層
されていることによって、ストライプ幅が狭くてしきい
値電流が低くてもしきい値電流密度が増加せず、熱放散
の良好な素子を実現できることである。この構造によっ
てしきい値電流密度4.5 kg/attで室温連続発
振を達成しり(ジャパニーズ・ジャーナル・オブ・アプ
ライド・フィツクス、  (Japanese  J、
 Appl。
The characteristics of this structure are that the grooves 20 and 21 are formed to limit the area where the current flows, and that the effect is further strengthened by Zn diffusion and AuZn alloy, and that the grooves 20 and 21 are formed with an oxide film with low thermal conductivity. By layering unalloyed metals without adding metal, the threshold current density does not increase even if the stripe width is narrow and the threshold current is low, making it possible to realize an element with good heat dissipation. . With this structure, we achieved continuous oscillation at room temperature with a threshold current density of 4.5 kg/att (Japanese Journal of Applied Fixtures, (Japanese J,
Appl.

Phys 、’l 4、L 163.1985))。Phys, 'l 4, L 163.1985)).

(発明が解決しようとする問題点) 第2図に示した構造は電流を効果的に狭窄し、活性層5
で発生する熱を効率よく外部に放散させることができ、
室温連続発振を可能にしたわけだが、その寿命は素子特
性を測定できる程度のわずかなものであり、光出力もt
〜2 mWにすぎない。
(Problems to be Solved by the Invention) The structure shown in FIG. 2 effectively constricts the current, and the active layer 5
The heat generated in can be efficiently dissipated to the outside,
This made continuous oscillation possible at room temperature, but its lifetime was short enough to measure device characteristics, and the optical output was also short.
~2 mW.

こうした劣化の大きな原因として、まだ熱抵抗が高いこ
との他に、電極での劣化が考えられる。P側オーミクク
電極とし【はAuZn合金を使用してきたが、AuZn
は接触抵抗が高く、オーミックコンタクトが比較的とり
(<<、また大電流を流した時にショートしやすい傾向
がある。ヒートシンクとしてはAu/Snを用いており
、高温動作時にSnが結晶中に侵入する劣化(ソルダー
・!イグレーショy m S M )が生じるおそれも
ある。こうした電極の劣化は’ri/Au+Cr/Au
でも観察されており、半導体レーザの安定性を高めるう
えでの大きな問題となっている。
In addition to the still high thermal resistance, a major cause of this deterioration is considered to be deterioration at the electrodes. [AuZn alloy has been used as the P-side ohmic electrode, but AuZn
has a high contact resistance and relatively good ohmic contact (<<, and tends to short-circuit when a large current is applied. Au/Sn is used as the heat sink, and during high-temperature operation, Sn may enter the crystal. There is also a risk that deterioration (solder ! migration y m S M ) may occur.Such deterioration of the electrode
This phenomenon has also been observed in semiconductor lasers, and is a major problem in improving the stability of semiconductor lasers.

(問題点を解決するための手段) 前述の問題点を解決するために本発明が提供する手段は
、半導体表面に誘電体膜を形成し、この′□誘電体膜の
一部をストライプ状に除いて前記半導体、表面を露出さ
せた後に、全体に白金(Pi)を蒸着し、この白金に合
金化処理を施し、次に前記誘電体膜上の前記白金層を剥
離することによって白金ストライプ電′糎を形成する方
法である。
(Means for Solving the Problems) The present invention provides means for solving the above-mentioned problems by forming a dielectric film on the semiconductor surface and forming a part of this dielectric film into stripes. After exposing the surface of the semiconductor, platinum (Pi) is deposited on the entire surface, alloying treatment is performed on the platinum, and then the platinum layer on the dielectric film is peeled off to form a platinum stripe electrode. 'This is a method of forming starch.

・(作用) ptは半導体との接触抵抗が低(、A u Z n e
Cr/Aue Ti/Au  等と比べて高温、大電流
時にも安定で劣化の度合が少ない。またpt上の電極(
特KAu)の結晶中への侵入を防とする働きがある。T
t/pt、/Au  はP側電極として使用されている
が、本発明では選択的(ストライプ状)KPtを蒸着し
て合金化し、他の領域は合金化せず金属が積層されてい
るだけなので電流が狭窄される。つまり、第2図に示し
た従来の構造において電極をptに変えた効果が加わっ
てくる。
・(Function) PT has low contact resistance with semiconductors (, A u Z n e
Compared to Cr/Au, Ti/Au, etc., it is stable even at high temperatures and large currents and has a low degree of deterioration. Also, the electrode on pt (
It has the function of preventing special KAu) from entering the crystal. T
t/pt, /Au is used as the P-side electrode, but in the present invention, KPt is selectively deposited (in stripes) and alloyed, and the other regions are not alloyed and are simply layered with metal. The current is constricted. In other words, the effect of changing the electrodes to PT in the conventional structure shown in FIG. 2 is added.

(実施例) 以下、第1図に示した実施例について説明する。(Example) The embodiment shown in FIG. 1 will be described below.

第1図(a)が完成図で、第2図のAuZn1iLOが
白金Pt 2に変わつ℃いる。ただし、製作法は以下に
示すように異なる部分がある。
Figure 1(a) is a completed diagram, in which AuZn1iLO in Figure 2 is replaced with platinum Pt2. However, there are some differences in the manufacturing method as shown below.

ハイドライド−vPE法により、n形Ga As QP
 aa / Ga入入組組成グレーデツド基板7上IC
8eドープn形InGaPクラツド GaAsP活性層5、ZnドープPPinGaPクラッ
ド層4、ノンドープエnGaAsPキャップ層3を屓次
に成長させる。欠1/C3iO,酸化膜を熱C’VD法
により2000人はど積層し、7μm幅のマスクを用い
てネガレジストによるフォトリソグラフィーを行ない、
ストライプ溝を形成する。ウェハおよびZnPl # 
 ZnAs!e InPを石英アンプル中に真空封正し
、熱拡散によってZnt−P形りラッド層4の中間まで
拡散し、810.をはがず。再びS10.膜をつけ、幅
5μm1間隔5μmの2本のストライプ溝をマスク合わ
せであけ、Br、−CH30H溶液でメサエッチングす
る。一般的には溝20.11は活性層5には到達しない
よう(するが、後に述べるように到達してもよい。
n-type GaAs QP by hydride-vPE method
IC on aa/Ga composition graded substrate 7
An 8e-doped n-type InGaP clad GaAsP active layer 5, a Zn-doped PPinGaP cladding layer 4, and an undoped n-type InGaAsP cap layer 3 are successively grown. A 1/C3iO, oxide film was laminated by 2,000 layers using a thermal C'VD method, and photolithography was performed using a negative resist using a 7 μm wide mask.
Form stripe grooves. Wafer and ZnPl#
ZnAs! e InP is vacuum sealed in a quartz ampoule and diffused to the middle of the Znt-P shaped rad layer 4 by thermal diffusion, 810. It should be removed. S10 again. A film is applied, two stripe grooves each having a width of 5 μm and an interval of 5 μm are opened by mask alignment, and mesa etching is performed using a Br, -CH30H solution. In general, the grooves 20.11 do not reach the active layer 5 (although they may do so, as will be described later).

そしてS10.をはがしたところを示すのが第1図(1
))である。
And S10. Figure 1 (1
)).

次に再びSin!膜10全10、今度は4μm@のマス
クを合わせてストライプを形成する(第1図(C))。
Next, Sin! The entire film 10 is now aligned with a 4 μm mask to form stripes (FIG. 1(C)).

その上にPちをスパッタ蒸着し、460℃でアロイする
(第1図(d))。中央のストライプのキャップ層3上
にPt2が積層している部分は合金化されるから接着力
が強いが回りの部分はSin、膜10上にあるから、接
着性は非常に悪い。そこで上から粘着テープttt密着
させた後はがすと、Sin!膜10上のPt 2は容易
にはがれ、中央部のみが残る(第1図(e))。
P is sputter-deposited thereon and alloyed at 460° C. (FIG. 1(d)). The part where Pt2 is laminated on the cap layer 3 of the central stripe is alloyed and has strong adhesive strength, but the surrounding parts are on the Sin film 10 and have very poor adhesive strength. Then, after applying adhesive tape ttt from above and peeling it off, Sin! The Pt 2 on the film 10 is easily peeled off, leaving only the central portion (FIG. 1(e)).

S io、膜10を除去しく第1図(f))、上に’r
i、”pt  Lを蒸着した後に基板7を100μm程
度に研磨し、n側に入uGaNi/Au 8を蒸着、ア
ロイ(350″C)し、最後に融着用にP側にTi/P
t/Auを蒸着して完成する(第1図(g)および(a
))。
To remove the membrane 10 (FIG. 1(f)),
After depositing "pt L", the substrate 7 is polished to about 100 μm, and uGaNi/Au 8 is deposited and alloyed (350"C) on the n side, and finally Ti/P is deposited on the p side for fusion.
t/Au is completed by vapor deposition (Fig. 1 (g) and (a)
)).

なお、Sin、酸化膜10を除去しないで、その上にT
i/Pt/Au電礪1を積層すれば、電流狭窄が完全に
近いほど効果的に行なえ、メサエッチングを活性層5の
下まで行なっても電流がショートしないから、しきい値
電流Ith をより低ぐできる。ただし、この場合は熱
伝導率の低いSin。
Note that without removing the Sin and oxide film 10, T is formed on it.
If the i/Pt/Au capacitor 1 is laminated, the current confinement can be more effectively achieved, and even if mesa etching is performed below the active layer 5, the current will not be short-circuited, so that the threshold current Ith can be further increased. Can be lowered. However, in this case, Sin has a low thermal conductivity.

膜によって熱放散が悪化するため、連続動作、高温動作
時に問題が生じるので、Sin、膜の厚さは約500〜
600人と薄くする必要がある。
Since the heat dissipation is worsened by the film, which causes problems during continuous operation and high temperature operation, the thickness of the film should be approximately 500~
We need to reduce the number to 600 people.

この方法により半導体レーザを製作し、素子特性を測定
したが、従来観察された電極部分での劣化は改善され、
良好な特性を得ることができた。
A semiconductor laser was manufactured using this method and the device characteristics were measured, but the deterioration at the electrode part that was observed conventionally was improved.
Good characteristics could be obtained.

(発明の効果) 以上のように従来用いられてきたAuZn を用いたオ
ーミック電極の代わりに白金を使用することにより、よ
り高温での連続発振が可能になり、素子特性が向上した
。誘電体膜上の白金を選択的に除去する方法の採用によ
り、容易かつ効果的に電1ストライプを形成することb
′−できる。
(Effects of the Invention) As described above, by using platinum instead of the conventionally used ohmic electrode using AuZn, continuous oscillation at a higher temperature is possible, and device characteristics are improved. By adopting a method of selectively removing platinum on a dielectric film, it is possible to easily and effectively form an electric stripe b.
′-I can.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による白金電極を採用したInGaAs
P/InGaP可視光半導体レーザの断面図であり、本
図(a)が完成図、本図(b)〜(g)までが製作工程
を途中(メサエッチングした後)から順に示している。 第2図は従来用いられたAuZntliを用いた同様の
半導体レーザの断面図である。 代理人 弁理士 本  庄 伸  介 ptt場 第1図(a) 第1図(1))     第1図(e)第1図忙)  
  第1図(f) 第1図(d)     第1図(9) 第2図
Figure 1 shows an InGaAs film using a platinum electrode according to the present invention.
1 is a cross-sectional view of a P/InGaP visible light semiconductor laser, in which figure (a) is a completed view, and figures (b) to (g) sequentially show the manufacturing process from the middle (after mesa etching). FIG. 2 is a cross-sectional view of a similar semiconductor laser using conventionally used AuZntli. Agent Patent Attorney Nobu Honjo PTT Figure 1 (a) Figure 1 (1)) Figure 1 (e) Figure 1 Busy)
Figure 1 (f) Figure 1 (d) Figure 1 (9) Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体表面に誘電体膜を形成し、この誘電体膜の一部を
ストライプ状に除いて前記半導体表面を露出させた後に
、全体に白金を蒸着し、この白金に合金化処理を施し、
次に前記誘電体膜上の前記白金層を剥離することによつ
て白金ストライプ電極を形成する電極形成方法。
A dielectric film is formed on a semiconductor surface, a part of this dielectric film is removed in a striped form to expose the semiconductor surface, and then platinum is deposited on the entire surface, and this platinum is subjected to an alloying treatment,
Next, a platinum stripe electrode is formed by peeling off the platinum layer on the dielectric film.
JP12547086A 1986-05-30 1986-05-30 Formation of electrode Pending JPS62282480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12547086A JPS62282480A (en) 1986-05-30 1986-05-30 Formation of electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12547086A JPS62282480A (en) 1986-05-30 1986-05-30 Formation of electrode

Publications (1)

Publication Number Publication Date
JPS62282480A true JPS62282480A (en) 1987-12-08

Family

ID=14910881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12547086A Pending JPS62282480A (en) 1986-05-30 1986-05-30 Formation of electrode

Country Status (1)

Country Link
JP (1) JPS62282480A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219674A (en) * 1990-01-25 1991-09-27 Toshiba Corp Electrode structure and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03219674A (en) * 1990-01-25 1991-09-27 Toshiba Corp Electrode structure and manufacturing method of semiconductor device

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