JPS62281631A - Detecting circuit for synchronizing signal of data transmission equipment - Google Patents

Abstract

PURPOSE:To continuously detect the synchronizing signals over a wide sampling frequency band by producing the synchronizing signal when the charging voltage exceeds a prescribed level, and at the same time, controlling the output current to equalize the peak level of the charging voltage and the reference signal level when the peak level of charging voltage is shifted from the reference signal level. CONSTITUTION:The charging circuits 9 and 11 repeat charging for each supply of an edge extracting signal of the digital data signal. The charging voltage levels of both circuits 9 and 11 are detected to know that these voltage levels exceed the fixed value only with a preamble part having a longer inverting interval than the data part. Then the synchronizing signal is produced only when the preamble part is detected after the charging voltage level exceeds the fixed value. While the charging current is controlled so that the peak level of the charging voltage is equal to the reference signal level. Thus the charging current is controlled when the sampling frequency has a changed and therefore the charging voltage level is fixed when the preamble part is detected. As a result, the synchronizing signals can be continuously detected over a wide sampling frequency band.

Description

[Detailed description of the invention] Detailed description of the invention The present invention will be explained in the following order.

A. Field of industrial application B. Summary of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example G1. Configuration of synchronizing signal detection circuit ( Figure 1) Detection operation of the G2 synchronization signal detection circuit (Figure 2) Specific circuit example of the G3 synchronization signal detection circuit (Figure 3) The present invention relates to a synchronization signal detection circuit for a data transmission device that detects synchronization signals of digital audio signals of various sampling frequencies according to the transmission method.

B. Summary of the Invention The present invention provides an edge extraction method for extracting edges of digital data signals in a synchronization signal detection circuit of a data transmission device that detects synchronization signals of digital audio signals of various sampling frequencies using a transmission system of a digital audio interface, for example. an extraction circuit, a charging circuit that repeatedly charges the output current of the current generating circuit every time the edge extraction signal of the edge extraction circuit is supplied, a level detection circuit that detects the level of the charging voltage of this charging circuit, and this charging circuit. It consists of a peak level detection circuit that detects the peak level of the charging voltage of the circuit, and a comparison means that compares the detection signal of this peak level detection circuit with a reference signal, and detects when the charging voltage has exceeded a predetermined value. When the detection circuit detects it, a synchronizing signal is created, and when the comparison means detects that the peak peak of the charging voltage deviates from the reference signal level, it generates a synchronizing signal so that it is equal to the reference signal level.
By controlling the output current of the current generating circuit, the synchronizing signal can be detected continuously over a wide sampling frequency band with a simple configuration.

C. Conventional Technology One type of digital transmission system is the transmission system of a digital audio interface. This digital audio interface supports L channel with one digital cable.

L channel transmits two data. For this reason, the fourth
As shown in Figure A, a time division multiplex transmission method is used in which L channel data and R channel data are alternately transmitted and received.

For example, a compact disc has a sampling frequency of 44. For I KHz, L channel,
44,100 pieces of data are transmitted per second for each R channel, and 88,200 pieces of data are transmitted for both channels in total. The length of one channel data section (word) is 11.3
It is 4 microseconds. Further, one word is composed of 32 bits, and the bits are divided as shown in FIG. 4B in this case. That is, in the figure, the first 4 bits are a 5YNC portion for synchronization, into which a preamble to be described later is inserted. Next is the part where audio data is entered, and there is a 24-bit field.

However, most audio data, such as compact discs, are 16 bits, and currently only the last 16 bits are used. The last 4 bits are a control part that carries information accompanying data such as emphasis 0N10F'F and subcode.

The data assembled in this way has a so-called bi-phase mark (bip
A modulation called "hase mark" is applied.

However, the synchronization signal part is an exception.
-mble) is fitted with a special pattern. In the preamble, inversion correspondence by data is ignored, and the duration of the beinpel is longer than in any other part.

Here, the conversion of the digital audio signal transmitted by the transmission method of the digital audio interface as shown in FIG. 4 into an analog signal (hereinafter referred to as D/A
There is a 5D/A converter that supports multiple sampling frequencies. That is, there are various sampling frequencies for digital audio signals.For example, a BS that receives 8HF waves from a broadcasting satellite
Tuner A mode is 32KHz, CDROM (
r)-if voice information is 37.8KHz, CD (=r
y Bakto Disk) is 44.1KHz.

The B mode of the BS tuner and digital audio tape recorder is 43KHz. A D/A converter that is compatible with various sampling frequencies, such as the ing.

FIG. 5 shows an example of a conventional synchronization signal detection circuit of this type, and in the figure, (1) indicates the input terminal of the digital audio signal transmitted by the transmission method of the digital audio interface as shown in FIG. The digital audio signal obtained at this input terminal (1) is supplied to an edge extraction circuit (3) of a sampling frequency reproduction device (2). This edge extraction circuit (3) detects, for example, inversion of data in a digital audio signal, and supplies a predetermined signal to a 2FS reproduction circuit (4) which reproduces twice the sampling frequency Fs every time the data is inverted. 2
The Fs regeneration circuit +41 operates a range switching circuit (5) which will be described later every time a predetermined signal is supplied from the edge extraction circuit (3).
) is a pulse signal with a constant width set by the signal from P
Supplied to the LL circuit (6). This pulse signal width can be switched to, for example, three types of ranges, is always in one of the ranges, and changes in order, for example, each time a signal is supplied from the range switching circuit (5). The PLL circuit (6) supplies a clock signal to the data demodulation circuit (7) based on the pulse signal from the 2F3 regeneration circuit (4). In addition, the digital audio signal obtained at the input terminal (1) is supplied to the data demodulation circuit (7), and the digital audio signal in the format of the digital audio interface is converted into a normal 16-bit digital audio signal in synchronization with the clock signal from the PLL circuit (tG). Demodulates signals such as data. Here, if this demodulation is not performed normally, a discharge signal is supplied to the range switching circuit (5). Every time this discharge signal is supplied, the range switching circuit (5) supplies a range switching signal to the 2F3 regeneration circuit (4), and switches until a proper range is reached and normal demodulation becomes possible. Then, the demodulated signal demodulated by the data demodulation circuit 111 (71) is supplied to the output terminal (81), and the signal is supplied from the output terminal (8) to a digital-to-analog conversion circuit, etc. to generate an analog audio signal. .

Here, this sampling frequency reproduction device! An example of a pulse signal reproduced by (2) is shown in FIG.

First, the data supplied to the input terminal (1) is as shown in FIG. Then, the edge extraction circuit (3) emits a pulse signal every time this data is inverted, as shown in FIG. 6B.Then, the 2Fs regeneration circuit (4) As shown in FIG. 6C, each time a pulse signal is supplied from the edge extraction circuit (3), a pulse signal with a width of 3102 times the minimum inverted data determined by the S/pulling frequency is emitted.Emitting a signal in this way As a result, a period C occurs in which no pulse signal is output in the preamble section a2.
The PLL circuit (6) detects the period C during which l' is absent, and supplies a clock signal based on this detection to the data demodulation circuit (7)K. By the way, P during the period C when no pulse signal is output
Detection by the LL circuit (6) vi is possible even if this period C is narrower than the width of the minimum inversion data a1, so even if the width of the minimum inversion data a1 changes due to fluctuations in the sampling frequency, the detection can be performed near the set sampling frequency. It is possible for the PLL circuit (6) to generate a clock signal within a certain range of . That is, as shown in FIGS. 7A, B, and C, when three ranges of the 2F'S reproducing circuit (4) are provided as low V/range, mid V range, and high range, for example, a low range car 30 KHz to 36 kHz. It is possible to demodulate data having a sampling frequency of 9 KHz, a mid range of 35 KHz to 43 KHz, and a high range of 40.7 KHz to 50 KHz. In addition,
The reason why the bands of each range partially overlap is because operation may become unstable near the edge of the winter band.

In this way, by providing three ranges in the 2F3 regeneration circuit (4) and switching them so that normal demodulation is possible,
For example, it is possible to demodulate data with a wide sampling frequency of 30KHz to 5QKHz.

However, in the configuration described above, when demodulating digital audio signals with sampling frequencies near the overlapping ends of each range, it is necessary to
It was not determined whether the Fs regeneration circuit (4) would operate or not, but it was determined by the state at that time. That is, for example, 36.9
Demodulation of a signal with a sampling frequency slightly lower than KHz can be performed in both the low range and mid range B ranges in the example in Figure 7, so the range when the operation starts is the Lorentz range. When the mode is A or midrange B, both can be demodulated, so the data demodulation circuit (7) to the range switching circuit +51
However, considering the stability of operation, it is preferable to use mid range B, and operation in low range A is at the end of the band. Therefore, there is a possibility that the demodulation is unstable and good demodulation cannot be performed, and if the demodulation condition deteriorates considerably, the low range A will switch to the mid range B, resulting in sound interruptions and the like.

For this reason, the present applicant previously proposed a synchronization signal detection circuit that can effectively switch between each range (Japanese Patent Application No. 60-268).
．． No. 654). This synchronization signal detection circuit counts the frequency of the output signal of the 2Fs regeneration circuit, supplies this count signal to the range switching logic determining circuit, and controls the range switching circuit based on the sampling frequency detected by the range switching logic determining circuit. This is how it was done. By controlling the switching in this way, for example, as shown in FIG.
The sampling frequency is 36 KH regardless of the demodulation state.
For swords below 1, switch to low range person, and 3
When the frequency is 6KHz or more and 42KH2 or less, use Midrange B.
When the frequency is 42 kHz or higher, the frequency is switched to zero range C, so that it does not operate at the edge of each range. By operating in this manner, even within overlapping frequency bands, the range is always switched to the optimum range.

D. Problems to be Solved by the Invention However, the configuration for switching a plurality of ranges as described above has the disadvantage that a range switching logic determination circuit consisting of a logic circuit is required, making the circuit configuration complicated.

Further, adjusting the set values of the range switching points of this logic circuit (for example, the above-mentioned 36 KHz and 4.4 KHz) required a special jig and was time-consuming. Furthermore, if the reproduced sampling frequency changes continuously and this change exceeds the range switching point, the range will change during playback and the PLL circuit will temporarily become unlocked, causing sound dropouts and other problems. There was a drawback that this occurred.

In view of these points, it is an object of the present invention to provide a synchronization signal detection circuit that can reproduce sampling frequencies over a wide frequency band with a simple configuration.

E. Means for Solving the Problems The synchronous signal detection circuit of the data transmission device of the present invention includes, for example, as shown in FIG. Circuit (3
) is supplied to the current generating circuit αC.
A charging circuit (9) that repeatedly charges the output current of αυ and this charging port 1% t91. (Level detection circuit α2 that detects the level of 1110 light tt pressure, charging circuit (9),
It consists of a peak peak detection circuit (141) that detects the peak peak of the charging voltage of αυ, and comparing means us and ue that compare the detection signal of this peak peak detection circuit I with a reference signal, and when the optical 11L voltage exceeds a predetermined value. When the novel detection circuit 2 detects this, it generates a synchronizing signal, and also compares means U to detect that the peak voltage of the charging voltage is deviated from the reference signal level.

1 so that it is equal to the reference signal level when uQ is detected! The output current of the current generating circuit α1 is controlled.

F Effect According to the synchronization signal detection circuit of the data transmission device of the present invention,
A charging circuit that repeats charging every time an edge extraction signal of a digital data signal is supplied [91, (By detecting a charging voltage level of 1υ, the charging voltage level is increased only in the preamble section, which has a longer inversion interval than the data section. It is a simple configuration that creates a synchronization signal when the light'w!L'lt pressure Vpel exceeds a certain value and the synchronization signal is created only when the preamble section is detected. .Also,
By controlling the charging current so that the peak level of the charging voltage is equal to the reference signal level, the charging current is controlled when the sampling frequency changes.
The optical I voltage level at the time of detecting the preamplifier portion is approximately constant, and the synchronization signal can be detected continuously over a wide sampling frequency band.

G. Embodiment Hereinafter, one embodiment of the synchronization signal detection circuit of the data transmission device of the present invention will be described with reference to FIGS. 1 to 3. In FIGS. 1 to 3, parts corresponding to those in FIGS. 4 to 7 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

01 Configuration of synchronous signal detection circuit The synchronous signal detection circuit of this example is configured as shown in Fig. 1. In Fig. 1, (9) indicates a capacitor, and this capacitor (9) It charges the current supplied from the generation circuit (l) and also charges the current supplied from the discharge circuit (l).
Charge 1 by 11! This prevents the current from being discharged. This discharge circuit Uυ discharges the charging current of the capacitor (9) every time the edge extraction circuit (3) extracts the edges of the digital audio signal obtained at the input terminal (1). Then, this capacitor (9) is connected to the input terminal of the Schmitt circuit (1z), and when this Schmitt circuit α2 detects that the charging voltage value of the capacitor (9) exceeds a predetermined reference value, the Schmitt circuit σ2 From the waveform shaping circuit (13
A pulse signal is output to the synchronization signal output terminal (13a) via the synchronization signal output terminal (13a). Furthermore, the capacitor (9) is connected to the detection signal input terminal of the peak level detector I, the peak value of the charging voltage of the capacitor (9) is detected by the peak level detector I, and this peak value detection signal is sent to the comparator. (supplied to the comparison signal input terminal of Le. Also, a reference voltage signal of constant V pel obtained from the reference voltage source (19) is supplied to the reference signal input terminal of comparator IIQ. The voltage signal and the peak value detection signal of the capacitor (9) are compared, and a comparison signal is supplied to the charging current generating circuit αl.

The optical current generating circuit σI controls the charging current supplied to the capacitor (9) by supplying this comparison signal. That is,
When the voltage value of the peak value detection signal is higher than the reference voltage signal, the charging current is controlled to be low. When the voltage value of the peak value detection signal is lower than the reference voltage signal, the charging current is controlled to be low. When the reference voltage signal and the peak value detection signal are the same, the element i at that time
Maintain the flow.

G2 Detection operation of the synchronization signal detection circuit The synchronization signal detection circuit of this example is configured as described above, so that it detects a synchronization signal from the digital audio signal obtained at the input terminal (1) and outputs this signal to the output terminal (13a). It should be able to output a sync signal.

That is, for example, if the digital audio signal supplied to the input terminal (1) is as shown in Figure 2, the edge extraction circuit (
The edge-extracted signal obtained by step 3) becomes a signal in which a short pulse signal P is obtained each time the signal is inverted, as shown in FIG. 2B. By supplying the pulse signal P of this edge extraction signal to the discharge circuit aυ, the capacitor (
9) Discharge the charging 'wL current. Therefore, the charging voltage value of the capacitor (9) becomes Ov every time the pulse signal P of the edge extraction signal is supplied, as shown in FIG. 2C, and remains at a constant ratio until the next pulse signal P is supplied. To increase.

Here, as mentioned above, the format of the digital audio signal is such that the inversion interval of the preamble part is longer than other parts.For example, as shown in FIG. Assuming that the interval ratio with T3 is T1:T2:'r3=1:2:3, the peak value of the light w'r!1 pressure of the capacitor (9) is the maximum inverted data T2 during normal data. The peak value of ■ never exceeds 1.

However, in the preamble section T3, the maximum inverted data T
Since the interval is longer than 2, charging is performed for a longer time than at the time of maximum inversion data T2, and a beater value v2 approximately 1.5 times larger than the above-mentioned value 1 is obtained. Therefore, Schmitt circuit c
If the reference value v3 of 3 is set so that Vl<V3<V2, the charging voltage value at the preamble section will be 3.
Until V2 is exceeded, the output signal of the Schmitt circuit σ2 becomes a Weinpel "H" pulse signal as shown in the second diagram. However, in this example, ■3 is set between ■1 and v2. In this way, a Beinpel "H" pulse signal is obtained only in the preamble section, and this pulse signal is shaped into a pulse signal of an appropriate length by the waveform shaping circuit q, and is sent to the output terminal as a synchronizing signal. (13a). The synchronization signal obtained at this output terminal (13a) is supplied to a PLL circuit (not shown) and used as a signal for data demodulation.

Next, a case where the sampling frequency of the digital audio signal supplied to the input terminal (11) changes will be explained. For example, if this sampling frequency is
When the frequency changes to a lower frequency than in the example shown in the figure, the ratio T1:T2:T3=1:2:3 of the minimum inversion data Tl, the maximum inversion data T2, and the preamble section T3 does not change, but the respective The length of the section becomes longer. For this reason, the charging time of the capacitor (9) in the preamplifier section is also long (and when charging with the same current value, the above-mentioned peak value 2 is exceeded as shown by the broken line in Fig. 2C. Then, the peak bell detector α1 always detects this peak value,
The comparator tte compares this detected peak value with the reference voltage source (1
Since the voltage is compared with the reference voltage output by the reference voltage source (19), it is possible to detect whether the voltage value v2 has been exceeded by setting the reference voltage output by the reference voltage source (19) to the above voltage value (2).

Then, when it is detected that the voltage value v2 has been exceeded,
A control signal is supplied to the charging current generating circuit (1G) to reduce the charging current so that the peak value becomes the reference voltage value v2 as shown by the two-dot chain line in FIG. By controlling, even if the sampling frequency is low, a pulse signal as shown in the second diagram above can be obtained.
Synchronization signals can be detected. Moreover, when the sampling frequency becomes high, the result is opposite to when it becomes low.

That is, in this case, the comparator αQ detects the peak voltage as being lower than the reference voltage v2 and increases the light il+ current so that the peak value becomes the reference voltage value ■2, and the synchronization signal cannot be detected. Ru.

As described above, according to the synchronization signal detection circuit of this example, a synchronization signal can be detected even if the sampling frequency changes, and can be detected over a wide sampling frequency band from 2Q KHz to 60 KHz, for example. In addition, since it does not switch between multiple ranges like in the past, there is no need for a logic circuit for switching, which simplifies the circuit configuration, eliminates the need for adjustment, and allows the sampling frequency to exceed the range switching point. The lock of the PLL circuit does not become unlocked midway, unlike in the case of continuous changes.

G3 Specific Circuit Example of Synchronizing Signal Detection Circuit FIG. 3 shows an example of a specific circuit W& configuration of the synchronizing signal detecting circuit shown in FIG. 1. The synchronization signal detection circuit shown in FIG. 3 receives the digital audio signal obtained at the input terminal +11,
The output signal of this edge extraction circuit (3) is supplied to an edge extraction circuit (3) made up of a plurality of Ex-OR circuits EXI to Ex4, a resistor FLl, and a capacitor C1, and the output signal of this edge extraction circuit (3) is sent to a monostable multivibrator αD made up of an IC. supply to. This monostable multivibrator αη is as shown in Figure 2C (
It is connected to a capacitor (9) that is charged in a sawtooth manner,
The charging voltage of this capacitor (9) supplies a pulse signal from the monostable multipipe router aη to the waveform shaping circuit αJ.

This waveform shaping circuit (13) is composed of an IC, a resistor R2, and a capacitor C2, and supplies the output signal of this waveform shaping circuit (131) to an output terminal (13a) as a synchronizing signal.

Further, the peak value of the charging pressure of the capacitor (9) is detected by a peak level detector (141) consisting of a diode D1 and a capacitor C3, and the output signal of this peak level detector
2 and resistor R3.

Then, the power supply voltage is divided by resistor R4 and resistor R5 to obtain a reference voltage.The output signal of reference voltage source 4 is supplied to comparator αe, and the output signal of comparator u61 is
transistor Tr 3 + Tr4 and resistor R6,
A charging current generating circuit (IQ) configured as a current mirror circuit with R7 supplies the charging current to the capacitor (9) via this current mirror circuit.In this way, the charging current of the capacitor (9) The circuit to be controlled is constructed as described above. The circuit shown in the example of FIG. 3 has no elements requiring adjustment and is simple in construction.

Note that the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations may be adopted without departing from the gist of the present invention.

H Effects of the invention According to the synchronization signal detection circuit of the data transmission device of the invention,
There is an advantage that synchronization signals can be detected continuously over a wide sampling frequency range with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the synchronizing signal detection circuit of the data transmission device of the present invention, FIG. 2 is a diagram for explaining the example in FIG. 1, and FIG. 3 is a diagram showing a specific example of the example in FIG. A circuit diagram showing an example of a circuit configuration, FIG. 4 is a diagram for explaining a digital audio interface format, FIG. 5 is a block diagram showing an example of a conventional synchronization signal detection circuit, and FIGS.
The figure is a diagram for explaining the example of Fig. 5. (3) is an edge extraction circuit, (9) is a capacitor, ul is a charging current generation circuit, αυ is a discharge circuit, a2 is a Schmitt circuit, (141 is a peak level detector, (1
9 is a reference voltage source, and 4 is a comparator.

Claims (1)

[Claims] an edge extraction circuit that extracts the edge of a digital data signal; a charging circuit that repeatedly charges the output current of the current generation circuit every time the edge extraction signal of the edge extraction circuit is supplied; and a charging circuit that repeatedly charges the output current of the current generation circuit; A level detection circuit detects the peak level of the charging voltage of the charging circuit, a peak level detection circuit detects the peak level of the charging voltage of the charging circuit, and a comparison means that compares the detection signal of the peak level detection circuit with a reference signal, When the level detecting circuit detects that the level has exceeded a predetermined value, it generates a synchronizing signal, and when the comparing means detects that the peak level of the charging voltage deviates from the reference signal level, it generates the reference signal level. A synchronous signal detection circuit for a data transmission device, characterized in that the output currents of the current generation circuit are controlled so that the output currents are equal to each other.