JPS62280909A - Address signal generating device - Google Patents

Abstract

PURPOSE:To generate an address signal, which is free from the number of gear teeth and frequency division ratio (denotes the frequency division ratio of a first frequency division means) of an FG, by setting the frequency division ratio of a second frequency division means so that the frequency ratio of the output of the first frequency division means to that of the second frequency division means or that of a gate means becomes a positive integer. CONSTITUTION:Where the number of gear teeth in the FG is 5 and the frequency division ratio is 2, the first frequency division means 1 frequency-divides an FG signal SFG by two and the second frequency division means 4 frequency- divides a PG signal SPG by two to generate a division PG signal S'PG. Therefore the frequency ratio of a division signal S'FG to a division PG signal S'PG can be set to a positive integer of 5. When the first division means 1 is reset with the aid of the division PG signal S'PG, the division FG signal S'FG can attain a constant period. A pulse sampling means 2 generates an output SR in such a way that it samples one pulse from the frequency division FG signal S'FG as a base. When said pulse resets an address counter 3 to count frequency division FG signals S'FG, address signal A0-A2, all of which have correspondence to the FG, can be generated.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention Industrial Field of Application The present invention relates to a device having a detector for detecting the rotational frequency of a rotating body, in which a rotational frequency detection signal obtained from the detector is frequency-divided. The present invention relates to an address signal generating device that generates an address signal from a signal.

Conventional technology Cylinder motors and capstan motors, that is, rotating bodies in magnetic recording and reproducing devices, etc., are equipped with a detector, that is, a frequency generator, that detects the rotational frequency in order to control the number of rotations at a constant level.
Hereinafter, FF (denoted as ,) will be used. However, this F
If there is a pitch error in G, the rotating body cannot be controlled to a constant rotation speed, causing rotational fluctuations. Therefore, as a method to reduce this rotational fluctuation, the frequency of the FG multiplied signal obtained from the FC is discriminated, the FG fluctuation pattern in one rotation of the rotating body is stored in a memory such as iRAM or ROM, and the FG fluctuation is determined based on the stored output. There is a correction method that cancels out the pattern. In this case, correct correction cannot be made unless the stored one-rotation variation pattern corresponds to the FG, so it is necessary to make the address of the RAM or ROM correspond to the FG. Therefore, it is necessary to assign addresses to the FC as well, and for this purpose, a rotational position detector (hereinafter referred to as PG) that detects a signal of one pulse per rotation is used. Then, FC signals are counted based on the rotational position detection signal (hereinafter referred to as PG multiplied signal) obtained from this PG, and an address signal is generated and used by an address counter. That is, the address signal generated by the address counter is stored in RAM or ROM.
Correspondence with FG is achieved by using it as an address signal.

3a and 3b are a block diagram and a waveform diagram of a conventional address signal generator. In Figure 3a, 1 is the PG multiplied signal P
Frequency dividing means 2 reset by G and divides the frequency of the FG multiplied signal y; 2 is a pulse extraction for extracting one pulse from the output of the frequency dividing means 1, that is, the divided FG multiplied signal y'e, based on the PG multiplied signal P; Means 3 is an address counter that is reset by the output SR of the pulse extraction means 2 and counts the frequency-divided FG multiplied signal FG. The configuration is such that address signals Ao to person n are obtained from this address counter 3. As a result, it is possible to generate an address signal that corresponds to the above-mentioned FG, and the fluctuation pattern of the FG can be stored in RAM or R.
You can store it in OM and make corrections to cancel it.

Problems to be Solved by the Invention However, in the above configuration, the number of teeth of the FG is set to 6, for example, and the frequency dividing ratio of the frequency dividing means 1 is set to 2, as shown in the waveform diagram of FIG. In this case, the frequency-divided FG-multiplied signal yc can be made into a signal with a constant period, but this frequency-divided FG-multiplied signal yc cannot be used as a signal for controlling the f rotational speed to be completely constant. Therefore, such a frequency division FG multiplication S? - Address signal sent to address counter 3 from 0. There was a problem in that even if ``Mom 1'' was generated, it would be useless. Conventionally, in order to solve this problem, the number of teeth of the FG and the frequency division ratio were set so that the frequency ratio between the frequency-divided FG multiplied signal,' and the PG multiplied signal PG was a positive integer.

In view of this, an object of the present invention is to provide an address signal generating device that is not limited by the number of teeth of the FG and the frequency division ratio.

Means for Solving the Problems The present invention comprises a first frequency dividing means for frequency dividing a rotational frequency detection signal, and a second frequency dividing means for frequency dividing a rotational position detection signal and creating a signal for resetting the first frequency dividing means. a pulse extraction means for extracting the output of the first frequency division means or one pulse of the rotational frequency detection signal based on the output of the second frequency division means; This is an address signal generating device comprising an address counter that generates an address signal by counting the output of the first frequency dividing means.

The present invention also provides a first frequency dividing means for frequency dividing the rotational frequency detection signal, a gate means for gating the rotational position detection signal and creating a signal for resetting the first frequency dividing means, and an output of the gate means. pulse extracting means for extracting one pulse of the output of the first frequency dividing means or the rotational frequency detection signal based on the output of the first frequency dividing means; and counting the output of the first frequency dividing means that is reset based on the output of the pulse extracting means. This is an address signal generating device comprising an address counter that generates an address signal and a gate signal for gating the gate means.

According to the above-described structure, the frequency division ratio of the second frequency division means is adjusted so that the frequency ratio between the output of the first frequency division means and the output of the second frequency division means or the output of the gate means becomes a positive integer. By setting , it is possible to generate an address signal that is not limited by the number of teeth of the FG and the frequency division ratio (referring to the frequency division ratio of the first frequency division means).

Embodiment FIGS. 1a and 1b are a block diagram and a waveform diagram of an address signal generator according to a first embodiment of the present invention. In FIG. 1a, 1 is a first frequency dividing means for dividing the frequency of the FG multiplied signal rc;
2 is a second frequency dividing means that divides the PC signal SPG and creates a signal Spc for resetting the first frequency dividing means 1 (hereinafter referred to as a frequency divided PG multiplication signal), and 2 is a frequency divided PG multiplied signal pc It based on Pulse extracting means extracts one pulse of the frequency-divided FG multiplied signal FG, and reference numeral 3 designates an address counter that is reset by the output SR of the pulse extracting means 2 and counts the frequency-divided FG multiplied signal FG. The address counter 3 is configured to generate address signals person 0 to person n. In the embodiment of the present invention configured as described above, for example, as shown in the waveform diagram of FIG. The frequency of the double signal yc is divided by 2, and the second
Since the frequency division means 4 divides the frequency of the PG multiplied signal PG by two to create the frequency divided PG multiplied signal pc, the frequency ratio of the frequency divided signal SFG and the frequency divided PG multiplied signal pc is set as a positive integer of 5. Therefore, when the first frequency dividing means 1 is reset with the frequency divided PG multiplied signal pc, the frequency divided FG multiplied signal ?'α can be made to have a constant period, and the frequency divided PG multiplied signal pc can be made to have a constant period. The address counter 3 receives the output SR of the pulse extracting means 2 which extracts one pulse from the frequency-divided FG multiplied signal FG based on the signal pc.
By resetting the address counter 3 and counting the frequency-divided FG multiplied signal rG, the address signal Ao corresponding to the FC can be obtained.
, A, , 2 can be generated. In this way, the address signal can be obtained without being restricted at all by the number of teeth of the FC and the frequency division ratio (referring to the frequency division ratio of the first frequency division means 1).

FIGS. 2a and 2b are a block diagram and a waveform diagram of an address signal generating device showing another embodiment of the present invention. In FIG.
Gate means for creating a signal Spce for gating the G multiplication signal pc and resetting the first frequency division means 1 (hereinafter referred to as the frequency division pc multiplication signal), 2 is a frequency division based on the frequency division PG multiplication signal Sp'c'ii- A pulse extracting means 3 extracting one pulse of the FG multiplied signal yc is reset by the output SR of the pulse extracting means 2 and frequency divided by F(.

This is an address counter that counts 5yct signals. Then, the address counter 3 generates an address signal person 0 to person n, and a gate signal SG gates the gate means 2.
occurs. Note that the gate signal SG can be obtained by decoding the count value of the address counter 3. In the second embodiment configured as above, for example, as shown in the waveform diagram of FIG. 2, when the number of teeth of the FG is 5 and the frequency division ratio is 2, The gate means 6 is gated by the gate signal SG created by dividing the frequency of the FG multiplied signal FG by two and decoding the count value 4 by the address counter 3, and the first frequency is divided by the obtained frequency divided PG multiplied signal p'c. By resetting the means 1, a frequency-divided FG multiplied signal y'c having a constant period can be obtained. Therefore, in the address counter 3, address signals 01, 11, 2 corresponding to the FG can be generated as in the first embodiment, and the number of teeth of the FG and the frequency division ratio (the division of the first frequency division means 1) can be generated. It is not restricted at all by the circumferential ratio.

Next, the above 1. In the second embodiment, when the low/con of the address signal, that is, the FG address is moved 7 feet before or after, the pulse extracting means 2 changes the one pulse extracting position of the divided FG multiplied signal F'G to the mode. This can be easily implemented by having a configuration that switches according to a signal (not shown). In addition, as another method of address signal rotation, the address signal, that is, the output large o-An of the address counter 3 is divided into a frequency FG times a signal FG using a latch means.
This can be easily realized by providing a switch means for latching the address counter 3 and selectively switching and outputting either the output of the address counter 3 or the output of the latch means according to the mode signal.

Note that when the address signal Ao-An is not rotated, the pulse extracting means 2 uses the frequency dividing FC,
A configuration may be adopted in which the FC signal syc is used instead of the signal SF'G.

The basic idea of the present invention explained above is to make the frequency ratio of the frequency division F(, signal SFG and the frequency division PG multiplied signal PG a positive integer, and within the range of not deviating from this basic idea) It goes without saying that various configurations are possible.Here, as a special case, in the first embodiment, the second frequency dividing means 4
When setting the frequency division ratio equal to the frequency division ratio of the first frequency division means 1, the decoded value of the counter count value of the gate signal Sc generated by the address counter 3 in the second embodiment is N.
-1 (however, N is the frequency ratio of the FG multiplied signal FG and the PG multiplied signal PG, and corresponds to the number of teeth of the FC), especially when setting the frequency division ratio and decode value to the minimum value. This saves you the trouble of performing calculations.

As described in detail, according to the present invention, the PG double signal pc,
FC, signal SF by the frequency-divided PC multiplied signal P'H
Since the method of resetting the frequency dividing means that divides G is used, the frequency ratio of the frequency-divided FG multiplied signal FG and the frequency-divided PG multiplied signal PG can be set to a positive integer, and thereby the address signal corresponding to FG can be generated. This can be done without being restricted by the number of teeth and frequency division ratio of the FC, and its practical effects are great.

[Brief explanation of drawings]

1A and 1B show a configuration diagram and a waveform diagram of an address signal generating device according to a first embodiment of the present invention, and FIGS. 2A and 2B show a diagram of an address signal generating device according to a second embodiment of the present invention, respectively. FIGS. 3A and 3B are a block diagram and a waveform diagram of a conventional address signal generator, respectively. 1...First frequency dividing means, 2...Pulse extracting means, 3...Address counter, 4...
...Second frequency dividing means, 5...Gate means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3

Claims (10)

[Claims] (1) first frequency dividing means for frequency dividing the rotational frequency detection signal;
a second frequency dividing means for dividing the rotational position detection signal and creating a signal for resetting the first frequency dividing means; It is characterized by comprising a pulse extracting means for extracting one pulse of the rotational frequency detection signal, and an address counter that is reset by the output of the pulse extracting means and generates an address signal by counting the output of the first frequency dividing means. address signal generator. (2) The frequency dividing ratio of the second frequency dividing means is set so that the frequency ratio between the output of the first frequency dividing means and the output of the second frequency dividing means is a positive integer. The address signal generator according to range 1. (3) The address signal generating device according to claim 1, wherein the frequency dividing ratios of the first frequency dividing means and the second frequency dividing means are set to be equal. (4) The address signal according to claim 1, wherein the pulse extracting means switches the pulse extracting position according to the mode signal only when extracting one pulse from the output of the first frequency dividing means. Generator. (5) The pulse extraction means includes a latch means for latching the output of the address counter with the output of the first frequency division means only when one pulse is extracted from the output of the first frequency division means; 2. The address signal generating device according to claim 1, further comprising switch means for selectively switching and outputting one of the outputs of said latch means in accordance with a mode signal. (6) first frequency dividing means for frequency dividing the rotational frequency detection signal;
gating means for gating the rotational position detection signal and creating a signal for resetting the first frequency division means; and an output of the first frequency division means or one pulse of the rotation frequency detection signal based on the output of the gate means. and an address counter that is reset by the output of the pulse extraction means and generates an address signal and a gate signal for gating the gate means by counting the output of the first frequency dividing means. An address signal generator characterized by: (7) The count value of the address counter is set so that the frequency ratio between the output of the first frequency dividing means and the output of the gate means is a positive integer. Address signal generator. (8) The address signal generating device according to claim 6, wherein the count value of the address counter is set equal to the frequency ratio of the rotational frequency detection signal and the rotational position detection signal. (9) The address signal according to claim 6, wherein the pulse extracting means switches the pulse extracting position according to the mode signal only when extracting one pulse from the output of the first frequency dividing means. Generator. (10) The pulse extraction means includes a latch means for latching the output of the address counter by the output of the first frequency division means only when one pulse is extracted from the output of the first frequency division means, and a latch means for latching the output of the address counter with the output of the first frequency division means; 7. The address signal generating device according to claim 6, further comprising switch means for selectively switching and outputting one of the outputs of said latch means in accordance with a mode signal.