JPS62279431A - Input/output emulator - Google Patents

Abstract

PURPOSE:To make an operation program operate in the same system by emulating input/output instruction on a program even when it does not conform to input/output instruction given to a hardware system. CONSTITUTION:When a main processor 1 executes an input output instruction, its execution status signal 2 is analyzed by an interrupt controller 3. Consequently, an interrupt instruction signal 4 to the processor 1 becomes effective immediately, and the interrupt is started to the processor 1. At this time, a port address and output data of input output instruction are stored in an address latch register 6 and a data latch register 8 by a latch signal 5 from the controller 3. Further, operation status of the processor 1 is stored in a status latch register 8, and at the same time, a bus driver 12 is cut off to prevent execution output of input output instruction from sent out to a system bus 11 through the controller 3. Then an emulation program is started and an operation program can be made to operate in the same system.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention is defined as a system in which a main processor executes an I10 instruction given to a loaded program by executing its GLODARUM. This invention relates to an input/output emulator that converts to I10 instructions. .

[Conventional technology]

Conversion of input/output instructions (referred to as engineering instructions) can be easily achieved using a hardware decoder if the only difference is the port address. However, if part or all of the data portion of the I10 instruction is different, it is difficult to convert the I10 instruction using hardware. One method to solve this problem is to arrange a sub-processor and emulate the I10 instruction exclusively, but this method has the disadvantage of complicating the hardware.

[Problem that the invention seeks to solve]

In general, in order to make software developed on different types of computer systems executable, it is necessary to have completely the same hardware or to have different hardware installed in duplicate. In particular, even if the processors of heterogeneous systems are the same, it is inevitable that the control of communication devices and other input/output peripheral devices will be different. At the basic level of hardware operation, this can be seen as a difference in the instructions for peripheral control. On the other hand, when planning to create a series of systems, inheriting the software assets of older models, that is, compatibility at the functional level, is an important factor. However, the functional enhancement of the peripheral control system inevitably creates a difference Ji in control commands. Processor I
If we focus on the 10 instructions, there are the following three problems.

(1) I/l: Difference only in port address (same hardware used) (2) Part of the data part of the r10 instruction is included in another I10 instruction.

(3) All instructions are included in other I10 instructions.

[Means for solving problems]

According to the present invention, registers are provided that hold the operating status of the main processor and the execution information (port address, data) of the I10 instruction, and these registers can be accessed from the main processor. Furthermore, it has an interrupt controller that generates an interrupt to the main processor itself immediately after executing the I10 instruction, and a memory that stores dedicated software (emulator) that operates mainly for processing the interrupt. Emulation is performed by running the emulator and reading the contents of the register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

When the main processor 1 executes the I10 instruction, its execution status signal 2 is analyzed by the interrupt controller 3. As a result, the interrupt command signal 4 to the main processor 1 becomes valid immediately, and the main processor 1 is activated to initiate an interrupt. At this time, the latch signal 5 from the interrupt controller 3 stores the port address and output data (in the case of an output command) as execution information of the pI10 instruction in the address latch reno star 6 and data latch reno star, respectively, and further stores the port address and output data (in the case of an output command) in the address latch reno star 6 and the data latch reno star, respectively. The operation status of is stored in the status register 8. At the same time, the bus driver 12 is cut off by the mask signal 9 from the interrupt controller 3 so that the execution output of the I10 instruction is not sent onto the system bus 11.

When the interrupt processing starts, the emulation program stored in the local memory 13 is activated.

A reference example of the emulation program will be described with reference to its processing sequence shown in FIG.

Read status register 8 for the first time (step S
1) Determine whether the main processor 1 has executed an input or output instruction, read the address register 6 and data renostaph (steps S2 and S3), and if the input instruction is executed, execute the necessary emulation. In step S4), the converted data is used as the read result of the input instruction to rewrite the original read data of the input instruction that was saved on the stack when the interrupt occurred (step S5).

If it is an output command, emulation is simply executed (step S6). Immediately after executing the I10 instruction, the program returns to the operating program.

According to the above sequence, the processor starts operating again from step 7 following the I10 instruction.

〔Effect of the invention〕

As explained above, even if the I10 instruction on the program to be executed does not match the I10 instruction given to the hardware system that runs the program, by emulating the I10 instruction, the operating program will appear to be the same. It has the effect of making the system work.

Moreover, this can be easily realized with a single processor and a minimum of 7-dware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the invention, and FIG. 2 is a flow chart showing an example of an emulation sequence. Patent applicant: NEC Co., Ltd. Representative: Takashi Kusano 1\Ku 1 To 5
<Ku = box or fan + smoker 2 Figure

Claims (1)

[Claims] (1) A register that can hold the operating status of the input/output command of the main processor and execution information of the input/output command, and that can be read from the main processor, and an interrupt to the main processor itself when the input/output command is executed. an interrupt controller that generates a current operating status of the main processor and stores execution information of the input/output command at that time in the register; and based on the interrupt, reads the contents of the register by the interrupt; An input/output emulator comprising emulation execution means for executing emulation of these.