JPS62278605A - Programmable sequence controller - Google Patents

Abstract

PURPOSE:To perform a batch monitoring action for the states of input and output signals which are controlled by a peripheral device performing the programming operation, by reading periodically the state of a signal input or output terminal out of an arithmetic means via an interface part and then writing these read-out states of the terminal to a display memory. CONSTITUTION:When a monitor request is received, a central processing part 6a of a peripheral device 6 reads the states of input and output signals received periodically from a PCS and write them to a display memory 6c via an interface part 6f. The contents written to the memory 6c are automatically displayed on a plane display part 6b a display controller 6d in response to the array of the signal input and output terminals. In this case, however, it is hard to display several thousands of input and output signals on the part 6b, e.g., a CRT at one time owing to the display capacity of the part 6b. Therefore the CRT screen is scrolled for display. Thus it is possible to collectively monitor the states of input and output signals through the device 6 in the image of a terminal board of an input/output module.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention particularly relates to a programmable sequence controller (hereinafter simply referred to as PCS) having a display function for displaying the input/output status of signals on a peripheral device. ).

[Conventional technology]

LE displays the signal input/output status of pQs.
There are two types of display: one based on cold cathode discharge tubes (hereinafter simply referred to as RT).The latter is displayed using a ladder diagram, and the volatility is determined according to the input/output status of the signal. Instead, it was displayed.

In addition, as a device for displaying signal input/output status, JP-A-58-
No. 132809, Japanese Patent Application Publication No. 58-94011, Japanese Patent Application Publication No. 1973
8-78207 etc.

[Problem that the invention seeks to solve]

In the case of display using LEDs, if a few of the LEDs become defective, it is not easy to determine whether there is no signal and the LEDs do not emit light, or whether they are defective and do not emit light.

On the other hand, in the case of a CRT, only a small portion of the circuit can be displayed on one screen.

The present invention has been made in view of these points, and its purpose is to display images on one screen even though a surface display such as a CRT or a liquid crystal display is used as the display means. The purpose is to be able to display many signal input/output states.

[Means for solving problems]

That is, in the present invention, a peripheral device that is a component of a PCS includes a display memory that stores the state of a signal input terminal or a signal output terminal in advance, a surface display section that displays according to the contents of the display memory, and a display memory that stores the state of a signal input terminal or a signal output terminal in advance. a display controller unit configured to display content on the screen display unit in accordance with the arrangement of the signal input terminals and the signal output terminals; and a display controller unit configured to control a display unit to display content on the screen display unit in accordance with the arrangement of the signal input terminals and the signal output terminals; an interface section for exchanging data and programs, and a central processing section for periodically reading the state of the signal input terminal or signal output terminal from the calculation means via the interface section and writing it to the display memory. to have. For example, a cold cathode discharge tube or a liquid crystal display can be used as the surface display section.

[Effect]

When a request to display the status of input/output signals, that is, to monitor, comes, the central processing unit 6a in the peripheral device 6.

The status of input/output signals periodically sent out by the PC 8 is read via the interface section 6f, and the status is stored in the display memory 6.
6. Contents written in the display memory 6C are automatically displayed on the surface display section 6b by the display controller 6d in correspondence with the arrangement of the signal input terminals and signal output terminals.

The problem here is the display capability of the screen display section 6b; in the case of a PAS that controls several thousand input/output signals, it is difficult to display this all at once on the screen display section, for example, a CRT. .

Therefore, the screen is scrolled and displayed as shown in FIG. 3, for example. By doing so, it becomes possible to monitor the status of input/output signals all at once from the peripheral device using the image of the terminal block of the input/output module.

〔Example〕

Embodiments of the present invention shown in the figures will be described below.

FIG. 2 is an overall view showing one form of the module type PC3. This controller includes a power supply unit indicated by 1,
and a central processing unit indicated by 2.

Input modules shown as 3a, 3b... and 4a.

It is composed of an output module indicated by 4b... and a peripheral device indicated by 6.

The power supply unit 1 receives commercial power and supplies it to the central processing unit 2 and input/output modules 3a3b...4.
Replace a, 4b... to the voltage level required,
It is configured to supply backup power for rectification or for holding the user program written in the user program storage means 2b when the commercial power supply is out of power. Central processing unit 2 and input
The output modules 3a, 3b, . . . 4a, 4b, . . . are connected in parallel to the parallel I10 bus 5. In addition,@
Figure 1 shows a state where only one input module and one output module, that is, only 3a and 4a are connected in parallel to the parallel I10 bus 5, and the other modules 3b,
3c...4b, 4c. are omitted from illustration.

The central processing unit 2 includes a calculation means 2a, a user program storage means 2b, and a system program storage means 2.
C and 1 peripheral device interface section 2d and timer section 2
It has e.

A sequence program written by the user is written into the user program storage means 2b, and a sequence program written by the user is written into the system program storage means 2C.

The 6-peripheral device interface section 2d, in which a system program necessary for operating the controller according to the sequence program is written, is a place for exchanging data and programs with the peripheral device 6.

The calculation means 2a calculates the input of the signal input terminal and, in some cases, the output of the signal output terminal as variables, based on the user program, and outputs a signal according to the calculation result to a predetermined signal output terminal, When a monitor command is received from the device 6, the status of the input/output signal to be monitored is periodically sent to the peripheral device via the peripheral device interface 2d under the time management of the timer section 2e.

The peripheral device 6 includes a central processing section 6a, a one-screen display section 6b, a display memory 6c, a one-display controller 6d, a key input section 6e, and an interface section 6f.

When a monitor is requested from the key human power section 6e, the central processing section 6
A detects this, reads the state of the input/output signal sent from the central processing unit 2 via the interface section 6f at regular intervals determined by the timer section 2e, and stores it in the display memory 6C. The display controller 6d automatically and repeatedly displays the pig written in the display memory 6C on the screen display section 6b at regular intervals.The display section 6b has a terminal as shown in FIG. Displays the 0N10FF status of the input/output signal with the image of a stand.

FIG. 4 shows an example of an address map within one peripheral device when the screen is scrolled.

The memory 6C shown here contains the status of all input/output signals (
(Figure 6a) When the 1-display controller displays on the screen, all you have to do is specify where the upper left position of the 1-screen is on this display memory (Fig. 6a) FIG. 6 shows an example when the upper left position of the screen is set to SAI and SA2.

(shown in C), to scroll the screen there.

All you have to do is move these addresses (SAI and 5A2) in order.

Next, we will discuss how to display the ○N/○FF status of each input/output signal.
I have a 6h CG memory with patterns written on it. Here is the character pattern (Fig. 5) corresponding to the input/output status ○N/○FF.

I have separate ON and OFF. Then, when a monitor request comes to the peripheral device, the central processing unit 6a determines the status of each input/output signal (which input/output signal is ON/OFF).
The character pattern in the CG memory corresponding to the CG memory is written to the corresponding location in the display memory. Here, the 1 display controller displays the specified display location in the display memory on the screen at a certain fixed time interval. Therefore, the ON/FF status of the target input/output signal can be monitored on the screen.

Therefore, by adopting such a configuration and display method, the operator can collectively monitor the status of the input/output signals to be controlled using the peripheral device for programming.

〔Effect of the invention〕

According to the present invention, as is clear from the above description, the operator (designer/maintenance person) collectively monitors the status of input/output signals controlled using peripheral devices using programming. becomes possible.

[Brief explanation of drawings]

The figures show an embodiment of the programmable sequence controller of the present invention, in which Fig. 1 is a block diagram thereof, Fig. 2 is an overall view, Fig. 3 is a display example of the display section, and Fig. 4 is an address map of peripheral devices. Figure 5 shows “1” ○N/○FF pattern,
FIG. 6 is a diagram showing the correspondence between display memory and screen. 1: Power supply unit, 2: Central processing unit. 3a, 3b...: Human power module, 4a, 4b...: Output module, 5: Parallel I10 bus, 6: Peripheral device,
2a: calculation means, 2b=user program storage means, 2
c system program storage means, 2d: peripheral device interface section, 2e: timer section, 6a: central processing section,
6b: Display unit, 6c: Display memory, 6d: Display controller 6e: Key power unit, 6f: Interface unit, 6
g = System program storage means - 6h: CG memory $ 1st #2th! vJ Prisoner 44 Hard 7 Do Sumatu γ ”/=/) fFF pattern ’I”/IrPN putter〉6th mouth (Q-) Tablework〆Gonokai Isakaguchi

Claims (1)

[Claims] 1. A plurality of signal input terminals, a plurality of signal output terminals, a user program storage means, a system program storage means, a peripheral device for programming the user program storage means, and the system program storage means. Under the jurisdiction of the system program stored in the means, the input of the signal input terminal is calculated as a variable based on the user program stored in the user program storage means, and a signal according to the calculation result is generated. a calculation means for outputting to the signal output terminal; a display memory for storing the state of the signal input terminal or the signal output terminal in advance; a surface display section for displaying according to the contents of the display memory; and contents stored in the display. a display controller unit that controls the screen display unit to display the data in accordance with the arrangement of the signal input terminals and the signal output terminals; and data and data between the calculation means, the user program storage means, etc., and the display memory. The present invention includes an interface section for exchanging programs, and a central processing section that periodically reads the state of the signal input terminal or the signal output terminal from the calculation means via the interface section and writes it to the display memory. Features programmable, sequence, controller. 2. The programmable device according to claim 1, wherein a cold cathode discharge tube is used as the surface display section.
sequence, controller. 3. The programmable sequence controller according to claim 1, wherein a liquid crystal display is used as the surface display section.