JPS6227553B2 - - Google Patents
Info
- Publication number
- JPS6227553B2 JPS6227553B2 JP14140185A JP14140185A JPS6227553B2 JP S6227553 B2 JPS6227553 B2 JP S6227553B2 JP 14140185 A JP14140185 A JP 14140185A JP 14140185 A JP14140185 A JP 14140185A JP S6227553 B2 JPS6227553 B2 JP S6227553B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor
- rectifier
- layer
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 115
- 239000012535 impurity Substances 0.000 claims description 9
- 239000013078 crystal Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000011084 recovery Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000006798 recombination Effects 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000005215 recombination Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 that is Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体整流装置の改良に関する。更
に詳しくは、高い逆方向耐圧を保ちながら順方向
電圧降下を低下させた半導体整流装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in semiconductor rectifier devices. More specifically, the present invention relates to a semiconductor rectifier that reduces forward voltage drop while maintaining high reverse breakdown voltage.
（従来の技術）
半導体整流装置として、従来、第２図を伴なつ
て次に述べる構成を有するものが提案されてい
る。(Prior Art) Conventionally, a semiconductor rectifier having the configuration described below with reference to FIG. 2 has been proposed.
すなわち、例えば５×1018atom／cm3以上のよう
な高い不純物濃度を有し且つ例えばN+型を有す
る半導体層１と、その半導体層１上に形成されて
いるとともに、例えば５×1016atom／cm3以下のよ
うな半導体層１に比し低い不純物濃度を有し且つ
P-型を有する半導体層２と、その半導体層２の
半導体層１とは反対側に形成されているとともに
例えば５×1018atom／cm3以上のような高い不純物
濃度を有し且つP+型を有する半導体層３とを有
する。 That is, a semiconductor layer 1 having a high impurity concentration of, for example, 5×10 18 atoms/cm 3 or more and having, for example, N + type, is formed on the semiconductor layer 1, and is formed on the semiconductor layer 1, for example, 5×10 16 It has a lower impurity concentration than the semiconductor layer 1, such as atoms/cm 3 or less, and
A semiconductor layer 2 having a P - type is formed on the opposite side of the semiconductor layer 1 from the semiconductor layer 1, and has a high impurity concentration of, for example, 5×10 18 atoms/cm 3 or more, and has a P + It has a semiconductor layer 3 having a mold.
また、半導体層１の半導体層２側とは反対側に
オーミツクに付されている電極４と、半導体層３
の半導体層２側とは反対側にオーミツクに付され
ている電極５とを有する。 Further, an electrode 4 attached to the ohmic on the side opposite to the semiconductor layer 2 side of the semiconductor layer 1 and the semiconductor layer 3
It has an electrode 5 attached to the ohmic on the side opposite to the semiconductor layer 2 side.
以上が、従来提案されている半導体整流装置の
構成である。 The above is the configuration of a conventionally proposed semiconductor rectifier.
このような構成を有する半導体整流装置は、所
謂PIN型ダイオード構成を有する半導体整流装置
である。 A semiconductor rectifier having such a configuration is a semiconductor rectifier having a so-called PIN diode configuration.
ところで、このような構成を有する半導体整流
装置によれば、その電極４及び５間に、電極５側
を正とする電圧が与えられた場合、半導体領域１
側から半導体層２側に電子が注入され、この電子
の電荷を中和するために、半導体層３側から、半
導体層２側に正孔が供給される機構で、電極４及
び５間が導通状態となる。 By the way, according to the semiconductor rectifier having such a configuration, when a voltage is applied between the electrodes 4 and 5 with the electrode 5 side being positive, the semiconductor region 1
Electrons are injected from the side to the semiconductor layer 2 side, and in order to neutralize the charge of the electrons, holes are supplied from the semiconductor layer 3 side to the semiconductor layer 2 side, and conduction occurs between the electrodes 4 and 5. state.
また、このような状態から、電極４及び５間に
電極５側を負とする電圧が与えられた場合、電極
４及び５間が不導通状態になる。 Further, in such a state, if a voltage is applied between the electrodes 4 and 5 such that the electrode 5 side is negative, the electrodes 4 and 5 become non-conductive.
従つて、第２図に示す半導体整流装置は、整流
装置としての機能を呈する。 Therefore, the semiconductor rectifier shown in FIG. 2 functions as a rectifier.
（発明が解決しようとする問題点）
しかし、このような従来の半導体整流装置の場
合、半導体層３は上述した導通状態が得られたと
き、上述したように半導体層２側に、正孔を供給
する作用を行つていると同時に、半導体層２に、
半導体層１側から注入された電子を吸収する作用
を行つている。この場合、半導体層３及び半導体
層２間には、半導体層３から半導体層２側に向う
正孔に対する電位障壁は存在しない。しかしなが
ら、P-P+接合があるので、半導体層２から半導
体層３側に向う電子に対する電位障壁が存在す
る。(Problems to be Solved by the Invention) However, in the case of such a conventional semiconductor rectifier, when the above-mentioned conductive state is obtained, the semiconductor layer 3 releases holes to the semiconductor layer 2 side as described above. At the same time as supplying the semiconductor layer 2,
It functions to absorb electrons injected from the semiconductor layer 1 side. In this case, there is no potential barrier between the semiconductor layer 3 and the semiconductor layer 2 for holes moving from the semiconductor layer 3 toward the semiconductor layer 2 side. However, since there is a P - P + junction, a potential barrier exists for electrons moving from the semiconductor layer 2 toward the semiconductor layer 3 side.
換言すれば半導体層３は、半導体層１側より注
入された半導体層２中の電子を吸収する能力が低
いことになる。このため、半導体層１から半導体
層２に注入された電子は、電極５への到達がさま
たげられる傾向にあり、また半導体層２の中に電
子が蓄積する。 In other words, the semiconductor layer 3 has a low ability to absorb electrons in the semiconductor layer 2 injected from the semiconductor layer 1 side. Therefore, electrons injected from the semiconductor layer 1 to the semiconductor layer 2 tend to be prevented from reaching the electrode 5, and electrons are accumulated in the semiconductor layer 2.
従つて、上述した半導体整流装置の場合、その
導通時における電極４及び５間の電圧即ち順方向
降下電圧が、比較的大であると共に、導通状態か
ら電極４及び５間に与える電圧を遮断することに
よつて不導通状態に回復する時の、その回復迄に
要する時間即ち逆方向回復時間が比較的長い、と
いう欠点を有する。 Therefore, in the case of the semiconductor rectifier described above, the voltage between the electrodes 4 and 5 when the device is conductive, that is, the forward voltage drop, is relatively large, and the voltage applied between the electrodes 4 and 5 is cut off from the conductive state. This has the drawback that the time required to recover from the non-conducting state, that is, the reverse recovery time is relatively long.
（問題点を解決するための手段）
このような問題点を解決するため、本発明は従
来と同じ導通型の素子として例示するならば、
P+形単結晶の面積をダイオード面積より少なく
し、かつ複数領域に分割して形成するとともに、
これら複数のP+形単結晶領域及びこれらが形成
されていないP-形単結晶半導体の上面に、オー
ミツクに連結して形成された高濃度P+形多結晶
半導体層を設け、多結晶半導体と単結晶半導体境
界面が、少数キヤリアたる電子を多結晶半導体中
に導くバンド構造であり、かつ多結晶半導体の結
晶粒界には高密度の再結合中心であることから、
電子吸収作用を有する点に着目し、これを電子吸
込層として動作させることにより順方向降下電圧
を小となすことを特徴とするものである。(Means for Solving the Problems) In order to solve these problems, the present invention is exemplified as a conduction type element like the conventional one.
By making the area of the P + type single crystal smaller than the diode area and dividing it into multiple regions,
A high concentration P + type polycrystalline semiconductor layer formed in an ohmic connection is provided on the upper surface of the plurality of P + type single crystal regions and the P - type single crystal semiconductor where these regions are not formed, and the polycrystalline semiconductor and polycrystalline semiconductor layers are formed. Since the single-crystal semiconductor interface has a band structure that guides minority carrier electrons into the polycrystalline semiconductor, and the grain boundaries of the polycrystalline semiconductor have a high density of recombination centers,
It is characterized by focusing on the fact that it has an electron absorption effect, and by operating it as an electron absorption layer, the forward voltage drop can be reduced.
（実施例）
第１図は、本願発明による半導体整流装置の特
徴を最もよく示した実施例である。(Example) FIG. 1 is an example that best illustrates the characteristics of the semiconductor rectifier according to the present invention.
第２図との対応部分には同一符号を付して示
す。 Components corresponding to those in FIG. 2 are designated by the same reference numerals.
第１図に示す本発明による半導体装置は、次に
述べる構成を有する。 The semiconductor device according to the present invention shown in FIG. 1 has the configuration described below.
すなわち、第２図で上述したと同様のN+型を
有する半導体層１と、
P-型を有する半導体層２とを有する。 That is, it has a semiconductor layer 1 having an N + type and a semiconductor layer 2 having a P - type similar to that described above in FIG.
また、半導体層２の半導体層１側とは反対側に
局部的に形成された、半導体層２に比し高い不純
物濃度を有し且つP+導電型を有する複数の半導
体領域１３を有する。この半導体領域１３は、半
導体層２に第１の電荷符号を有するキヤリアすな
わち正孔を供給する作用を行う領域として形成さ
れている。 Further, a plurality of semiconductor regions 13 having an impurity concentration higher than that of the semiconductor layer 2 and having a P + conductivity type are formed locally on the side of the semiconductor layer 2 opposite to the semiconductor layer 1 side. This semiconductor region 13 is formed as a region that functions to supply carriers, that is, holes having a first charge sign to the semiconductor layer 2 .
さらに、半導体層１の半導体層２側とは反対側
上にオーミツクに付されている電極４を有する。 Further, an electrode 4 is provided on the side of the semiconductor layer 1 opposite to the semiconductor layer 2 side, which is attached to an ohmic.
なおさらに、高不純物濃度のP+形多結晶（単
結晶領域と同一物質のもの、例えばシリコン）半
導体でなる層２０が半導体領域１３と、半導体層
２のP+形半導体領域１３の形成されていない領
域とに連結して形成され、従つて、P+多結晶半
導体（例えばシリコン）２０とP-単結晶半導体
（例えばシリコン）２の境界１６を形成し、又多
結晶半導体層２０の半導体層２とは反対側上に電
極１５がオーミツクに付されている。 Furthermore, the semiconductor region 13 and the P + type semiconductor region 13 of the semiconductor layer 2 are formed by a layer 20 made of a highly impurity-concentrated P + type polycrystalline (same material as the single crystal region, for example, silicon) semiconductor. 2, and thus forms a boundary 16 between the P + polycrystalline semiconductor (e.g., silicon) 20 and the P - single-crystalline semiconductor (e.g., silicon) 2, and also forms a semiconductor layer of the polycrystalline semiconductor layer 20. On the side opposite to 2, an electrode 15 is attached to the ohmic.
このような構成によれば、電極４及び１５間に
電極１５側を正とする電圧が与えられた場合、半
導体層１及び２、及び半導体領域１３が、夫々第
２図の半導体整流装置の半導体層１及び２、及び
半導体層３に対応し、また、電極４及び１５が第
２図の半導体整流装置の電極４及び５に対応して
いるので、半導体領域１側から、半導体層２内に
電子が注入され、また、半導体層１３側から半導
体層２内に正孔が供給される機構で電極４及び１
５間が導通状態となる。 According to such a configuration, when a voltage is applied between the electrodes 4 and 15 with the electrode 15 side being positive, the semiconductor layers 1 and 2 and the semiconductor region 13 are respectively connected to the semiconductor rectifying device of FIG. Since the electrodes 4 and 15 correspond to the electrodes 4 and 5 of the semiconductor rectifier shown in FIG. The electrodes 4 and 1 have a mechanism in which electrons are injected and holes are supplied from the semiconductor layer 13 side into the semiconductor layer 2.
5 becomes conductive.
また、このような状態から、電極４及び１５間
に、電極１５側を負とする電圧が与えられた場
合、電極４及び１５間は不導電状態になる。 Further, in such a state, if a voltage is applied between the electrodes 4 and 15 with the electrode 15 side being negative, the electrodes 4 and 15 become non-conductive.
従つて、第２図の半導体整流装置の場合と同様
に、整流装置としての機能を呈する。 Therefore, like the semiconductor rectifier shown in FIG. 2, it functions as a rectifier.
然し乍ら、第１図に示す本発明による半導体整
流装置の実施例の場合、半導体領域１３のほかに
これと並置している電子を吸収する作用を行う
『P+多結晶半導体層２０とP-単結晶半導体２との
境界１６』を有するので、上述した導通状態が得
られているとき、上記境界１６が半導体層１側か
ら半導体層２内に注入される電子を吸収する作用
を行う。この動作原理を、半導体がシリコンであ
る場合を例にとつて説明する。単結晶上に堆積さ
れた多結晶シリコンは第３図に図示するように
結晶粒が重なつた構造となり、均一な層が積層す
るものではない。ここで、単結晶上に堆積された
多結晶シリコン及び単結晶をABで切つたとき、
その断面に沿つてみたバンド構造は第３図のよ
うになる。粒界部分ａ〜ｅ及び多結晶と単結晶の
境界が、半導体がＰ型ならばバンドが第３図に
示すように下に曲り、ｎ型ならば逆に上に曲がる
ことが知られている。多結晶シリコン中の各結晶
粒、及び粒界部のバンド構造が、第３図のよう
になることは、例えばジヤーナル・オブ・アプラ
イド・フイジツクスの1983年第54巻第1976頁〜
1980頁に記載されたトンプソンらの論文「エフエ
クツ・オブ・インターフエイス・ポテンシヤル・
ノンユニフオーミテイー・オン・キヤリヤ・トラ
ンスポート・アクロス・シリコン・グレイン・バ
ンダリーズ」（Journal of Applied Physics
vol54 No.４ PP1976〜1980（1983）；D.J.
Thompson“Effects of interface−potential
nonuniformities on carrier transport across
silicon grain boundaries”）の第１図ａ（Fig1
(a)）から論理的に導かれる。 However, in the case of the embodiment of the semiconductor rectifying device according to the present invention shown in FIG . Since the semiconductor layer 1 has a boundary 16 with the crystalline semiconductor 2, the boundary 16 acts to absorb electrons injected into the semiconductor layer 2 from the semiconductor layer 1 side when the above-mentioned conductive state is obtained. This principle of operation will be explained using an example in which the semiconductor is silicon. Polycrystalline silicon deposited on a single crystal has a structure in which crystal grains overlap, as shown in FIG. 3, and the layers are not uniformly laminated. Here, when the polycrystalline silicon deposited on the single crystal and the single crystal are cut at AB,
The band structure seen along the cross section is shown in Figure 3. It is known that if the semiconductor is P-type, the band will bend downwards as shown in Figure 3, and if the semiconductor is N-type, the band will bend upwards at the grain boundary parts a to e and the boundary between polycrystal and single crystal. . The band structure of each crystal grain and grain boundary in polycrystalline silicon is as shown in Figure 3, for example, as described in Journal of Applied Physics, 1983, Volume 54, Page 1976.
Thompson et al.'s paper “Effects of Interface Potential” published on page 1980.
“Nonuniformity on Carrier Transport Across Silicon Grain Bandages” (Journal of Applied Physics)
vol54 No.4 PP1976-1980 (1983); DJ
Thompson “Effects of interface−potential
nonuniformities on carrier transport across
Fig. 1 a (Fig. 1
It follows logically from (a)).
なおかつ、上記単結晶と多結晶の境界面、及び
多結晶内の粒界部には、高密度の再結合中心（界
面準位）が存在し、ライフタイムが短い再結合中
心となつて少数キヤリアを再結合させる作用があ
り、具体的にはライフタイムが数ps〜数nsと非
常に短時間で少数キヤリアをほとんど再結合させ
てしまうことが、例えばアイ・イー・イー・イ
ー、トランザクシヨン・オン・イー・デイーの
1977年第1025〜1031頁に記されたリーブリツヒら
の論文「ア・ポリシリコン−シリコン−エヌ・ピ
ージヤンクシヨン）（IEEE.Trans on ED vol
ED−24 No.８ PP1025〜1031、1977；Z.
Lieblich“Ａ Polysilicon−Silicon ｎ−Ｐ
Junction”）の第１０図（Fig10）に示されてい
る。即ち、再結合中心のライフタイムと、その結
晶でｐ−ｎ接合を作り、その接合部のライフタイ
ムを実測した結果とは、ほぼ等しくなる（高々約
1/2〜約２倍のちがい）ということが、本技術分
野で周知であるので上記Fig10より再結合中心の
ライフタイムも、やはり数ピコ〜数ナノ秒と非常
に短いことがわかる。従つて、第３図に示すよう
に、Ｐ形単結晶側から電子が多結晶方向に流れて
くると（で示す）多結晶との境界、若しくは境
界からわずかに入つた多結晶中の再結合中心を介
して急速に再結合する（、）。即ち、境界１
６は電子を吸収する作用を有する。（多結晶と単
結晶がｎ形のときは正孔吸収の作用を有する。）
このため、第２図で上述した半導体整流装置と
比較した場合、半導体層１から半導体層２に注入
された電子は、P+形多結晶シリコン層２０に容
易に注入することができ、またそのため半導体層
２の中に電子が蓄積する量は無視し得る程度に小
である。 Furthermore, there are high-density recombination centers (interface states) at the interface between the single crystal and polycrystal, as well as at the grain boundaries within the polycrystal, and these recombination centers have a short lifetime and become minority carriers. Specifically, most of the minority carriers are recombined in a very short time with a lifetime of several ps to several ns. On E.D.
Liebrich et al., 1977, pp. 1025-1031, “A Polysilicon-N.P. Yankee” (IEEE. Trans on ED vol.
ED-24 No.8 PP1025-1031, 1977; Z.
Lieblich“A Polysilicon-Silicon n-P
In other words, the lifetime of the recombination center and the result of making a p-n junction with the crystal and actually measuring the lifetime of the junction are approximately the same. be equal (at most about
Since it is well known in this technical field that the difference is 1/2 to about 2 times, it can be seen from Fig. 10 above that the lifetime of the recombination center is also very short, ranging from several picoseconds to several nanoseconds. Therefore, as shown in Figure 3, when electrons flow from the P-type single crystal side toward the polycrystal, they recombine at the boundary with the polycrystal (indicated by ) or within the polycrystal that slightly enters from the boundary. rapidly recombining through the center (,). That is, boundary 1
6 has the function of absorbing electrons. (When polycrystal and single crystal are n-type, they have a hole absorption effect.) Therefore, when compared with the semiconductor rectifier device described above in FIG. can be easily injected into the P + type polycrystalline silicon layer 20, and therefore the amount of electrons accumulated in the semiconductor layer 2 is negligibly small.
従つて、第１図に示す本発明による半導体整流
装置の実施例の場合、その導通時における電極４
及び１５間の電圧すなわち順方向降下電圧が、第
２図で上述した従来の半導体整流装置の場合に比
し、格段的に小であるとともに、導通状態から、
電極４及び１５間に与える電圧を遮断することに
よつて不導通状態に回復するまでの時間、すなわ
ち逆方向回復時間が、第２図で上述した従来の半
導体整流装置の場合に比し、格段的に短いという
特徴を有する。 Therefore, in the case of the embodiment of the semiconductor rectifier according to the invention shown in FIG.
The voltage between
The time taken to restore the non-conducting state by cutting off the voltage applied between the electrodes 4 and 15, that is, the reverse recovery time, is significantly shorter than that of the conventional semiconductor rectifier described above in FIG. It has the characteristic of being relatively short.
上述の効果を実証するために、第２図に示す従
来構造及び第１図に示す本発明の構造を有する電
力整流用ダイオードをそれぞれ試作し、逆方向回
復時間を実測した。それぞれのダイオードにおい
て、N+層は500μｍの厚さで、0.01Ωcm、P-層は
15μｍの厚さで５Ωcmとした。又、従来構造にお
けるP+層は0.5μｍ厚の単結晶で不純物濃度が
1019cm-3の層を用いた。一方、本発明の構造にお
いて、P+層２０はボロンをドープした多結晶シ
リコンを用い不純物濃度は２×1020cm-3の層を用
い、部分的に存在するP+領域１３は0.1μｍの厚
さの拡散領域（不純物濃度1019cm-3）を用いた。
両者の逆方向回復時間を実測したところ第４図に
示すように、従来構造が約0.6μｓであつたのに
対し（第４図ａ）、本発明の構造では約70nsであ
り（第４図ｂ）、約１桁高速に動作することが確
認できた。 In order to demonstrate the above-mentioned effect, power rectifying diodes having the conventional structure shown in FIG. 2 and the structure of the present invention shown in FIG. 1 were manufactured as prototypes, and the reverse recovery time was actually measured. In each diode, the N + layer is 500μm thick, the P− layer is 0.01Ωcm, and the P− layer is 0.01Ωcm thick.
The thickness was 15μm and the resistance was 5Ωcm. In addition, the P + layer in the conventional structure is a 0.5 μm thick single crystal with a low impurity concentration.
A layer of 10 19 cm -3 was used. On the other hand, in the structure of the present invention, the P + layer 20 is made of boron-doped polycrystalline silicon with an impurity concentration of 2×10 20 cm -3 , and the partially existing P + region 13 has a thickness of 0.1 μm. A thick diffusion region (impurity concentration 10 19 cm -3 ) was used.
When we actually measured the reverse recovery time for both, as shown in Figure 4, it was approximately 0.6 μs for the conventional structure (Figure 4 a), while it was approximately 70 ns for the structure of the present invention (Figure 4). b), it was confirmed that it operated approximately one order of magnitude faster.
なお、上述においては、本発明の僅かな実施例
を示したに留まり、例えば、上述せる実施例にお
いて、「N+」を「P+」、「P-」を「N-」、「P+」を
「N+」、電子を正孔、正孔を電子に読替えた構成
とすることもでき、その他、本発明の精神を脱す
ることなしに、種々の変型、変更をなし得るであ
ろう。 In the above description, only a few embodiments of the present invention have been shown. For example, in the embodiments described above, "N + " is replaced by "P + ", "P - " is replaced by "N - ", "P + "" may be replaced with "N + ", electrons may be replaced with holes, and holes may be replaced with electrons, and various other modifications and changes may be made without departing from the spirit of the present invention. .
（発明の効果）
以上説明したように、本発明によれば順方向電
圧降下が小さく、整流効率が高く、更に逆方向回
復時間の短縮化が可能なPIN型ダイオードを簡単
な構造で実現することができる。(Effects of the Invention) As explained above, according to the present invention, it is possible to realize a PIN diode with a simple structure, which has a small forward voltage drop, high rectification efficiency, and shortens the reverse recovery time. I can do it.
第１図は、本願発明による半導体整流装置の実
施例を示す略線的断面図である。第２図は、従来
の半導体整流装置を示す略線的断面図である。第
３図は単結晶上の多結晶シリコン層の形態を説
明する概念図。第３図は、のABに沿つたバ
ンド構造及び少数キヤリア（電子）吸収作用の説
明図。第４図ａ，ｂは、それぞれ従来構造及び本
発明の構造で試作した電力整流用ダイオードの逆
方向回復時間の実測波形。
１……N+半導体層、２……P-半導体層、３，
１３……P+半導体層（半導体領域）、４，５，１
５……電極、１６……P+多結晶とP-単結晶の境
界、２０……P+多結晶半導体、ａ，ｂ，ｃ，
ｄ，ｅ……多結晶内の結晶粒界。
FIG. 1 is a schematic cross-sectional view showing an embodiment of a semiconductor rectifier according to the present invention. FIG. 2 is a schematic cross-sectional view showing a conventional semiconductor rectifier. FIG. 3 is a conceptual diagram explaining the form of a polycrystalline silicon layer on a single crystal. Figure 3 is an explanatory diagram of the band structure along AB and minority carrier (electron) absorption effect. FIGS. 4a and 4b show actually measured waveforms of the reverse recovery time of power rectifier diodes prototyped with the conventional structure and the structure of the present invention, respectively. 1...N + semiconductor layer, 2...P - semiconductor layer, 3,
13...P + semiconductor layer (semiconductor region), 4, 5, 1
5... Electrode, 16... Boundary between P + polycrystal and P - single crystal, 20... P + polycrystalline semiconductor, a, b, c,
d, e: Grain boundaries within the polycrystal.
Claims (1)
１の半導体層に比し低い不純物濃度を有し且つ第
１の導電型とは逆の第２の導電型を有する第２の
半導体層と、 該第２の半導体層の上記第１の半導体層側とは
反対側に、局部的に形成された、上記第２の半導
体層に比し高い不純物濃度を有し且つ第２の導電
型を有する半導体領域と、 上記第１の半導体層の上記第２の半導体層側と
は反対側上にオーミツクに附された第１の電極
と、 上記第２の半導体層の上記第１の半導体層側と
は反対側上に、上記半導体領域と、上記第２の半
導体層の上記半導体領域の形成されていない領域
とにオーミツクに連結して形成された、第２の導
電型を有する多結晶半導体層と、 上記多結晶半導体層上にオーミツクに付された
第２の電極とを有することを特徴とする半導体整
流装置。[Claims] 1: a first semiconductor layer having a first conductivity type; and having an impurity concentration lower than that of the first semiconductor layer formed on the first semiconductor layer; a second semiconductor layer having a second conductivity type opposite to the first conductivity type, and locally formed on a side of the second semiconductor layer opposite to the first semiconductor layer side; a semiconductor region having a higher impurity concentration than the second semiconductor layer and a second conductivity type; and an ohmic semiconductor region on a side of the first semiconductor layer opposite to the second semiconductor layer side. the first electrode, the semiconductor region on the side of the second semiconductor layer opposite to the first semiconductor layer, and the region of the second semiconductor layer where the semiconductor region is not formed. A semiconductor rectifier comprising: a polycrystalline semiconductor layer having a second conductivity type formed in an ohmic connection with the polycrystalline semiconductor layer; and a second electrode attached to an ohmic on the polycrystalline semiconductor layer. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14140185A JPS6139575A (en) | 1985-06-27 | 1985-06-27 | Semiconductor rectifying equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14140185A JPS6139575A (en) | 1985-06-27 | 1985-06-27 | Semiconductor rectifying equipment |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11321679A Division JPS5637683A (en) | 1979-05-07 | 1979-09-04 | Semiconductor rectifying device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6139575A JPS6139575A (en) | 1986-02-25 |
| JPS6227553B2 true JPS6227553B2 (en) | 1987-06-15 |
Family
ID=15291144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14140185A Granted JPS6139575A (en) | 1985-06-27 | 1985-06-27 | Semiconductor rectifying equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6139575A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3633161A1 (en) * | 1986-09-30 | 1988-04-07 | Licentia Gmbh | SEMICONDUCTOR COMPONENT WITH AN ANODE-SIDED P-ZONE AND A LOW-DOPED N-BASE ZONE |
| KR20010014774A (en) * | 1999-04-22 | 2001-02-26 | 인터실 코포레이션 | Fast Turn-Off Power Semiconductor Devices |
| JP2006086457A (en) * | 2004-09-17 | 2006-03-30 | Matsushita Electric Works Ltd | Magnetic detection device |
| JP5194273B2 (en) * | 2007-09-20 | 2013-05-08 | 三菱電機株式会社 | Semiconductor device |
-
1985
- 1985-06-27 JP JP14140185A patent/JPS6139575A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6139575A (en) | 1986-02-25 |
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