JPS6227478B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a single memory device with redundant configuration.

Currently, improvements in the degree of integration of semiconductor memories are being made mainly by using microfabrication technology, but with the use of microfabrication technology, the percentage of defects caused by dust, etc., which did not pose much of a problem in the past, has increased. , yield tends to decrease. As a result, in order to improve yields, redundant configurations are being adopted in which when a defect exists in a part, the defective part is replaced with a pre-arranged spare part to make it appear that there is no defect. Ta. 1-transistor dynamic with spare decoder and spare cells on the row (ROW) side
Figure 1 shows the block configuration of the RAM decoder, cells, and sense amplifier. For simplicity, the decoder, cell, and sense amplifier are each represented by one circuit.

Memory cells 1 and 11, dummy cells 2 and 12, and spare cells 3 and 13 are arranged above and below the sense amplifier 20, respectively. The memory cells 1 and 11 are connected to the correct and correction bit lines 21 and 22 by word lines 7 and 17 selected by row decoders 4 and 14, respectively, and the dummy cells 2 and
Reference numerals 12 denote dummy word lines 8 and 18 selected by dummy decoders 5 and 15, respectively, which correspond to the above-mentioned correction bit line 2.
1, 22, and further connected to the spare cells 3, 22,
Reference numerals 13 denote spare word lines 9 and 19 selected by spare decoders 6 and 16, which are connected to the positive and complementary bit lines 21 and 22, respectively. The correction bit lines 21 and 22 are connected to the sense amplifier 20.

The operation when reproducing the signal of the memory cell 1 will be briefly explained. The row (ROW) decoder 4 selects the upper word line 7 and transfers the signal of the memory cell 1 to the positive bit line 21, while the dummy decoder 15 selects the lower dummy word line 18 and transfers the signal to the dummy cell 12.
The signal is transmitted to the complementary bit line 22, and the sense amplifier 20 compares both signals to reproduce the memory cell signal. By the way, if there is a defect in the memory cell 1, normal operation cannot be performed, so the memory cell 1 is replaced with a spare cell 3 to avoid this defect. That is, instead of stopping the operation of the ROW decoder 4 and selecting the word line 7,
Select spare word line 9 with spare decoder 6,
The signal of the spare cell 3 and the signal of the dummy cell 12 are compared to reproduce the spare cell signal.

In this way, in the conventional example, the dummy cell selection method is not changed between memory cell selection and spare cell selection, so the upper memory cell 1 is the upper spare cell 3.
Also, the lower memory cell 11 is the lower spare cell 1.
It can only be replaced with 3. Therefore, in order to increase the defect relief rate, it is necessary to arrange a large number of spare decoders and spare cells, which has the disadvantage of increasing the chip area.

An object of the present invention is to provide a memory device in which a memory cell can be replaced with either an upper or a lower spare cell, and which has a high defect repair rate with a small number of spare decoders and spare cells.

According to the present invention, a one-transistor type dynamic circuit is equipped with a PROM element for registering the address signal of a defective word line, a spare decoder for replacing the defective part, a spare cell, and a spare word activation signal generation circuit. When replacing a defective word line with the above spare word line in RAM, by switching the selection of the dummy decoder from address signal control to spare word activation signal control, the defective word line can be replaced with the same block or spare word line. A one-transistor type dynamic RAM is obtained which can be replaced with the spare word line arranged on either side of the other block.

The method of replacing a defective word line will be described in detail below. FIG. 2 shows a conventional example of each decoder, in which a and b are row decoders, c and d are dummy decoders, and e and f are spare decoders. In this example, selection of upper and lower row decoders a, b and dummy decoders c, d is performed using address signals An, n. Also, the address signal of the word line that has a defect and needs to be replaced.
Write to the PROM element, and this written address signal is input to the spare decoder Aop, op, ~,
It is now supplied to Anp and np. On the other hand, if the external address signal and the program address signal written in the PROM element match, that is, to select a defective word line, a spare word activation signal SWE is generated; A spare word activation signal generation circuit is separately provided which does not generate the signal SWE when selecting a line.

When selecting a word line with no defects, the signal SWE is not generated and the address signals Ao, o~
The row decoder and dummy decoder determined by An and n operate, and for example, the row decoder 4 selects the word line 7 and the dummy decoder 15 selects the dummy word line 18.

On the other hand, when selecting a defective word line, the signal SWE is generated to stop the operation of the Row decoder, and instead the program address signal Aop,
A spare decoder determined by op to Anp, np and a dummy decoder determined by address signals An, n operate. For example, the spare decoder 6 selects the spare word line 9 and the dummy decoder 15 selects the dummy word line 18. In this way, in the conventional example, when replacing with a spare, the selection of the dummy decoder is not changed under the control of the address signals An, n, so the upper word line 7 is connected to the upper spare word line 9 and the lower word line. 17 must be replaced by the lower spare word line 19.

An embodiment of the present invention will be explained with reference to FIG.

In Fig. 3, a, b are Row decoders, c,
d indicates a dummy decoder, and e and f indicate logic circuits of spare decoders. In this example as well, selection of the upper and lower row decoders a and b is performed using address signals An and n. On the other hand, upper and lower dummy decoders c,
Selection of d is performed using address signals An, n or spare word activation signals SWE1, SWE2. As in the case of Figure 2, the address signal of the word line that has a defect and needs to be replaced is written into the PROM element, and the written address signal is supplied to the inputs Aop, op to Anp, np of the spare decoder. It's getting old. On the other hand, when the external address signal and the program address signal written in the PROM element match, that is, when selecting a defective word line, the spare word line activation signal SWE1 or SWE2 is generated; In other words, a spare word activation signal generation circuit is separately provided which does not generate the signals SWE1 and SWE2 when selecting a word line with no defects.

When selecting a word line with no defects, signals SWE1 and SWE2 are not generated, and the Row decoder and dummy decoder determined by the address signals Ao, o to An, n operate. For example, Row decoder 4 selects a word line. Line 7 and dummy decoder 15
selects the dummy word line 18.

On the other hand, when selecting a defective word line, the signal SWE1 or SWE2 is generated to stop the operation of the Row decoder, and instead, the spare decoder determined by the program address signals Aop, op to Anp, np operates. , select the spare word line. On the other hand, the dummy decoder outputs the signal SWE1 or SWE.
2, the selection by the address signals An, n is switched to the selection by the signal SWE1 or SWE2, and a dummy word line existing in a block different from the selected spare word line is selected. For example, the spare decoder 16 selects the spare word line 17, and the dummy decoder 5 selects the dummy word line 8.

In this way, in the present invention, when replacing a defective word line with a spare word line, the selection of the dummy decoder is switched from control by address signals An and n to control by signals SWE1 and SWE2, thereby replacing the defective word line with a spare word line. The line can be replaced with either the upper or lower spare word line, and it is possible to increase the relief rate with fewer spare decoders and spare cells.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of a decoder, cell, and sense amplifier, Figure 2 is a diagram showing a conventional example of a row decoder, dummy decoder, and spare decoder, and Figure 3 is a diagram showing the configuration of a decoder, cell, and sense amplifier.
1 is a diagram showing an embodiment of the present invention of a row decoder, a dummy decoder, and a spare decoder. FIG. 1,11...Memory cell, 2,12...Dummy cell, 3,13...Spare cell, 4,14...
Row decoder, 5, 15...dummy decoder,
6, 16... Spare decoder, 7, 17... Word line, 8, 18... Dummy word line, 9, 19...
...Spare word line, 20...Sense amplifier, 2
1, 22...correction bit line.

Claims (1)

[Claims] 1 first and second decoders, first and second dummy decoders that select first and second dummy cells, first and second spare decoders that select first and second spare cells, and first, In the memory device comprising a second spare word activation signal generation circuit and having a correction bit line connected to a sense amplifier,
The dummy decoder includes a first NOR circuit that receives a positive address signal and a second spare activation signal;
a second NOR circuit that receives a first spare activation signal and the output of the first NOR circuit; and a first AND circuit that receives a dummy word activation signal and the output of the second NOR circuit. The second dummy decoder receives the complementary address signal and the first dummy decoder.
a third NOR circuit which inputs the spare activation signal of the second spare activation signal and the third NOR circuit;
a fourth NOR circuit that receives the output of the NOR circuit, a dummy word activation signal, and the fourth NOR circuit;
A memory device comprising a second AND circuit whose input is the output of the circuit.